1/* 2 * linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S 3 * 4 * Copyright (C) 1999-2001 ARM Limited 5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 6 * hacked for non-paged-MM by Hyok S. Choi, 2003. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * 22 * 23 * These are the low level assembler for performing cache and TLB 24 * functions on the arm926. 25 * 26 * CONFIG_CPU_ARM926_CPU_IDLE -> nohlt 27 */ 28#include <linux/linkage.h> 29#include <linux/init.h> 30#include <asm/assembler.h> 31#include <asm/hwcap.h> 32#include <asm/pgtable-hwdef.h> 33#include <asm/pgtable.h> 34#include <asm/page.h> 35#include <asm/ptrace.h> 36#include "proc-macros.S" 37 38/* 39 * This is the maximum size of an area which will be invalidated 40 * using the single invalidate entry instructions. Anything larger 41 * than this, and we go for the whole cache. 42 * 43 * This value should be chosen such that we choose the cheapest 44 * alternative. 45 */ 46#define CACHE_DLIMIT 16384 47 48/* 49 * the cache line size of the I and D cache 50 */ 51#define CACHE_DLINESIZE 32 52 53 .text 54/* 55 * cpu_arm926_proc_init() 56 */ 57ENTRY(cpu_arm926_proc_init) 58 mov pc, lr 59 60/* 61 * cpu_arm926_proc_fin() 62 */ 63ENTRY(cpu_arm926_proc_fin) 64 stmfd sp!, {lr} 65 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE 66 msr cpsr_c, ip 67 bl arm926_flush_kern_cache_all 68 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 69 bic r0, r0, #0x1000 @ ...i............ 70 bic r0, r0, #0x000e @ ............wca. 71 mcr p15, 0, r0, c1, c0, 0 @ disable caches 72 ldmfd sp!, {pc} 73 74/* 75 * cpu_arm926_reset(loc) 76 * 77 * Perform a soft reset of the system. Put the CPU into the 78 * same state as it would be if it had been reset, and branch 79 * to what would be the reset vector. 80 * 81 * loc: location to jump to for soft reset 82 */ 83 .align 5 84ENTRY(cpu_arm926_reset) 85 mov ip, #0 86 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 87 mcr p15, 0, ip, c7, c10, 4 @ drain WB 88#ifdef CONFIG_MMU 89 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 90#endif 91 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 92 bic ip, ip, #0x000f @ ............wcam 93 bic ip, ip, #0x1100 @ ...i...s........ 94 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 95 mov pc, r0 96 97/* 98 * cpu_arm926_do_idle() 99 * 100 * Called with IRQs disabled 101 */ 102 .align 10 103ENTRY(cpu_arm926_do_idle) 104 mov r0, #0 105 mrc p15, 0, r1, c1, c0, 0 @ Read control register 106 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 107 bic r2, r1, #1 << 12 108 mrs r3, cpsr @ Disable FIQs while Icache 109 orr ip, r3, #PSR_F_BIT @ is disabled 110 msr cpsr_c, ip 111 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache 112 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 113 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable 114 msr cpsr_c, r3 @ Restore FIQ state 115 mov pc, lr 116 117/* 118 * flush_user_cache_all() 119 * 120 * Clean and invalidate all cache entries in a particular 121 * address space. 122 */ 123ENTRY(arm926_flush_user_cache_all) 124 /* FALLTHROUGH */ 125 126/* 127 * flush_kern_cache_all() 128 * 129 * Clean and invalidate the entire cache. 130 */ 131ENTRY(arm926_flush_kern_cache_all) 132 mov r2, #VM_EXEC 133 mov ip, #0 134__flush_whole_cache: 135#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 136 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 137#else 1381: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate 139 bne 1b 140#endif 141 tst r2, #VM_EXEC 142 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 143 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 144 mov pc, lr 145 146/* 147 * flush_user_cache_range(start, end, flags) 148 * 149 * Clean and invalidate a range of cache entries in the 150 * specified address range. 151 * 152 * - start - start address (inclusive) 153 * - end - end address (exclusive) 154 * - flags - vm_flags describing address space 155 */ 156ENTRY(arm926_flush_user_cache_range) 157 mov ip, #0 158 sub r3, r1, r0 @ calculate total size 159 cmp r3, #CACHE_DLIMIT 160 bgt __flush_whole_cache 1611: tst r2, #VM_EXEC 162#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 163 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 164 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 165 add r0, r0, #CACHE_DLINESIZE 166 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 167 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 168 add r0, r0, #CACHE_DLINESIZE 169#else 170 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 171 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 172 add r0, r0, #CACHE_DLINESIZE 173 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 174 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 175 add r0, r0, #CACHE_DLINESIZE 176#endif 177 cmp r0, r1 178 blo 1b 179 tst r2, #VM_EXEC 180 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 181 mov pc, lr 182 183/* 184 * coherent_kern_range(start, end) 185 * 186 * Ensure coherency between the Icache and the Dcache in the 187 * region described by start, end. If you have non-snooping 188 * Harvard caches, you need to implement this function. 189 * 190 * - start - virtual start address 191 * - end - virtual end address 192 */ 193ENTRY(arm926_coherent_kern_range) 194 /* FALLTHROUGH */ 195 196/* 197 * coherent_user_range(start, end) 198 * 199 * Ensure coherency between the Icache and the Dcache in the 200 * region described by start, end. If you have non-snooping 201 * Harvard caches, you need to implement this function. 202 * 203 * - start - virtual start address 204 * - end - virtual end address 205 */ 206ENTRY(arm926_coherent_user_range) 207 bic r0, r0, #CACHE_DLINESIZE - 1 2081: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 209 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 210 add r0, r0, #CACHE_DLINESIZE 211 cmp r0, r1 212 blo 1b 213 mcr p15, 0, r0, c7, c10, 4 @ drain WB 214 mov pc, lr 215 216/* 217 * flush_kern_dcache_area(void *addr, size_t size) 218 * 219 * Ensure no D cache aliasing occurs, either with itself or 220 * the I cache 221 * 222 * - addr - kernel address 223 * - size - region size 224 */ 225ENTRY(arm926_flush_kern_dcache_area) 226 add r1, r0, r1 2271: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 228 add r0, r0, #CACHE_DLINESIZE 229 cmp r0, r1 230 blo 1b 231 mov r0, #0 232 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 233 mcr p15, 0, r0, c7, c10, 4 @ drain WB 234 mov pc, lr 235 236/* 237 * dma_inv_range(start, end) 238 * 239 * Invalidate (discard) the specified virtual address range. 240 * May not write back any entries. If 'start' or 'end' 241 * are not cache line aligned, those lines must be written 242 * back. 243 * 244 * - start - virtual start address 245 * - end - virtual end address 246 * 247 * (same as v4wb) 248 */ 249arm926_dma_inv_range: 250#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 251 tst r0, #CACHE_DLINESIZE - 1 252 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 253 tst r1, #CACHE_DLINESIZE - 1 254 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 255#endif 256 bic r0, r0, #CACHE_DLINESIZE - 1 2571: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 258 add r0, r0, #CACHE_DLINESIZE 259 cmp r0, r1 260 blo 1b 261 mcr p15, 0, r0, c7, c10, 4 @ drain WB 262 mov pc, lr 263 264/* 265 * dma_clean_range(start, end) 266 * 267 * Clean the specified virtual address range. 268 * 269 * - start - virtual start address 270 * - end - virtual end address 271 * 272 * (same as v4wb) 273 */ 274arm926_dma_clean_range: 275#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 276 bic r0, r0, #CACHE_DLINESIZE - 1 2771: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 278 add r0, r0, #CACHE_DLINESIZE 279 cmp r0, r1 280 blo 1b 281#endif 282 mcr p15, 0, r0, c7, c10, 4 @ drain WB 283 mov pc, lr 284 285/* 286 * dma_flush_range(start, end) 287 * 288 * Clean and invalidate the specified virtual address range. 289 * 290 * - start - virtual start address 291 * - end - virtual end address 292 */ 293ENTRY(arm926_dma_flush_range) 294 bic r0, r0, #CACHE_DLINESIZE - 1 2951: 296#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 297 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 298#else 299 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 300#endif 301 add r0, r0, #CACHE_DLINESIZE 302 cmp r0, r1 303 blo 1b 304 mcr p15, 0, r0, c7, c10, 4 @ drain WB 305 mov pc, lr 306 307/* 308 * dma_map_area(start, size, dir) 309 * - start - kernel virtual start address 310 * - size - size of region 311 * - dir - DMA direction 312 */ 313ENTRY(arm926_dma_map_area) 314 add r1, r1, r0 315 cmp r2, #DMA_TO_DEVICE 316 beq arm926_dma_clean_range 317 bcs arm926_dma_inv_range 318 b arm926_dma_flush_range 319ENDPROC(arm926_dma_map_area) 320 321/* 322 * dma_unmap_area(start, size, dir) 323 * - start - kernel virtual start address 324 * - size - size of region 325 * - dir - DMA direction 326 */ 327ENTRY(arm926_dma_unmap_area) 328 mov pc, lr 329ENDPROC(arm926_dma_unmap_area) 330 331ENTRY(arm926_cache_fns) 332 .long arm926_flush_kern_cache_all 333 .long arm926_flush_user_cache_all 334 .long arm926_flush_user_cache_range 335 .long arm926_coherent_kern_range 336 .long arm926_coherent_user_range 337 .long arm926_flush_kern_dcache_area 338 .long arm926_dma_map_area 339 .long arm926_dma_unmap_area 340 .long arm926_dma_flush_range 341 342ENTRY(cpu_arm926_dcache_clean_area) 343#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 3441: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 345 add r0, r0, #CACHE_DLINESIZE 346 subs r1, r1, #CACHE_DLINESIZE 347 bhi 1b 348#endif 349 mcr p15, 0, r0, c7, c10, 4 @ drain WB 350 mov pc, lr 351 352/* =============================== PageTable ============================== */ 353 354/* 355 * cpu_arm926_switch_mm(pgd) 356 * 357 * Set the translation base pointer to be as described by pgd. 358 * 359 * pgd: new page tables 360 */ 361 .align 5 362ENTRY(cpu_arm926_switch_mm) 363#ifdef CONFIG_MMU 364 mov ip, #0 365#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 366 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 367#else 368@ && 'Clean & Invalidate whole DCache' 3691: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate 370 bne 1b 371#endif 372 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 373 mcr p15, 0, ip, c7, c10, 4 @ drain WB 374 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 375 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 376#endif 377 mov pc, lr 378 379/* 380 * cpu_arm926_set_pte_ext(ptep, pte, ext) 381 * 382 * Set a PTE and flush it out 383 */ 384 .align 5 385ENTRY(cpu_arm926_set_pte_ext) 386#ifdef CONFIG_MMU 387 armv3_set_pte_ext 388 mov r0, r0 389#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 390 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 391#endif 392 mcr p15, 0, r0, c7, c10, 4 @ drain WB 393#endif 394 mov pc, lr 395 396 __INIT 397 398 .type __arm926_setup, #function 399__arm926_setup: 400 mov r0, #0 401 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 402 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 403#ifdef CONFIG_MMU 404 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 405#endif 406 407 408#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 409 mov r0, #4 @ disable write-back on caches explicitly 410 mcr p15, 7, r0, c15, c0, 0 411#endif 412 413 adr r5, arm926_crval 414 ldmia r5, {r5, r6} 415 mrc p15, 0, r0, c1, c0 @ get control register v4 416 bic r0, r0, r5 417 orr r0, r0, r6 418#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 419 orr r0, r0, #0x4000 @ .1.. .... .... .... 420#endif 421 mov pc, lr 422 .size __arm926_setup, . - __arm926_setup 423 424 /* 425 * R 426 * .RVI ZFRS BLDP WCAM 427 * .011 0001 ..11 0101 428 * 429 */ 430 .type arm926_crval, #object 431arm926_crval: 432 crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134 433 434 __INITDATA 435 436/* 437 * Purpose : Function pointers used to access above functions - all calls 438 * come through these 439 */ 440 .type arm926_processor_functions, #object 441arm926_processor_functions: 442 .word v5tj_early_abort 443 .word legacy_pabort 444 .word cpu_arm926_proc_init 445 .word cpu_arm926_proc_fin 446 .word cpu_arm926_reset 447 .word cpu_arm926_do_idle 448 .word cpu_arm926_dcache_clean_area 449 .word cpu_arm926_switch_mm 450 .word cpu_arm926_set_pte_ext 451 .size arm926_processor_functions, . - arm926_processor_functions 452 453 .section ".rodata" 454 455 .type cpu_arch_name, #object 456cpu_arch_name: 457 .asciz "armv5tej" 458 .size cpu_arch_name, . - cpu_arch_name 459 460 .type cpu_elf_name, #object 461cpu_elf_name: 462 .asciz "v5" 463 .size cpu_elf_name, . - cpu_elf_name 464 465 .type cpu_arm926_name, #object 466cpu_arm926_name: 467 .asciz "ARM926EJ-S" 468 .size cpu_arm926_name, . - cpu_arm926_name 469 470 .align 471 472 .section ".proc.info.init", #alloc, #execinstr 473 474 .type __arm926_proc_info,#object 475__arm926_proc_info: 476 .long 0x41069260 @ ARM926EJ-S (v5TEJ) 477 .long 0xff0ffff0 478 .long PMD_TYPE_SECT | \ 479 PMD_SECT_BUFFERABLE | \ 480 PMD_SECT_CACHEABLE | \ 481 PMD_BIT4 | \ 482 PMD_SECT_AP_WRITE | \ 483 PMD_SECT_AP_READ 484 .long PMD_TYPE_SECT | \ 485 PMD_BIT4 | \ 486 PMD_SECT_AP_WRITE | \ 487 PMD_SECT_AP_READ 488 b __arm926_setup 489 .long cpu_arch_name 490 .long cpu_elf_name 491 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA 492 .long cpu_arm926_name 493 .long arm926_processor_functions 494 .long v4wbi_tlb_fns 495 .long v4wb_user_fns 496 .long arm926_cache_fns 497 .size __arm926_proc_info, . - __arm926_proc_info 498