1/* 2 * linux/arch/arm/mm/arm925.S: MMU functions for ARM925 3 * 4 * Copyright (C) 1999,2000 ARM Limited 5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 6 * Copyright (C) 2002 RidgeRun, Inc. 7 * Copyright (C) 2002-2003 MontaVista Software, Inc. 8 * 9 * Update for Linux-2.6 and cache flush improvements 10 * Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com> 11 * 12 * hacked for non-paged-MM by Hyok S. Choi, 2004. 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 27 * 28 * 29 * These are the low level assembler for performing cache and TLB 30 * functions on the arm925. 31 * 32 * CONFIG_CPU_ARM925_CPU_IDLE -> nohlt 33 * 34 * Some additional notes based on deciphering the TI TRM on OMAP-5910: 35 * 36 * NOTE1: The TI925T Configuration Register bit "D-cache clean and flush 37 * entry mode" must be 0 to flush the entries in both segments 38 * at once. This is the default value. See TRM 2-20 and 2-24 for 39 * more information. 40 * 41 * NOTE2: Default is the "D-cache clean and flush entry mode". It looks 42 * like the "Transparent mode" must be on for partial cache flushes 43 * to work in this mode. This mode only works with 16-bit external 44 * memory. See TRM 2-24 for more information. 45 * 46 * NOTE3: Write-back cache flushing seems to be flakey with devices using 47 * direct memory access, such as USB OHCI. The workaround is to use 48 * write-through cache with CONFIG_CPU_DCACHE_WRITETHROUGH (this is 49 * the default for OMAP-1510). 50 */ 51 52#include <linux/linkage.h> 53#include <linux/init.h> 54#include <asm/assembler.h> 55#include <asm/hwcap.h> 56#include <asm/pgtable-hwdef.h> 57#include <asm/pgtable.h> 58#include <asm/page.h> 59#include <asm/ptrace.h> 60#include "proc-macros.S" 61 62/* 63 * The size of one data cache line. 64 */ 65#define CACHE_DLINESIZE 16 66 67/* 68 * The number of data cache segments. 69 */ 70#define CACHE_DSEGMENTS 2 71 72/* 73 * The number of lines in a cache segment. 74 */ 75#define CACHE_DENTRIES 256 76 77/* 78 * This is the size at which it becomes more efficient to 79 * clean the whole cache, rather than using the individual 80 * cache line maintainence instructions. 81 */ 82#define CACHE_DLIMIT 8192 83 84 .text 85/* 86 * cpu_arm925_proc_init() 87 */ 88ENTRY(cpu_arm925_proc_init) 89 mov pc, lr 90 91/* 92 * cpu_arm925_proc_fin() 93 */ 94ENTRY(cpu_arm925_proc_fin) 95 stmfd sp!, {lr} 96 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE 97 msr cpsr_c, ip 98 bl arm925_flush_kern_cache_all 99 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 100 bic r0, r0, #0x1000 @ ...i............ 101 bic r0, r0, #0x000e @ ............wca. 102 mcr p15, 0, r0, c1, c0, 0 @ disable caches 103 ldmfd sp!, {pc} 104 105/* 106 * cpu_arm925_reset(loc) 107 * 108 * Perform a soft reset of the system. Put the CPU into the 109 * same state as it would be if it had been reset, and branch 110 * to what would be the reset vector. 111 * 112 * loc: location to jump to for soft reset 113 */ 114 .align 5 115ENTRY(cpu_arm925_reset) 116 /* Send software reset to MPU and DSP */ 117 mov ip, #0xff000000 118 orr ip, ip, #0x00fe0000 119 orr ip, ip, #0x0000ce00 120 mov r4, #1 121 strh r4, [ip, #0x10] 122 123 mov ip, #0 124 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 125 mcr p15, 0, ip, c7, c10, 4 @ drain WB 126#ifdef CONFIG_MMU 127 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 128#endif 129 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 130 bic ip, ip, #0x000f @ ............wcam 131 bic ip, ip, #0x1100 @ ...i...s........ 132 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 133 mov pc, r0 134 135/* 136 * cpu_arm925_do_idle() 137 * 138 * Called with IRQs disabled 139 */ 140 .align 10 141ENTRY(cpu_arm925_do_idle) 142 mov r0, #0 143 mrc p15, 0, r1, c1, c0, 0 @ Read control register 144 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 145 bic r2, r1, #1 << 12 146 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache 147 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 148 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable 149 mov pc, lr 150 151/* 152 * flush_user_cache_all() 153 * 154 * Clean and invalidate all cache entries in a particular 155 * address space. 156 */ 157ENTRY(arm925_flush_user_cache_all) 158 /* FALLTHROUGH */ 159 160/* 161 * flush_kern_cache_all() 162 * 163 * Clean and invalidate the entire cache. 164 */ 165ENTRY(arm925_flush_kern_cache_all) 166 mov r2, #VM_EXEC 167 mov ip, #0 168__flush_whole_cache: 169#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 170 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 171#else 172 /* Flush entries in both segments at once, see NOTE1 above */ 173 mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment 1742: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 175 subs r3, r3, #1 << 4 176 bcs 2b @ entries 255 to 0 177#endif 178 tst r2, #VM_EXEC 179 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 180 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 181 mov pc, lr 182 183/* 184 * flush_user_cache_range(start, end, flags) 185 * 186 * Clean and invalidate a range of cache entries in the 187 * specified address range. 188 * 189 * - start - start address (inclusive) 190 * - end - end address (exclusive) 191 * - flags - vm_flags describing address space 192 */ 193ENTRY(arm925_flush_user_cache_range) 194 mov ip, #0 195 sub r3, r1, r0 @ calculate total size 196 cmp r3, #CACHE_DLIMIT 197 bgt __flush_whole_cache 1981: tst r2, #VM_EXEC 199#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 200 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 201 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 202 add r0, r0, #CACHE_DLINESIZE 203 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 204 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 205 add r0, r0, #CACHE_DLINESIZE 206#else 207 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 208 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 209 add r0, r0, #CACHE_DLINESIZE 210 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 211 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 212 add r0, r0, #CACHE_DLINESIZE 213#endif 214 cmp r0, r1 215 blo 1b 216 tst r2, #VM_EXEC 217 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 218 mov pc, lr 219 220/* 221 * coherent_kern_range(start, end) 222 * 223 * Ensure coherency between the Icache and the Dcache in the 224 * region described by start, end. If you have non-snooping 225 * Harvard caches, you need to implement this function. 226 * 227 * - start - virtual start address 228 * - end - virtual end address 229 */ 230ENTRY(arm925_coherent_kern_range) 231 /* FALLTHROUGH */ 232 233/* 234 * coherent_user_range(start, end) 235 * 236 * Ensure coherency between the Icache and the Dcache in the 237 * region described by start, end. If you have non-snooping 238 * Harvard caches, you need to implement this function. 239 * 240 * - start - virtual start address 241 * - end - virtual end address 242 */ 243ENTRY(arm925_coherent_user_range) 244 bic r0, r0, #CACHE_DLINESIZE - 1 2451: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 246 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 247 add r0, r0, #CACHE_DLINESIZE 248 cmp r0, r1 249 blo 1b 250 mcr p15, 0, r0, c7, c10, 4 @ drain WB 251 mov pc, lr 252 253/* 254 * flush_kern_dcache_area(void *addr, size_t size) 255 * 256 * Ensure no D cache aliasing occurs, either with itself or 257 * the I cache 258 * 259 * - addr - kernel address 260 * - size - region size 261 */ 262ENTRY(arm925_flush_kern_dcache_area) 263 add r1, r0, r1 2641: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 265 add r0, r0, #CACHE_DLINESIZE 266 cmp r0, r1 267 blo 1b 268 mov r0, #0 269 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 270 mcr p15, 0, r0, c7, c10, 4 @ drain WB 271 mov pc, lr 272 273/* 274 * dma_inv_range(start, end) 275 * 276 * Invalidate (discard) the specified virtual address range. 277 * May not write back any entries. If 'start' or 'end' 278 * are not cache line aligned, those lines must be written 279 * back. 280 * 281 * - start - virtual start address 282 * - end - virtual end address 283 * 284 * (same as v4wb) 285 */ 286ENTRY(arm925_dma_inv_range) 287#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 288 tst r0, #CACHE_DLINESIZE - 1 289 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 290 tst r1, #CACHE_DLINESIZE - 1 291 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 292#endif 293 bic r0, r0, #CACHE_DLINESIZE - 1 2941: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 295 add r0, r0, #CACHE_DLINESIZE 296 cmp r0, r1 297 blo 1b 298 mcr p15, 0, r0, c7, c10, 4 @ drain WB 299 mov pc, lr 300 301/* 302 * dma_clean_range(start, end) 303 * 304 * Clean the specified virtual address range. 305 * 306 * - start - virtual start address 307 * - end - virtual end address 308 * 309 * (same as v4wb) 310 */ 311ENTRY(arm925_dma_clean_range) 312#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 313 bic r0, r0, #CACHE_DLINESIZE - 1 3141: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 315 add r0, r0, #CACHE_DLINESIZE 316 cmp r0, r1 317 blo 1b 318#endif 319 mcr p15, 0, r0, c7, c10, 4 @ drain WB 320 mov pc, lr 321 322/* 323 * dma_flush_range(start, end) 324 * 325 * Clean and invalidate the specified virtual address range. 326 * 327 * - start - virtual start address 328 * - end - virtual end address 329 */ 330ENTRY(arm925_dma_flush_range) 331 bic r0, r0, #CACHE_DLINESIZE - 1 3321: 333#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 334 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 335#else 336 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 337#endif 338 add r0, r0, #CACHE_DLINESIZE 339 cmp r0, r1 340 blo 1b 341 mcr p15, 0, r0, c7, c10, 4 @ drain WB 342 mov pc, lr 343 344ENTRY(arm925_cache_fns) 345 .long arm925_flush_kern_cache_all 346 .long arm925_flush_user_cache_all 347 .long arm925_flush_user_cache_range 348 .long arm925_coherent_kern_range 349 .long arm925_coherent_user_range 350 .long arm925_flush_kern_dcache_area 351 .long arm925_dma_inv_range 352 .long arm925_dma_clean_range 353 .long arm925_dma_flush_range 354 355ENTRY(cpu_arm925_dcache_clean_area) 356#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 3571: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 358 add r0, r0, #CACHE_DLINESIZE 359 subs r1, r1, #CACHE_DLINESIZE 360 bhi 1b 361#endif 362 mcr p15, 0, r0, c7, c10, 4 @ drain WB 363 mov pc, lr 364 365/* =============================== PageTable ============================== */ 366 367/* 368 * cpu_arm925_switch_mm(pgd) 369 * 370 * Set the translation base pointer to be as described by pgd. 371 * 372 * pgd: new page tables 373 */ 374 .align 5 375ENTRY(cpu_arm925_switch_mm) 376#ifdef CONFIG_MMU 377 mov ip, #0 378#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 379 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 380#else 381 /* Flush entries in bothe segments at once, see NOTE1 above */ 382 mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment 3832: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index 384 subs r3, r3, #1 << 4 385 bcs 2b @ entries 255 to 0 386#endif 387 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 388 mcr p15, 0, ip, c7, c10, 4 @ drain WB 389 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 390 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 391#endif 392 mov pc, lr 393 394/* 395 * cpu_arm925_set_pte_ext(ptep, pte, ext) 396 * 397 * Set a PTE and flush it out 398 */ 399 .align 5 400ENTRY(cpu_arm925_set_pte_ext) 401#ifdef CONFIG_MMU 402 armv3_set_pte_ext 403 mov r0, r0 404#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 405 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 406#endif 407 mcr p15, 0, r0, c7, c10, 4 @ drain WB 408#endif /* CONFIG_MMU */ 409 mov pc, lr 410 411 __INIT 412 413 .type __arm925_setup, #function 414__arm925_setup: 415 mov r0, #0 416#if defined(CONFIG_CPU_ICACHE_STREAMING_DISABLE) 417 orr r0,r0,#1 << 7 418#endif 419 420 /* Transparent on, D-cache clean & flush mode. See NOTE2 above */ 421 orr r0,r0,#1 << 1 @ transparent mode on 422 mcr p15, 0, r0, c15, c1, 0 @ write TI config register 423 424 mov r0, #0 425 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 426 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 427#ifdef CONFIG_MMU 428 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 429#endif 430 431#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 432 mov r0, #4 @ disable write-back on caches explicitly 433 mcr p15, 7, r0, c15, c0, 0 434#endif 435 436 adr r5, arm925_crval 437 ldmia r5, {r5, r6} 438 mrc p15, 0, r0, c1, c0 @ get control register v4 439 bic r0, r0, r5 440 orr r0, r0, r6 441#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 442 orr r0, r0, #0x4000 @ .1.. .... .... .... 443#endif 444 mov pc, lr 445 .size __arm925_setup, . - __arm925_setup 446 447 /* 448 * R 449 * .RVI ZFRS BLDP WCAM 450 * .011 0001 ..11 1101 451 * 452 */ 453 .type arm925_crval, #object 454arm925_crval: 455 crval clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130 456 457 __INITDATA 458 459/* 460 * Purpose : Function pointers used to access above functions - all calls 461 * come through these 462 */ 463 .type arm925_processor_functions, #object 464arm925_processor_functions: 465 .word v4t_early_abort 466 .word legacy_pabort 467 .word cpu_arm925_proc_init 468 .word cpu_arm925_proc_fin 469 .word cpu_arm925_reset 470 .word cpu_arm925_do_idle 471 .word cpu_arm925_dcache_clean_area 472 .word cpu_arm925_switch_mm 473 .word cpu_arm925_set_pte_ext 474 .size arm925_processor_functions, . - arm925_processor_functions 475 476 .section ".rodata" 477 478 .type cpu_arch_name, #object 479cpu_arch_name: 480 .asciz "armv4t" 481 .size cpu_arch_name, . - cpu_arch_name 482 483 .type cpu_elf_name, #object 484cpu_elf_name: 485 .asciz "v4" 486 .size cpu_elf_name, . - cpu_elf_name 487 488 .type cpu_arm925_name, #object 489cpu_arm925_name: 490 .asciz "ARM925T" 491 .size cpu_arm925_name, . - cpu_arm925_name 492 493 .align 494 495 .section ".proc.info.init", #alloc, #execinstr 496 497 .type __arm925_proc_info,#object 498__arm925_proc_info: 499 .long 0x54029250 500 .long 0xfffffff0 501 .long PMD_TYPE_SECT | \ 502 PMD_BIT4 | \ 503 PMD_SECT_AP_WRITE | \ 504 PMD_SECT_AP_READ 505 .long PMD_TYPE_SECT | \ 506 PMD_BIT4 | \ 507 PMD_SECT_AP_WRITE | \ 508 PMD_SECT_AP_READ 509 b __arm925_setup 510 .long cpu_arch_name 511 .long cpu_elf_name 512 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB 513 .long cpu_arm925_name 514 .long arm925_processor_functions 515 .long v4wbi_tlb_fns 516 .long v4wb_user_fns 517 .long arm925_cache_fns 518 .size __arm925_proc_info, . - __arm925_proc_info 519 520 .type __arm915_proc_info,#object 521__arm915_proc_info: 522 .long 0x54029150 523 .long 0xfffffff0 524 .long PMD_TYPE_SECT | \ 525 PMD_BIT4 | \ 526 PMD_SECT_AP_WRITE | \ 527 PMD_SECT_AP_READ 528 .long PMD_TYPE_SECT | \ 529 PMD_BIT4 | \ 530 PMD_SECT_AP_WRITE | \ 531 PMD_SECT_AP_READ 532 b __arm925_setup 533 .long cpu_arch_name 534 .long cpu_elf_name 535 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB 536 .long cpu_arm925_name 537 .long arm925_processor_functions 538 .long v4wbi_tlb_fns 539 .long v4wb_user_fns 540 .long arm925_cache_fns 541 .size __arm925_proc_info, . - __arm925_proc_info 542