1/* 2 * linux/arch/arm/mm/arm925.S: MMU functions for ARM925 3 * 4 * Copyright (C) 1999,2000 ARM Limited 5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 6 * Copyright (C) 2002 RidgeRun, Inc. 7 * Copyright (C) 2002-2003 MontaVista Software, Inc. 8 * 9 * Update for Linux-2.6 and cache flush improvements 10 * Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com> 11 * 12 * hacked for non-paged-MM by Hyok S. Choi, 2004. 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 27 * 28 * 29 * These are the low level assembler for performing cache and TLB 30 * functions on the arm925. 31 * 32 * CONFIG_CPU_ARM925_CPU_IDLE -> nohlt 33 * 34 * Some additional notes based on deciphering the TI TRM on OMAP-5910: 35 * 36 * NOTE1: The TI925T Configuration Register bit "D-cache clean and flush 37 * entry mode" must be 0 to flush the entries in both segments 38 * at once. This is the default value. See TRM 2-20 and 2-24 for 39 * more information. 40 * 41 * NOTE2: Default is the "D-cache clean and flush entry mode". It looks 42 * like the "Transparent mode" must be on for partial cache flushes 43 * to work in this mode. This mode only works with 16-bit external 44 * memory. See TRM 2-24 for more information. 45 * 46 * NOTE3: Write-back cache flushing seems to be flakey with devices using 47 * direct memory access, such as USB OHCI. The workaround is to use 48 * write-through cache with CONFIG_CPU_DCACHE_WRITETHROUGH (this is 49 * the default for OMAP-1510). 50 */ 51 52#include <linux/linkage.h> 53#include <linux/init.h> 54#include <asm/assembler.h> 55#include <asm/hwcap.h> 56#include <asm/pgtable-hwdef.h> 57#include <asm/pgtable.h> 58#include <asm/page.h> 59#include <asm/ptrace.h> 60#include "proc-macros.S" 61 62/* 63 * The size of one data cache line. 64 */ 65#define CACHE_DLINESIZE 16 66 67/* 68 * The number of data cache segments. 69 */ 70#define CACHE_DSEGMENTS 2 71 72/* 73 * The number of lines in a cache segment. 74 */ 75#define CACHE_DENTRIES 256 76 77/* 78 * This is the size at which it becomes more efficient to 79 * clean the whole cache, rather than using the individual 80 * cache line maintainence instructions. 81 */ 82#define CACHE_DLIMIT 8192 83 84 .text 85/* 86 * cpu_arm925_proc_init() 87 */ 88ENTRY(cpu_arm925_proc_init) 89 mov pc, lr 90 91/* 92 * cpu_arm925_proc_fin() 93 */ 94ENTRY(cpu_arm925_proc_fin) 95 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 96 bic r0, r0, #0x1000 @ ...i............ 97 bic r0, r0, #0x000e @ ............wca. 98 mcr p15, 0, r0, c1, c0, 0 @ disable caches 99 mov pc, lr 100 101/* 102 * cpu_arm925_reset(loc) 103 * 104 * Perform a soft reset of the system. Put the CPU into the 105 * same state as it would be if it had been reset, and branch 106 * to what would be the reset vector. 107 * 108 * loc: location to jump to for soft reset 109 */ 110 .align 5 111ENTRY(cpu_arm925_reset) 112 /* Send software reset to MPU and DSP */ 113 mov ip, #0xff000000 114 orr ip, ip, #0x00fe0000 115 orr ip, ip, #0x0000ce00 116 mov r4, #1 117 strh r4, [ip, #0x10] 118 119 mov ip, #0 120 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 121 mcr p15, 0, ip, c7, c10, 4 @ drain WB 122#ifdef CONFIG_MMU 123 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 124#endif 125 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 126 bic ip, ip, #0x000f @ ............wcam 127 bic ip, ip, #0x1100 @ ...i...s........ 128 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 129 mov pc, r0 130 131/* 132 * cpu_arm925_do_idle() 133 * 134 * Called with IRQs disabled 135 */ 136 .align 10 137ENTRY(cpu_arm925_do_idle) 138 mov r0, #0 139 mrc p15, 0, r1, c1, c0, 0 @ Read control register 140 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 141 bic r2, r1, #1 << 12 142 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache 143 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 144 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable 145 mov pc, lr 146 147/* 148 * flush_user_cache_all() 149 * 150 * Clean and invalidate all cache entries in a particular 151 * address space. 152 */ 153ENTRY(arm925_flush_user_cache_all) 154 /* FALLTHROUGH */ 155 156/* 157 * flush_kern_cache_all() 158 * 159 * Clean and invalidate the entire cache. 160 */ 161ENTRY(arm925_flush_kern_cache_all) 162 mov r2, #VM_EXEC 163 mov ip, #0 164__flush_whole_cache: 165#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 166 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 167#else 168 /* Flush entries in both segments at once, see NOTE1 above */ 169 mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment 1702: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 171 subs r3, r3, #1 << 4 172 bcs 2b @ entries 255 to 0 173#endif 174 tst r2, #VM_EXEC 175 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 176 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 177 mov pc, lr 178 179/* 180 * flush_user_cache_range(start, end, flags) 181 * 182 * Clean and invalidate a range of cache entries in the 183 * specified address range. 184 * 185 * - start - start address (inclusive) 186 * - end - end address (exclusive) 187 * - flags - vm_flags describing address space 188 */ 189ENTRY(arm925_flush_user_cache_range) 190 mov ip, #0 191 sub r3, r1, r0 @ calculate total size 192 cmp r3, #CACHE_DLIMIT 193 bgt __flush_whole_cache 1941: tst r2, #VM_EXEC 195#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 196 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 197 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 198 add r0, r0, #CACHE_DLINESIZE 199 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 200 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 201 add r0, r0, #CACHE_DLINESIZE 202#else 203 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 204 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 205 add r0, r0, #CACHE_DLINESIZE 206 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 207 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 208 add r0, r0, #CACHE_DLINESIZE 209#endif 210 cmp r0, r1 211 blo 1b 212 tst r2, #VM_EXEC 213 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 214 mov pc, lr 215 216/* 217 * coherent_kern_range(start, end) 218 * 219 * Ensure coherency between the Icache and the Dcache in the 220 * region described by start, end. If you have non-snooping 221 * Harvard caches, you need to implement this function. 222 * 223 * - start - virtual start address 224 * - end - virtual end address 225 */ 226ENTRY(arm925_coherent_kern_range) 227 /* FALLTHROUGH */ 228 229/* 230 * coherent_user_range(start, end) 231 * 232 * Ensure coherency between the Icache and the Dcache in the 233 * region described by start, end. If you have non-snooping 234 * Harvard caches, you need to implement this function. 235 * 236 * - start - virtual start address 237 * - end - virtual end address 238 */ 239ENTRY(arm925_coherent_user_range) 240 bic r0, r0, #CACHE_DLINESIZE - 1 2411: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 242 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 243 add r0, r0, #CACHE_DLINESIZE 244 cmp r0, r1 245 blo 1b 246 mcr p15, 0, r0, c7, c10, 4 @ drain WB 247 mov pc, lr 248 249/* 250 * flush_kern_dcache_area(void *addr, size_t size) 251 * 252 * Ensure no D cache aliasing occurs, either with itself or 253 * the I cache 254 * 255 * - addr - kernel address 256 * - size - region size 257 */ 258ENTRY(arm925_flush_kern_dcache_area) 259 add r1, r0, r1 2601: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 261 add r0, r0, #CACHE_DLINESIZE 262 cmp r0, r1 263 blo 1b 264 mov r0, #0 265 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 266 mcr p15, 0, r0, c7, c10, 4 @ drain WB 267 mov pc, lr 268 269/* 270 * dma_inv_range(start, end) 271 * 272 * Invalidate (discard) the specified virtual address range. 273 * May not write back any entries. If 'start' or 'end' 274 * are not cache line aligned, those lines must be written 275 * back. 276 * 277 * - start - virtual start address 278 * - end - virtual end address 279 * 280 * (same as v4wb) 281 */ 282arm925_dma_inv_range: 283#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 284 tst r0, #CACHE_DLINESIZE - 1 285 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 286 tst r1, #CACHE_DLINESIZE - 1 287 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 288#endif 289 bic r0, r0, #CACHE_DLINESIZE - 1 2901: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 291 add r0, r0, #CACHE_DLINESIZE 292 cmp r0, r1 293 blo 1b 294 mcr p15, 0, r0, c7, c10, 4 @ drain WB 295 mov pc, lr 296 297/* 298 * dma_clean_range(start, end) 299 * 300 * Clean the specified virtual address range. 301 * 302 * - start - virtual start address 303 * - end - virtual end address 304 * 305 * (same as v4wb) 306 */ 307arm925_dma_clean_range: 308#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 309 bic r0, r0, #CACHE_DLINESIZE - 1 3101: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 311 add r0, r0, #CACHE_DLINESIZE 312 cmp r0, r1 313 blo 1b 314#endif 315 mcr p15, 0, r0, c7, c10, 4 @ drain WB 316 mov pc, lr 317 318/* 319 * dma_flush_range(start, end) 320 * 321 * Clean and invalidate the specified virtual address range. 322 * 323 * - start - virtual start address 324 * - end - virtual end address 325 */ 326ENTRY(arm925_dma_flush_range) 327 bic r0, r0, #CACHE_DLINESIZE - 1 3281: 329#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 330 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 331#else 332 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 333#endif 334 add r0, r0, #CACHE_DLINESIZE 335 cmp r0, r1 336 blo 1b 337 mcr p15, 0, r0, c7, c10, 4 @ drain WB 338 mov pc, lr 339 340/* 341 * dma_map_area(start, size, dir) 342 * - start - kernel virtual start address 343 * - size - size of region 344 * - dir - DMA direction 345 */ 346ENTRY(arm925_dma_map_area) 347 add r1, r1, r0 348 cmp r2, #DMA_TO_DEVICE 349 beq arm925_dma_clean_range 350 bcs arm925_dma_inv_range 351 b arm925_dma_flush_range 352ENDPROC(arm925_dma_map_area) 353 354/* 355 * dma_unmap_area(start, size, dir) 356 * - start - kernel virtual start address 357 * - size - size of region 358 * - dir - DMA direction 359 */ 360ENTRY(arm925_dma_unmap_area) 361 mov pc, lr 362ENDPROC(arm925_dma_unmap_area) 363 364ENTRY(arm925_cache_fns) 365 .long arm925_flush_kern_cache_all 366 .long arm925_flush_user_cache_all 367 .long arm925_flush_user_cache_range 368 .long arm925_coherent_kern_range 369 .long arm925_coherent_user_range 370 .long arm925_flush_kern_dcache_area 371 .long arm925_dma_map_area 372 .long arm925_dma_unmap_area 373 .long arm925_dma_flush_range 374 375ENTRY(cpu_arm925_dcache_clean_area) 376#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 3771: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 378 add r0, r0, #CACHE_DLINESIZE 379 subs r1, r1, #CACHE_DLINESIZE 380 bhi 1b 381#endif 382 mcr p15, 0, r0, c7, c10, 4 @ drain WB 383 mov pc, lr 384 385/* =============================== PageTable ============================== */ 386 387/* 388 * cpu_arm925_switch_mm(pgd) 389 * 390 * Set the translation base pointer to be as described by pgd. 391 * 392 * pgd: new page tables 393 */ 394 .align 5 395ENTRY(cpu_arm925_switch_mm) 396#ifdef CONFIG_MMU 397 mov ip, #0 398#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 399 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 400#else 401 /* Flush entries in bothe segments at once, see NOTE1 above */ 402 mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment 4032: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index 404 subs r3, r3, #1 << 4 405 bcs 2b @ entries 255 to 0 406#endif 407 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 408 mcr p15, 0, ip, c7, c10, 4 @ drain WB 409 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 410 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 411#endif 412 mov pc, lr 413 414/* 415 * cpu_arm925_set_pte_ext(ptep, pte, ext) 416 * 417 * Set a PTE and flush it out 418 */ 419 .align 5 420ENTRY(cpu_arm925_set_pte_ext) 421#ifdef CONFIG_MMU 422 armv3_set_pte_ext 423 mov r0, r0 424#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 425 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 426#endif 427 mcr p15, 0, r0, c7, c10, 4 @ drain WB 428#endif /* CONFIG_MMU */ 429 mov pc, lr 430 431 __CPUINIT 432 433 .type __arm925_setup, #function 434__arm925_setup: 435 mov r0, #0 436#if defined(CONFIG_CPU_ICACHE_STREAMING_DISABLE) 437 orr r0,r0,#1 << 7 438#endif 439 440 /* Transparent on, D-cache clean & flush mode. See NOTE2 above */ 441 orr r0,r0,#1 << 1 @ transparent mode on 442 mcr p15, 0, r0, c15, c1, 0 @ write TI config register 443 444 mov r0, #0 445 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 446 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 447#ifdef CONFIG_MMU 448 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 449#endif 450 451#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 452 mov r0, #4 @ disable write-back on caches explicitly 453 mcr p15, 7, r0, c15, c0, 0 454#endif 455 456 adr r5, arm925_crval 457 ldmia r5, {r5, r6} 458 mrc p15, 0, r0, c1, c0 @ get control register v4 459 bic r0, r0, r5 460 orr r0, r0, r6 461#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 462 orr r0, r0, #0x4000 @ .1.. .... .... .... 463#endif 464 mov pc, lr 465 .size __arm925_setup, . - __arm925_setup 466 467 /* 468 * R 469 * .RVI ZFRS BLDP WCAM 470 * .011 0001 ..11 1101 471 * 472 */ 473 .type arm925_crval, #object 474arm925_crval: 475 crval clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130 476 477 __INITDATA 478 479/* 480 * Purpose : Function pointers used to access above functions - all calls 481 * come through these 482 */ 483 .type arm925_processor_functions, #object 484arm925_processor_functions: 485 .word v4t_early_abort 486 .word legacy_pabort 487 .word cpu_arm925_proc_init 488 .word cpu_arm925_proc_fin 489 .word cpu_arm925_reset 490 .word cpu_arm925_do_idle 491 .word cpu_arm925_dcache_clean_area 492 .word cpu_arm925_switch_mm 493 .word cpu_arm925_set_pte_ext 494 .size arm925_processor_functions, . - arm925_processor_functions 495 496 .section ".rodata" 497 498 .type cpu_arch_name, #object 499cpu_arch_name: 500 .asciz "armv4t" 501 .size cpu_arch_name, . - cpu_arch_name 502 503 .type cpu_elf_name, #object 504cpu_elf_name: 505 .asciz "v4" 506 .size cpu_elf_name, . - cpu_elf_name 507 508 .type cpu_arm925_name, #object 509cpu_arm925_name: 510 .asciz "ARM925T" 511 .size cpu_arm925_name, . - cpu_arm925_name 512 513 .align 514 515 .section ".proc.info.init", #alloc, #execinstr 516 517 .type __arm925_proc_info,#object 518__arm925_proc_info: 519 .long 0x54029250 520 .long 0xfffffff0 521 .long PMD_TYPE_SECT | \ 522 PMD_BIT4 | \ 523 PMD_SECT_AP_WRITE | \ 524 PMD_SECT_AP_READ 525 .long PMD_TYPE_SECT | \ 526 PMD_BIT4 | \ 527 PMD_SECT_AP_WRITE | \ 528 PMD_SECT_AP_READ 529 b __arm925_setup 530 .long cpu_arch_name 531 .long cpu_elf_name 532 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB 533 .long cpu_arm925_name 534 .long arm925_processor_functions 535 .long v4wbi_tlb_fns 536 .long v4wb_user_fns 537 .long arm925_cache_fns 538 .size __arm925_proc_info, . - __arm925_proc_info 539 540 .type __arm915_proc_info,#object 541__arm915_proc_info: 542 .long 0x54029150 543 .long 0xfffffff0 544 .long PMD_TYPE_SECT | \ 545 PMD_BIT4 | \ 546 PMD_SECT_AP_WRITE | \ 547 PMD_SECT_AP_READ 548 .long PMD_TYPE_SECT | \ 549 PMD_BIT4 | \ 550 PMD_SECT_AP_WRITE | \ 551 PMD_SECT_AP_READ 552 b __arm925_setup 553 .long cpu_arch_name 554 .long cpu_elf_name 555 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB 556 .long cpu_arm925_name 557 .long arm925_processor_functions 558 .long v4wbi_tlb_fns 559 .long v4wb_user_fns 560 .long arm925_cache_fns 561 .size __arm925_proc_info, . - __arm925_proc_info 562