1/* 2 * linux/arch/arm/mm/proc-arm922.S: MMU functions for ARM922 3 * 4 * Copyright (C) 1999,2000 ARM Limited 5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 6 * Copyright (C) 2001 Altera Corporation 7 * hacked for non-paged-MM by Hyok S. Choi, 2003. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 * 23 * 24 * These are the low level assembler for performing cache and TLB 25 * functions on the arm922. 26 * 27 * CONFIG_CPU_ARM922_CPU_IDLE -> nohlt 28 */ 29#include <linux/linkage.h> 30#include <linux/init.h> 31#include <asm/assembler.h> 32#include <asm/hwcap.h> 33#include <asm/pgtable-hwdef.h> 34#include <asm/pgtable.h> 35#include <asm/page.h> 36#include <asm/ptrace.h> 37#include "proc-macros.S" 38 39/* 40 * The size of one data cache line. 41 */ 42#define CACHE_DLINESIZE 32 43 44/* 45 * The number of data cache segments. 46 */ 47#define CACHE_DSEGMENTS 4 48 49/* 50 * The number of lines in a cache segment. 51 */ 52#define CACHE_DENTRIES 64 53 54/* 55 * This is the size at which it becomes more efficient to 56 * clean the whole cache, rather than using the individual 57 * cache line maintenance instructions. (I think this should 58 * be 32768). 59 */ 60#define CACHE_DLIMIT 8192 61 62 63 .text 64/* 65 * cpu_arm922_proc_init() 66 */ 67ENTRY(cpu_arm922_proc_init) 68 mov pc, lr 69 70/* 71 * cpu_arm922_proc_fin() 72 */ 73ENTRY(cpu_arm922_proc_fin) 74 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 75 bic r0, r0, #0x1000 @ ...i............ 76 bic r0, r0, #0x000e @ ............wca. 77 mcr p15, 0, r0, c1, c0, 0 @ disable caches 78 mov pc, lr 79 80/* 81 * cpu_arm922_reset(loc) 82 * 83 * Perform a soft reset of the system. Put the CPU into the 84 * same state as it would be if it had been reset, and branch 85 * to what would be the reset vector. 86 * 87 * loc: location to jump to for soft reset 88 */ 89 .align 5 90 .pushsection .idmap.text, "ax" 91ENTRY(cpu_arm922_reset) 92 mov ip, #0 93 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 94 mcr p15, 0, ip, c7, c10, 4 @ drain WB 95#ifdef CONFIG_MMU 96 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 97#endif 98 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 99 bic ip, ip, #0x000f @ ............wcam 100 bic ip, ip, #0x1100 @ ...i...s........ 101 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 102 mov pc, r0 103ENDPROC(cpu_arm922_reset) 104 .popsection 105 106/* 107 * cpu_arm922_do_idle() 108 */ 109 .align 5 110ENTRY(cpu_arm922_do_idle) 111 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 112 mov pc, lr 113 114 115#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 116 117/* 118 * flush_icache_all() 119 * 120 * Unconditionally clean and invalidate the entire icache. 121 */ 122ENTRY(arm922_flush_icache_all) 123 mov r0, #0 124 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 125 mov pc, lr 126ENDPROC(arm922_flush_icache_all) 127 128/* 129 * flush_user_cache_all() 130 * 131 * Clean and invalidate all cache entries in a particular 132 * address space. 133 */ 134ENTRY(arm922_flush_user_cache_all) 135 /* FALLTHROUGH */ 136 137/* 138 * flush_kern_cache_all() 139 * 140 * Clean and invalidate the entire cache. 141 */ 142ENTRY(arm922_flush_kern_cache_all) 143 mov r2, #VM_EXEC 144 mov ip, #0 145__flush_whole_cache: 146 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments 1471: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 1482: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 149 subs r3, r3, #1 << 26 150 bcs 2b @ entries 63 to 0 151 subs r1, r1, #1 << 5 152 bcs 1b @ segments 7 to 0 153 tst r2, #VM_EXEC 154 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 155 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 156 mov pc, lr 157 158/* 159 * flush_user_cache_range(start, end, flags) 160 * 161 * Clean and invalidate a range of cache entries in the 162 * specified address range. 163 * 164 * - start - start address (inclusive) 165 * - end - end address (exclusive) 166 * - flags - vm_flags describing address space 167 */ 168ENTRY(arm922_flush_user_cache_range) 169 mov ip, #0 170 sub r3, r1, r0 @ calculate total size 171 cmp r3, #CACHE_DLIMIT 172 bhs __flush_whole_cache 173 1741: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 175 tst r2, #VM_EXEC 176 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 177 add r0, r0, #CACHE_DLINESIZE 178 cmp r0, r1 179 blo 1b 180 tst r2, #VM_EXEC 181 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 182 mov pc, lr 183 184/* 185 * coherent_kern_range(start, end) 186 * 187 * Ensure coherency between the Icache and the Dcache in the 188 * region described by start, end. If you have non-snooping 189 * Harvard caches, you need to implement this function. 190 * 191 * - start - virtual start address 192 * - end - virtual end address 193 */ 194ENTRY(arm922_coherent_kern_range) 195 /* FALLTHROUGH */ 196 197/* 198 * coherent_user_range(start, end) 199 * 200 * Ensure coherency between the Icache and the Dcache in the 201 * region described by start, end. If you have non-snooping 202 * Harvard caches, you need to implement this function. 203 * 204 * - start - virtual start address 205 * - end - virtual end address 206 */ 207ENTRY(arm922_coherent_user_range) 208 bic r0, r0, #CACHE_DLINESIZE - 1 2091: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 210 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 211 add r0, r0, #CACHE_DLINESIZE 212 cmp r0, r1 213 blo 1b 214 mcr p15, 0, r0, c7, c10, 4 @ drain WB 215 mov pc, lr 216 217/* 218 * flush_kern_dcache_area(void *addr, size_t size) 219 * 220 * Ensure no D cache aliasing occurs, either with itself or 221 * the I cache 222 * 223 * - addr - kernel address 224 * - size - region size 225 */ 226ENTRY(arm922_flush_kern_dcache_area) 227 add r1, r0, r1 2281: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 229 add r0, r0, #CACHE_DLINESIZE 230 cmp r0, r1 231 blo 1b 232 mov r0, #0 233 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 234 mcr p15, 0, r0, c7, c10, 4 @ drain WB 235 mov pc, lr 236 237/* 238 * dma_inv_range(start, end) 239 * 240 * Invalidate (discard) the specified virtual address range. 241 * May not write back any entries. If 'start' or 'end' 242 * are not cache line aligned, those lines must be written 243 * back. 244 * 245 * - start - virtual start address 246 * - end - virtual end address 247 * 248 * (same as v4wb) 249 */ 250arm922_dma_inv_range: 251 tst r0, #CACHE_DLINESIZE - 1 252 bic r0, r0, #CACHE_DLINESIZE - 1 253 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 254 tst r1, #CACHE_DLINESIZE - 1 255 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 2561: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 257 add r0, r0, #CACHE_DLINESIZE 258 cmp r0, r1 259 blo 1b 260 mcr p15, 0, r0, c7, c10, 4 @ drain WB 261 mov pc, lr 262 263/* 264 * dma_clean_range(start, end) 265 * 266 * Clean the specified virtual address range. 267 * 268 * - start - virtual start address 269 * - end - virtual end address 270 * 271 * (same as v4wb) 272 */ 273arm922_dma_clean_range: 274 bic r0, r0, #CACHE_DLINESIZE - 1 2751: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 276 add r0, r0, #CACHE_DLINESIZE 277 cmp r0, r1 278 blo 1b 279 mcr p15, 0, r0, c7, c10, 4 @ drain WB 280 mov pc, lr 281 282/* 283 * dma_flush_range(start, end) 284 * 285 * Clean and invalidate the specified virtual address range. 286 * 287 * - start - virtual start address 288 * - end - virtual end address 289 */ 290ENTRY(arm922_dma_flush_range) 291 bic r0, r0, #CACHE_DLINESIZE - 1 2921: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 293 add r0, r0, #CACHE_DLINESIZE 294 cmp r0, r1 295 blo 1b 296 mcr p15, 0, r0, c7, c10, 4 @ drain WB 297 mov pc, lr 298 299/* 300 * dma_map_area(start, size, dir) 301 * - start - kernel virtual start address 302 * - size - size of region 303 * - dir - DMA direction 304 */ 305ENTRY(arm922_dma_map_area) 306 add r1, r1, r0 307 cmp r2, #DMA_TO_DEVICE 308 beq arm922_dma_clean_range 309 bcs arm922_dma_inv_range 310 b arm922_dma_flush_range 311ENDPROC(arm922_dma_map_area) 312 313/* 314 * dma_unmap_area(start, size, dir) 315 * - start - kernel virtual start address 316 * - size - size of region 317 * - dir - DMA direction 318 */ 319ENTRY(arm922_dma_unmap_area) 320 mov pc, lr 321ENDPROC(arm922_dma_unmap_area) 322 323 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) 324 define_cache_functions arm922 325#endif 326 327 328ENTRY(cpu_arm922_dcache_clean_area) 329#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 3301: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 331 add r0, r0, #CACHE_DLINESIZE 332 subs r1, r1, #CACHE_DLINESIZE 333 bhi 1b 334#endif 335 mov pc, lr 336 337/* =============================== PageTable ============================== */ 338 339/* 340 * cpu_arm922_switch_mm(pgd) 341 * 342 * Set the translation base pointer to be as described by pgd. 343 * 344 * pgd: new page tables 345 */ 346 .align 5 347ENTRY(cpu_arm922_switch_mm) 348#ifdef CONFIG_MMU 349 mov ip, #0 350#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 351 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 352#else 353@ && 'Clean & Invalidate whole DCache' 354@ && Re-written to use Index Ops. 355@ && Uses registers r1, r3 and ip 356 357 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 4 segments 3581: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 3592: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index 360 subs r3, r3, #1 << 26 361 bcs 2b @ entries 63 to 0 362 subs r1, r1, #1 << 5 363 bcs 1b @ segments 7 to 0 364#endif 365 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 366 mcr p15, 0, ip, c7, c10, 4 @ drain WB 367 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 368 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 369#endif 370 mov pc, lr 371 372/* 373 * cpu_arm922_set_pte_ext(ptep, pte, ext) 374 * 375 * Set a PTE and flush it out 376 */ 377 .align 5 378ENTRY(cpu_arm922_set_pte_ext) 379#ifdef CONFIG_MMU 380 armv3_set_pte_ext 381 mov r0, r0 382 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 383 mcr p15, 0, r0, c7, c10, 4 @ drain WB 384#endif /* CONFIG_MMU */ 385 mov pc, lr 386 387 __CPUINIT 388 389 .type __arm922_setup, #function 390__arm922_setup: 391 mov r0, #0 392 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 393 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 394#ifdef CONFIG_MMU 395 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 396#endif 397 adr r5, arm922_crval 398 ldmia r5, {r5, r6} 399 mrc p15, 0, r0, c1, c0 @ get control register v4 400 bic r0, r0, r5 401 orr r0, r0, r6 402 mov pc, lr 403 .size __arm922_setup, . - __arm922_setup 404 405 /* 406 * R 407 * .RVI ZFRS BLDP WCAM 408 * ..11 0001 ..11 0101 409 * 410 */ 411 .type arm922_crval, #object 412arm922_crval: 413 crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130 414 415 __INITDATA 416 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) 417 define_processor_functions arm922, dabort=v4t_early_abort, pabort=legacy_pabort 418 419 .section ".rodata" 420 421 string cpu_arch_name, "armv4t" 422 string cpu_elf_name, "v4" 423 string cpu_arm922_name, "ARM922T" 424 425 .align 426 427 .section ".proc.info.init", #alloc, #execinstr 428 429 .type __arm922_proc_info,#object 430__arm922_proc_info: 431 .long 0x41009220 432 .long 0xff00fff0 433 .long PMD_TYPE_SECT | \ 434 PMD_SECT_BUFFERABLE | \ 435 PMD_SECT_CACHEABLE | \ 436 PMD_BIT4 | \ 437 PMD_SECT_AP_WRITE | \ 438 PMD_SECT_AP_READ 439 .long PMD_TYPE_SECT | \ 440 PMD_BIT4 | \ 441 PMD_SECT_AP_WRITE | \ 442 PMD_SECT_AP_READ 443 b __arm922_setup 444 .long cpu_arch_name 445 .long cpu_elf_name 446 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB 447 .long cpu_arm922_name 448 .long arm922_processor_functions 449 .long v4wbi_tlb_fns 450 .long v4wb_user_fns 451#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 452 .long arm922_cache_fns 453#else 454 .long v4wt_cache_fns 455#endif 456 .size __arm922_proc_info, . - __arm922_proc_info 457