1/* 2 * linux/arch/arm/mm/proc-arm920.S: MMU functions for ARM920 3 * 4 * Copyright (C) 1999,2000 ARM Limited 5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 6 * hacked for non-paged-MM by Hyok S. Choi, 2003. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * 22 * 23 * These are the low level assembler for performing cache and TLB 24 * functions on the arm920. 25 * 26 * CONFIG_CPU_ARM920_CPU_IDLE -> nohlt 27 */ 28#include <linux/linkage.h> 29#include <linux/init.h> 30#include <asm/assembler.h> 31#include <asm/hwcap.h> 32#include <asm/pgtable-hwdef.h> 33#include <asm/pgtable.h> 34#include <asm/page.h> 35#include <asm/ptrace.h> 36#include "proc-macros.S" 37 38/* 39 * The size of one data cache line. 40 */ 41#define CACHE_DLINESIZE 32 42 43/* 44 * The number of data cache segments. 45 */ 46#define CACHE_DSEGMENTS 8 47 48/* 49 * The number of lines in a cache segment. 50 */ 51#define CACHE_DENTRIES 64 52 53/* 54 * This is the size at which it becomes more efficient to 55 * clean the whole cache, rather than using the individual 56 * cache line maintenance instructions. 57 */ 58#define CACHE_DLIMIT 65536 59 60 61 .text 62/* 63 * cpu_arm920_proc_init() 64 */ 65ENTRY(cpu_arm920_proc_init) 66 mov pc, lr 67 68/* 69 * cpu_arm920_proc_fin() 70 */ 71ENTRY(cpu_arm920_proc_fin) 72 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 73 bic r0, r0, #0x1000 @ ...i............ 74 bic r0, r0, #0x000e @ ............wca. 75 mcr p15, 0, r0, c1, c0, 0 @ disable caches 76 mov pc, lr 77 78/* 79 * cpu_arm920_reset(loc) 80 * 81 * Perform a soft reset of the system. Put the CPU into the 82 * same state as it would be if it had been reset, and branch 83 * to what would be the reset vector. 84 * 85 * loc: location to jump to for soft reset 86 */ 87 .align 5 88 .pushsection .idmap.text, "ax" 89ENTRY(cpu_arm920_reset) 90 mov ip, #0 91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 92 mcr p15, 0, ip, c7, c10, 4 @ drain WB 93#ifdef CONFIG_MMU 94 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 95#endif 96 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 97 bic ip, ip, #0x000f @ ............wcam 98 bic ip, ip, #0x1100 @ ...i...s........ 99 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 100 mov pc, r0 101ENDPROC(cpu_arm920_reset) 102 .popsection 103 104/* 105 * cpu_arm920_do_idle() 106 */ 107 .align 5 108ENTRY(cpu_arm920_do_idle) 109 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 110 mov pc, lr 111 112 113#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 114 115/* 116 * flush_icache_all() 117 * 118 * Unconditionally clean and invalidate the entire icache. 119 */ 120ENTRY(arm920_flush_icache_all) 121 mov r0, #0 122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 123 mov pc, lr 124ENDPROC(arm920_flush_icache_all) 125 126/* 127 * flush_user_cache_all() 128 * 129 * Invalidate all cache entries in a particular address 130 * space. 131 */ 132ENTRY(arm920_flush_user_cache_all) 133 /* FALLTHROUGH */ 134 135/* 136 * flush_kern_cache_all() 137 * 138 * Clean and invalidate the entire cache. 139 */ 140ENTRY(arm920_flush_kern_cache_all) 141 mov r2, #VM_EXEC 142 mov ip, #0 143__flush_whole_cache: 144 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments 1451: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 1462: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 147 subs r3, r3, #1 << 26 148 bcs 2b @ entries 63 to 0 149 subs r1, r1, #1 << 5 150 bcs 1b @ segments 7 to 0 151 tst r2, #VM_EXEC 152 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 153 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 154 mov pc, lr 155 156/* 157 * flush_user_cache_range(start, end, flags) 158 * 159 * Invalidate a range of cache entries in the specified 160 * address space. 161 * 162 * - start - start address (inclusive) 163 * - end - end address (exclusive) 164 * - flags - vm_flags for address space 165 */ 166ENTRY(arm920_flush_user_cache_range) 167 mov ip, #0 168 sub r3, r1, r0 @ calculate total size 169 cmp r3, #CACHE_DLIMIT 170 bhs __flush_whole_cache 171 1721: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 173 tst r2, #VM_EXEC 174 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 175 add r0, r0, #CACHE_DLINESIZE 176 cmp r0, r1 177 blo 1b 178 tst r2, #VM_EXEC 179 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 180 mov pc, lr 181 182/* 183 * coherent_kern_range(start, end) 184 * 185 * Ensure coherency between the Icache and the Dcache in the 186 * region described by start, end. If you have non-snooping 187 * Harvard caches, you need to implement this function. 188 * 189 * - start - virtual start address 190 * - end - virtual end address 191 */ 192ENTRY(arm920_coherent_kern_range) 193 /* FALLTHROUGH */ 194 195/* 196 * coherent_user_range(start, end) 197 * 198 * Ensure coherency between the Icache and the Dcache in the 199 * region described by start, end. If you have non-snooping 200 * Harvard caches, you need to implement this function. 201 * 202 * - start - virtual start address 203 * - end - virtual end address 204 */ 205ENTRY(arm920_coherent_user_range) 206 bic r0, r0, #CACHE_DLINESIZE - 1 2071: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 208 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 209 add r0, r0, #CACHE_DLINESIZE 210 cmp r0, r1 211 blo 1b 212 mcr p15, 0, r0, c7, c10, 4 @ drain WB 213 mov pc, lr 214 215/* 216 * flush_kern_dcache_area(void *addr, size_t size) 217 * 218 * Ensure no D cache aliasing occurs, either with itself or 219 * the I cache 220 * 221 * - addr - kernel address 222 * - size - region size 223 */ 224ENTRY(arm920_flush_kern_dcache_area) 225 add r1, r0, r1 2261: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 227 add r0, r0, #CACHE_DLINESIZE 228 cmp r0, r1 229 blo 1b 230 mov r0, #0 231 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 232 mcr p15, 0, r0, c7, c10, 4 @ drain WB 233 mov pc, lr 234 235/* 236 * dma_inv_range(start, end) 237 * 238 * Invalidate (discard) the specified virtual address range. 239 * May not write back any entries. If 'start' or 'end' 240 * are not cache line aligned, those lines must be written 241 * back. 242 * 243 * - start - virtual start address 244 * - end - virtual end address 245 * 246 * (same as v4wb) 247 */ 248arm920_dma_inv_range: 249 tst r0, #CACHE_DLINESIZE - 1 250 bic r0, r0, #CACHE_DLINESIZE - 1 251 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 252 tst r1, #CACHE_DLINESIZE - 1 253 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 2541: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 255 add r0, r0, #CACHE_DLINESIZE 256 cmp r0, r1 257 blo 1b 258 mcr p15, 0, r0, c7, c10, 4 @ drain WB 259 mov pc, lr 260 261/* 262 * dma_clean_range(start, end) 263 * 264 * Clean the specified virtual address range. 265 * 266 * - start - virtual start address 267 * - end - virtual end address 268 * 269 * (same as v4wb) 270 */ 271arm920_dma_clean_range: 272 bic r0, r0, #CACHE_DLINESIZE - 1 2731: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 274 add r0, r0, #CACHE_DLINESIZE 275 cmp r0, r1 276 blo 1b 277 mcr p15, 0, r0, c7, c10, 4 @ drain WB 278 mov pc, lr 279 280/* 281 * dma_flush_range(start, end) 282 * 283 * Clean and invalidate the specified virtual address range. 284 * 285 * - start - virtual start address 286 * - end - virtual end address 287 */ 288ENTRY(arm920_dma_flush_range) 289 bic r0, r0, #CACHE_DLINESIZE - 1 2901: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 291 add r0, r0, #CACHE_DLINESIZE 292 cmp r0, r1 293 blo 1b 294 mcr p15, 0, r0, c7, c10, 4 @ drain WB 295 mov pc, lr 296 297/* 298 * dma_map_area(start, size, dir) 299 * - start - kernel virtual start address 300 * - size - size of region 301 * - dir - DMA direction 302 */ 303ENTRY(arm920_dma_map_area) 304 add r1, r1, r0 305 cmp r2, #DMA_TO_DEVICE 306 beq arm920_dma_clean_range 307 bcs arm920_dma_inv_range 308 b arm920_dma_flush_range 309ENDPROC(arm920_dma_map_area) 310 311/* 312 * dma_unmap_area(start, size, dir) 313 * - start - kernel virtual start address 314 * - size - size of region 315 * - dir - DMA direction 316 */ 317ENTRY(arm920_dma_unmap_area) 318 mov pc, lr 319ENDPROC(arm920_dma_unmap_area) 320 321 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) 322 define_cache_functions arm920 323#endif 324 325 326ENTRY(cpu_arm920_dcache_clean_area) 3271: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 328 add r0, r0, #CACHE_DLINESIZE 329 subs r1, r1, #CACHE_DLINESIZE 330 bhi 1b 331 mov pc, lr 332 333/* =============================== PageTable ============================== */ 334 335/* 336 * cpu_arm920_switch_mm(pgd) 337 * 338 * Set the translation base pointer to be as described by pgd. 339 * 340 * pgd: new page tables 341 */ 342 .align 5 343ENTRY(cpu_arm920_switch_mm) 344#ifdef CONFIG_MMU 345 mov ip, #0 346#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 347 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 348#else 349@ && 'Clean & Invalidate whole DCache' 350@ && Re-written to use Index Ops. 351@ && Uses registers r1, r3 and ip 352 353 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments 3541: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 3552: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index 356 subs r3, r3, #1 << 26 357 bcs 2b @ entries 63 to 0 358 subs r1, r1, #1 << 5 359 bcs 1b @ segments 7 to 0 360#endif 361 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 362 mcr p15, 0, ip, c7, c10, 4 @ drain WB 363 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 364 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 365#endif 366 mov pc, lr 367 368/* 369 * cpu_arm920_set_pte(ptep, pte, ext) 370 * 371 * Set a PTE and flush it out 372 */ 373 .align 5 374ENTRY(cpu_arm920_set_pte_ext) 375#ifdef CONFIG_MMU 376 armv3_set_pte_ext 377 mov r0, r0 378 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 379 mcr p15, 0, r0, c7, c10, 4 @ drain WB 380#endif 381 mov pc, lr 382 383/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ 384.globl cpu_arm920_suspend_size 385.equ cpu_arm920_suspend_size, 4 * 3 386#ifdef CONFIG_PM_SLEEP 387ENTRY(cpu_arm920_do_suspend) 388 stmfd sp!, {r4 - r6, lr} 389 mrc p15, 0, r4, c13, c0, 0 @ PID 390 mrc p15, 0, r5, c3, c0, 0 @ Domain ID 391 mrc p15, 0, r6, c1, c0, 0 @ Control register 392 stmia r0, {r4 - r6} 393 ldmfd sp!, {r4 - r6, pc} 394ENDPROC(cpu_arm920_do_suspend) 395 396ENTRY(cpu_arm920_do_resume) 397 mov ip, #0 398 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs 399 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches 400 ldmia r0, {r4 - r6} 401 mcr p15, 0, r4, c13, c0, 0 @ PID 402 mcr p15, 0, r5, c3, c0, 0 @ Domain ID 403 mcr p15, 0, r1, c2, c0, 0 @ TTB address 404 mov r0, r6 @ control register 405 b cpu_resume_mmu 406ENDPROC(cpu_arm920_do_resume) 407#endif 408 409 __CPUINIT 410 411 .type __arm920_setup, #function 412__arm920_setup: 413 mov r0, #0 414 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 415 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 416#ifdef CONFIG_MMU 417 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 418#endif 419 adr r5, arm920_crval 420 ldmia r5, {r5, r6} 421 mrc p15, 0, r0, c1, c0 @ get control register v4 422 bic r0, r0, r5 423 orr r0, r0, r6 424 mov pc, lr 425 .size __arm920_setup, . - __arm920_setup 426 427 /* 428 * R 429 * .RVI ZFRS BLDP WCAM 430 * ..11 0001 ..11 0101 431 * 432 */ 433 .type arm920_crval, #object 434arm920_crval: 435 crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130 436 437 __INITDATA 438 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) 439 define_processor_functions arm920, dabort=v4t_early_abort, pabort=legacy_pabort, suspend=1 440 441 .section ".rodata" 442 443 string cpu_arch_name, "armv4t" 444 string cpu_elf_name, "v4" 445 string cpu_arm920_name, "ARM920T" 446 447 .align 448 449 .section ".proc.info.init", #alloc, #execinstr 450 451 .type __arm920_proc_info,#object 452__arm920_proc_info: 453 .long 0x41009200 454 .long 0xff00fff0 455 .long PMD_TYPE_SECT | \ 456 PMD_SECT_BUFFERABLE | \ 457 PMD_SECT_CACHEABLE | \ 458 PMD_BIT4 | \ 459 PMD_SECT_AP_WRITE | \ 460 PMD_SECT_AP_READ 461 .long PMD_TYPE_SECT | \ 462 PMD_BIT4 | \ 463 PMD_SECT_AP_WRITE | \ 464 PMD_SECT_AP_READ 465 b __arm920_setup 466 .long cpu_arch_name 467 .long cpu_elf_name 468 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB 469 .long cpu_arm920_name 470 .long arm920_processor_functions 471 .long v4wbi_tlb_fns 472 .long v4wb_user_fns 473#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 474 .long arm920_cache_fns 475#else 476 .long v4wt_cache_fns 477#endif 478 .size __arm920_proc_info, . - __arm920_proc_info 479