xref: /openbmc/linux/arch/arm/mm/proc-arm740.S (revision 4800cd83)
1/*
2 *  linux/arch/arm/mm/arm740.S: utility functions for ARM740
3 *
4 *  Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11#include <linux/linkage.h>
12#include <linux/init.h>
13#include <asm/assembler.h>
14#include <asm/asm-offsets.h>
15#include <asm/hwcap.h>
16#include <asm/pgtable-hwdef.h>
17#include <asm/pgtable.h>
18#include <asm/ptrace.h>
19
20	.text
21/*
22 * cpu_arm740_proc_init()
23 * cpu_arm740_do_idle()
24 * cpu_arm740_dcache_clean_area()
25 * cpu_arm740_switch_mm()
26 *
27 * These are not required.
28 */
29ENTRY(cpu_arm740_proc_init)
30ENTRY(cpu_arm740_do_idle)
31ENTRY(cpu_arm740_dcache_clean_area)
32ENTRY(cpu_arm740_switch_mm)
33	mov	pc, lr
34
35/*
36 * cpu_arm740_proc_fin()
37 */
38ENTRY(cpu_arm740_proc_fin)
39	mrc	p15, 0, r0, c1, c0, 0
40	bic	r0, r0, #0x3f000000		@ bank/f/lock/s
41	bic	r0, r0, #0x0000000c		@ w-buffer/cache
42	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
43	mov	pc, lr
44
45/*
46 * cpu_arm740_reset(loc)
47 * Params  : r0 = address to jump to
48 * Notes   : This sets up everything for a reset
49 */
50ENTRY(cpu_arm740_reset)
51	mov	ip, #0
52	mcr	p15, 0, ip, c7, c0, 0		@ invalidate cache
53	mrc	p15, 0, ip, c1, c0, 0		@ get ctrl register
54	bic	ip, ip, #0x0000000c		@ ............wc..
55	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
56	mov	pc, r0
57
58	__CPUINIT
59
60	.type	__arm740_setup, #function
61__arm740_setup:
62	mov	r0, #0
63	mcr	p15, 0, r0, c7, c0, 0		@ invalidate caches
64
65	mcr	p15, 0, r0, c6, c3		@ disable area 3~7
66	mcr	p15, 0, r0, c6, c4
67	mcr	p15, 0, r0, c6, c5
68	mcr	p15, 0, r0, c6, c6
69	mcr	p15, 0, r0, c6, c7
70
71	mov	r0, #0x0000003F			@ base = 0, size = 4GB
72	mcr	p15, 0, r0, c6,	c0		@ set area 0, default
73
74	ldr	r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
75	ldr	r1, =(CONFIG_DRAM_SIZE >> 12)	@ size of RAM (must be >= 4KB)
76	mov	r2, #10				@ 11 is the minimum (4KB)
771:	add	r2, r2, #1			@ area size *= 2
78	mov	r1, r1, lsr #1
79	bne	1b				@ count not zero r-shift
80	orr	r0, r0, r2, lsl #1		@ the area register value
81	orr	r0, r0, #1			@ set enable bit
82	mcr	p15, 0, r0, c6,	c1		@ set area 1, RAM
83
84	ldr	r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
85	ldr	r1, =(CONFIG_FLASH_SIZE >> 12)	@ size of FLASH (must be >= 4KB)
86	mov	r2, #10				@ 11 is the minimum (4KB)
871:	add	r2, r2, #1			@ area size *= 2
88	mov	r1, r1, lsr #1
89	bne	1b				@ count not zero r-shift
90	orr	r0, r0, r2, lsl #1		@ the area register value
91	orr	r0, r0, #1			@ set enable bit
92	mcr	p15, 0, r0, c6,	c2		@ set area 2, ROM/FLASH
93
94	mov	r0, #0x06
95	mcr	p15, 0, r0, c2, c0		@ Region 1&2 cacheable
96#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
97	mov	r0, #0x00			@ disable whole write buffer
98#else
99	mov	r0, #0x02			@ Region 1 write bufferred
100#endif
101	mcr	p15, 0, r0, c3, c0
102
103	mov	r0, #0x10000
104	sub	r0, r0, #1			@ r0 = 0xffff
105	mcr	p15, 0, r0, c5, c0		@ all read/write access
106
107	mrc	p15, 0, r0, c1, c0		@ get control register
108	bic	r0, r0, #0x3F000000		@ set to standard caching mode
109						@ need some benchmark
110	orr	r0, r0, #0x0000000d		@ MPU/Cache/WB
111
112	mov	pc, lr
113
114	.size	__arm740_setup, . - __arm740_setup
115
116	__INITDATA
117
118/*
119 * Purpose : Function pointers used to access above functions - all calls
120 *	     come through these
121 */
122	.type	arm740_processor_functions, #object
123ENTRY(arm740_processor_functions)
124	.word	v4t_late_abort
125	.word	legacy_pabort
126	.word	cpu_arm740_proc_init
127	.word	cpu_arm740_proc_fin
128	.word	cpu_arm740_reset
129	.word   cpu_arm740_do_idle
130	.word	cpu_arm740_dcache_clean_area
131	.word	cpu_arm740_switch_mm
132	.word	0			@ cpu_*_set_pte
133	.size	arm740_processor_functions, . - arm740_processor_functions
134
135	.section ".rodata"
136
137	.type	cpu_arch_name, #object
138cpu_arch_name:
139	.asciz	"armv4"
140	.size	cpu_arch_name, . - cpu_arch_name
141
142	.type	cpu_elf_name, #object
143cpu_elf_name:
144	.asciz	"v4"
145	.size	cpu_elf_name, . - cpu_elf_name
146
147	.type	cpu_arm740_name, #object
148cpu_arm740_name:
149	.ascii	"ARM740T"
150	.size	cpu_arm740_name, . - cpu_arm740_name
151
152	.align
153
154	.section ".proc.info.init", #alloc, #execinstr
155	.type	__arm740_proc_info,#object
156__arm740_proc_info:
157	.long	0x41807400
158	.long	0xfffffff0
159	.long	0
160	b	__arm740_setup
161	.long	cpu_arch_name
162	.long	cpu_elf_name
163	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT
164	.long	cpu_arm740_name
165	.long	arm740_processor_functions
166	.long	0
167	.long	0
168	.long	v3_cache_fns			@ cache model
169	.size	__arm740_proc_info, . - __arm740_proc_info
170
171
172