1/* 2 * linux/arch/arm/mm/proc-arm1022.S: MMU functions for ARM1022E 3 * 4 * Copyright (C) 2000 ARM Limited 5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 6 * hacked for non-paged-MM by Hyok S. Choi, 2003. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * 14 * These are the low level assembler for performing cache and TLB 15 * functions on the ARM1022E. 16 */ 17#include <linux/linkage.h> 18#include <linux/init.h> 19#include <asm/assembler.h> 20#include <asm/asm-offsets.h> 21#include <asm/hwcap.h> 22#include <asm/pgtable-hwdef.h> 23#include <asm/pgtable.h> 24#include <asm/ptrace.h> 25 26#include "proc-macros.S" 27 28/* 29 * This is the maximum size of an area which will be invalidated 30 * using the single invalidate entry instructions. Anything larger 31 * than this, and we go for the whole cache. 32 * 33 * This value should be chosen such that we choose the cheapest 34 * alternative. 35 */ 36#define MAX_AREA_SIZE 32768 37 38/* 39 * The size of one data cache line. 40 */ 41#define CACHE_DLINESIZE 32 42 43/* 44 * The number of data cache segments. 45 */ 46#define CACHE_DSEGMENTS 16 47 48/* 49 * The number of lines in a cache segment. 50 */ 51#define CACHE_DENTRIES 64 52 53/* 54 * This is the size at which it becomes more efficient to 55 * clean the whole cache, rather than using the individual 56 * cache line maintainence instructions. 57 */ 58#define CACHE_DLIMIT 32768 59 60 .text 61/* 62 * cpu_arm1022_proc_init() 63 */ 64ENTRY(cpu_arm1022_proc_init) 65 mov pc, lr 66 67/* 68 * cpu_arm1022_proc_fin() 69 */ 70ENTRY(cpu_arm1022_proc_fin) 71 stmfd sp!, {lr} 72 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE 73 msr cpsr_c, ip 74 bl arm1022_flush_kern_cache_all 75 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 76 bic r0, r0, #0x1000 @ ...i............ 77 bic r0, r0, #0x000e @ ............wca. 78 mcr p15, 0, r0, c1, c0, 0 @ disable caches 79 ldmfd sp!, {pc} 80 81/* 82 * cpu_arm1022_reset(loc) 83 * 84 * Perform a soft reset of the system. Put the CPU into the 85 * same state as it would be if it had been reset, and branch 86 * to what would be the reset vector. 87 * 88 * loc: location to jump to for soft reset 89 */ 90 .align 5 91ENTRY(cpu_arm1022_reset) 92 mov ip, #0 93 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 94 mcr p15, 0, ip, c7, c10, 4 @ drain WB 95#ifdef CONFIG_MMU 96 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 97#endif 98 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 99 bic ip, ip, #0x000f @ ............wcam 100 bic ip, ip, #0x1100 @ ...i...s........ 101 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 102 mov pc, r0 103 104/* 105 * cpu_arm1022_do_idle() 106 */ 107 .align 5 108ENTRY(cpu_arm1022_do_idle) 109 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 110 mov pc, lr 111 112/* ================================= CACHE ================================ */ 113 114 .align 5 115/* 116 * flush_user_cache_all() 117 * 118 * Invalidate all cache entries in a particular address 119 * space. 120 */ 121ENTRY(arm1022_flush_user_cache_all) 122 /* FALLTHROUGH */ 123/* 124 * flush_kern_cache_all() 125 * 126 * Clean and invalidate the entire cache. 127 */ 128ENTRY(arm1022_flush_kern_cache_all) 129 mov r2, #VM_EXEC 130 mov ip, #0 131__flush_whole_cache: 132#ifndef CONFIG_CPU_DCACHE_DISABLE 133 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments 1341: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 1352: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 136 subs r3, r3, #1 << 26 137 bcs 2b @ entries 63 to 0 138 subs r1, r1, #1 << 5 139 bcs 1b @ segments 15 to 0 140#endif 141 tst r2, #VM_EXEC 142#ifndef CONFIG_CPU_ICACHE_DISABLE 143 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 144#endif 145 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 146 mov pc, lr 147 148/* 149 * flush_user_cache_range(start, end, flags) 150 * 151 * Invalidate a range of cache entries in the specified 152 * address space. 153 * 154 * - start - start address (inclusive) 155 * - end - end address (exclusive) 156 * - flags - vm_flags for this space 157 */ 158ENTRY(arm1022_flush_user_cache_range) 159 mov ip, #0 160 sub r3, r1, r0 @ calculate total size 161 cmp r3, #CACHE_DLIMIT 162 bhs __flush_whole_cache 163 164#ifndef CONFIG_CPU_DCACHE_DISABLE 1651: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 166 add r0, r0, #CACHE_DLINESIZE 167 cmp r0, r1 168 blo 1b 169#endif 170 tst r2, #VM_EXEC 171#ifndef CONFIG_CPU_ICACHE_DISABLE 172 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 173#endif 174 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 175 mov pc, lr 176 177/* 178 * coherent_kern_range(start, end) 179 * 180 * Ensure coherency between the Icache and the Dcache in the 181 * region described by start. If you have non-snooping 182 * Harvard caches, you need to implement this function. 183 * 184 * - start - virtual start address 185 * - end - virtual end address 186 */ 187ENTRY(arm1022_coherent_kern_range) 188 /* FALLTHROUGH */ 189 190/* 191 * coherent_user_range(start, end) 192 * 193 * Ensure coherency between the Icache and the Dcache in the 194 * region described by start. If you have non-snooping 195 * Harvard caches, you need to implement this function. 196 * 197 * - start - virtual start address 198 * - end - virtual end address 199 */ 200ENTRY(arm1022_coherent_user_range) 201 mov ip, #0 202 bic r0, r0, #CACHE_DLINESIZE - 1 2031: 204#ifndef CONFIG_CPU_DCACHE_DISABLE 205 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 206#endif 207#ifndef CONFIG_CPU_ICACHE_DISABLE 208 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 209#endif 210 add r0, r0, #CACHE_DLINESIZE 211 cmp r0, r1 212 blo 1b 213 mcr p15, 0, ip, c7, c10, 4 @ drain WB 214 mov pc, lr 215 216/* 217 * flush_kern_dcache_area(void *addr, size_t size) 218 * 219 * Ensure no D cache aliasing occurs, either with itself or 220 * the I cache 221 * 222 * - addr - kernel address 223 * - size - region size 224 */ 225ENTRY(arm1022_flush_kern_dcache_area) 226 mov ip, #0 227#ifndef CONFIG_CPU_DCACHE_DISABLE 228 add r1, r0, r1 2291: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 230 add r0, r0, #CACHE_DLINESIZE 231 cmp r0, r1 232 blo 1b 233#endif 234 mcr p15, 0, ip, c7, c10, 4 @ drain WB 235 mov pc, lr 236 237/* 238 * dma_inv_range(start, end) 239 * 240 * Invalidate (discard) the specified virtual address range. 241 * May not write back any entries. If 'start' or 'end' 242 * are not cache line aligned, those lines must be written 243 * back. 244 * 245 * - start - virtual start address 246 * - end - virtual end address 247 * 248 * (same as v4wb) 249 */ 250ENTRY(arm1022_dma_inv_range) 251 mov ip, #0 252#ifndef CONFIG_CPU_DCACHE_DISABLE 253 tst r0, #CACHE_DLINESIZE - 1 254 bic r0, r0, #CACHE_DLINESIZE - 1 255 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 256 tst r1, #CACHE_DLINESIZE - 1 257 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 2581: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 259 add r0, r0, #CACHE_DLINESIZE 260 cmp r0, r1 261 blo 1b 262#endif 263 mcr p15, 0, ip, c7, c10, 4 @ drain WB 264 mov pc, lr 265 266/* 267 * dma_clean_range(start, end) 268 * 269 * Clean the specified virtual address range. 270 * 271 * - start - virtual start address 272 * - end - virtual end address 273 * 274 * (same as v4wb) 275 */ 276ENTRY(arm1022_dma_clean_range) 277 mov ip, #0 278#ifndef CONFIG_CPU_DCACHE_DISABLE 279 bic r0, r0, #CACHE_DLINESIZE - 1 2801: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 281 add r0, r0, #CACHE_DLINESIZE 282 cmp r0, r1 283 blo 1b 284#endif 285 mcr p15, 0, ip, c7, c10, 4 @ drain WB 286 mov pc, lr 287 288/* 289 * dma_flush_range(start, end) 290 * 291 * Clean and invalidate the specified virtual address range. 292 * 293 * - start - virtual start address 294 * - end - virtual end address 295 */ 296ENTRY(arm1022_dma_flush_range) 297 mov ip, #0 298#ifndef CONFIG_CPU_DCACHE_DISABLE 299 bic r0, r0, #CACHE_DLINESIZE - 1 3001: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 301 add r0, r0, #CACHE_DLINESIZE 302 cmp r0, r1 303 blo 1b 304#endif 305 mcr p15, 0, ip, c7, c10, 4 @ drain WB 306 mov pc, lr 307 308ENTRY(arm1022_cache_fns) 309 .long arm1022_flush_kern_cache_all 310 .long arm1022_flush_user_cache_all 311 .long arm1022_flush_user_cache_range 312 .long arm1022_coherent_kern_range 313 .long arm1022_coherent_user_range 314 .long arm1022_flush_kern_dcache_area 315 .long arm1022_dma_inv_range 316 .long arm1022_dma_clean_range 317 .long arm1022_dma_flush_range 318 319 .align 5 320ENTRY(cpu_arm1022_dcache_clean_area) 321#ifndef CONFIG_CPU_DCACHE_DISABLE 322 mov ip, #0 3231: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 324 add r0, r0, #CACHE_DLINESIZE 325 subs r1, r1, #CACHE_DLINESIZE 326 bhi 1b 327#endif 328 mov pc, lr 329 330/* =============================== PageTable ============================== */ 331 332/* 333 * cpu_arm1022_switch_mm(pgd) 334 * 335 * Set the translation base pointer to be as described by pgd. 336 * 337 * pgd: new page tables 338 */ 339 .align 5 340ENTRY(cpu_arm1022_switch_mm) 341#ifdef CONFIG_MMU 342#ifndef CONFIG_CPU_DCACHE_DISABLE 343 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments 3441: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 3452: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 346 subs r3, r3, #1 << 26 347 bcs 2b @ entries 63 to 0 348 subs r1, r1, #1 << 5 349 bcs 1b @ segments 15 to 0 350#endif 351 mov r1, #0 352#ifndef CONFIG_CPU_ICACHE_DISABLE 353 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 354#endif 355 mcr p15, 0, r1, c7, c10, 4 @ drain WB 356 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 357 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 358#endif 359 mov pc, lr 360 361/* 362 * cpu_arm1022_set_pte_ext(ptep, pte, ext) 363 * 364 * Set a PTE and flush it out 365 */ 366 .align 5 367ENTRY(cpu_arm1022_set_pte_ext) 368#ifdef CONFIG_MMU 369 armv3_set_pte_ext 370 mov r0, r0 371#ifndef CONFIG_CPU_DCACHE_DISABLE 372 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 373#endif 374#endif /* CONFIG_MMU */ 375 mov pc, lr 376 377 __INIT 378 379 .type __arm1022_setup, #function 380__arm1022_setup: 381 mov r0, #0 382 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 383 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 384#ifdef CONFIG_MMU 385 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 386#endif 387 adr r5, arm1022_crval 388 ldmia r5, {r5, r6} 389 mrc p15, 0, r0, c1, c0 @ get control register v4 390 bic r0, r0, r5 391 orr r0, r0, r6 392#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 393 orr r0, r0, #0x4000 @ .R.............. 394#endif 395 mov pc, lr 396 .size __arm1022_setup, . - __arm1022_setup 397 398 /* 399 * R 400 * .RVI ZFRS BLDP WCAM 401 * .011 1001 ..11 0101 402 * 403 */ 404 .type arm1022_crval, #object 405arm1022_crval: 406 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930 407 408 __INITDATA 409 410/* 411 * Purpose : Function pointers used to access above functions - all calls 412 * come through these 413 */ 414 .type arm1022_processor_functions, #object 415arm1022_processor_functions: 416 .word v4t_early_abort 417 .word legacy_pabort 418 .word cpu_arm1022_proc_init 419 .word cpu_arm1022_proc_fin 420 .word cpu_arm1022_reset 421 .word cpu_arm1022_do_idle 422 .word cpu_arm1022_dcache_clean_area 423 .word cpu_arm1022_switch_mm 424 .word cpu_arm1022_set_pte_ext 425 .size arm1022_processor_functions, . - arm1022_processor_functions 426 427 .section ".rodata" 428 429 .type cpu_arch_name, #object 430cpu_arch_name: 431 .asciz "armv5te" 432 .size cpu_arch_name, . - cpu_arch_name 433 434 .type cpu_elf_name, #object 435cpu_elf_name: 436 .asciz "v5" 437 .size cpu_elf_name, . - cpu_elf_name 438 439 .type cpu_arm1022_name, #object 440cpu_arm1022_name: 441 .asciz "ARM1022" 442 .size cpu_arm1022_name, . - cpu_arm1022_name 443 444 .align 445 446 .section ".proc.info.init", #alloc, #execinstr 447 448 .type __arm1022_proc_info,#object 449__arm1022_proc_info: 450 .long 0x4105a220 @ ARM 1022E (v5TE) 451 .long 0xff0ffff0 452 .long PMD_TYPE_SECT | \ 453 PMD_BIT4 | \ 454 PMD_SECT_AP_WRITE | \ 455 PMD_SECT_AP_READ 456 .long PMD_TYPE_SECT | \ 457 PMD_BIT4 | \ 458 PMD_SECT_AP_WRITE | \ 459 PMD_SECT_AP_READ 460 b __arm1022_setup 461 .long cpu_arch_name 462 .long cpu_elf_name 463 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP 464 .long cpu_arm1022_name 465 .long arm1022_processor_functions 466 .long v4wbi_tlb_fns 467 .long v4wb_user_fns 468 .long arm1022_cache_fns 469 .size __arm1022_proc_info, . - __arm1022_proc_info 470