1/* 2 * linux/arch/arm/mm/proc-arm1020.S: MMU functions for ARM1020 3 * 4 * Copyright (C) 2000 ARM Limited 5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 6 * hacked for non-paged-MM by Hyok S. Choi, 2003. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * 22 * 23 * These are the low level assembler for performing cache and TLB 24 * functions on the arm1020. 25 * 26 * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt 27 */ 28#include <linux/linkage.h> 29#include <linux/init.h> 30#include <asm/assembler.h> 31#include <asm/asm-offsets.h> 32#include <asm/hwcap.h> 33#include <asm/pgtable-hwdef.h> 34#include <asm/pgtable.h> 35#include <asm/ptrace.h> 36 37#include "proc-macros.S" 38 39/* 40 * This is the maximum size of an area which will be invalidated 41 * using the single invalidate entry instructions. Anything larger 42 * than this, and we go for the whole cache. 43 * 44 * This value should be chosen such that we choose the cheapest 45 * alternative. 46 */ 47#define MAX_AREA_SIZE 32768 48 49/* 50 * The size of one data cache line. 51 */ 52#define CACHE_DLINESIZE 32 53 54/* 55 * The number of data cache segments. 56 */ 57#define CACHE_DSEGMENTS 16 58 59/* 60 * The number of lines in a cache segment. 61 */ 62#define CACHE_DENTRIES 64 63 64/* 65 * This is the size at which it becomes more efficient to 66 * clean the whole cache, rather than using the individual 67 * cache line maintainence instructions. 68 */ 69#define CACHE_DLIMIT 32768 70 71 .text 72/* 73 * cpu_arm1020_proc_init() 74 */ 75ENTRY(cpu_arm1020_proc_init) 76 mov pc, lr 77 78/* 79 * cpu_arm1020_proc_fin() 80 */ 81ENTRY(cpu_arm1020_proc_fin) 82 stmfd sp!, {lr} 83 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE 84 msr cpsr_c, ip 85 bl arm1020_flush_kern_cache_all 86 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 87 bic r0, r0, #0x1000 @ ...i............ 88 bic r0, r0, #0x000e @ ............wca. 89 mcr p15, 0, r0, c1, c0, 0 @ disable caches 90 ldmfd sp!, {pc} 91 92/* 93 * cpu_arm1020_reset(loc) 94 * 95 * Perform a soft reset of the system. Put the CPU into the 96 * same state as it would be if it had been reset, and branch 97 * to what would be the reset vector. 98 * 99 * loc: location to jump to for soft reset 100 */ 101 .align 5 102ENTRY(cpu_arm1020_reset) 103 mov ip, #0 104 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 105 mcr p15, 0, ip, c7, c10, 4 @ drain WB 106#ifdef CONFIG_MMU 107 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 108#endif 109 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 110 bic ip, ip, #0x000f @ ............wcam 111 bic ip, ip, #0x1100 @ ...i...s........ 112 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 113 mov pc, r0 114 115/* 116 * cpu_arm1020_do_idle() 117 */ 118 .align 5 119ENTRY(cpu_arm1020_do_idle) 120 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 121 mov pc, lr 122 123/* ================================= CACHE ================================ */ 124 125 .align 5 126/* 127 * flush_user_cache_all() 128 * 129 * Invalidate all cache entries in a particular address 130 * space. 131 */ 132ENTRY(arm1020_flush_user_cache_all) 133 /* FALLTHROUGH */ 134/* 135 * flush_kern_cache_all() 136 * 137 * Clean and invalidate the entire cache. 138 */ 139ENTRY(arm1020_flush_kern_cache_all) 140 mov r2, #VM_EXEC 141 mov ip, #0 142__flush_whole_cache: 143#ifndef CONFIG_CPU_DCACHE_DISABLE 144 mcr p15, 0, ip, c7, c10, 4 @ drain WB 145 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments 1461: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 1472: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 148 mcr p15, 0, ip, c7, c10, 4 @ drain WB 149 subs r3, r3, #1 << 26 150 bcs 2b @ entries 63 to 0 151 subs r1, r1, #1 << 5 152 bcs 1b @ segments 15 to 0 153#endif 154 tst r2, #VM_EXEC 155#ifndef CONFIG_CPU_ICACHE_DISABLE 156 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 157#endif 158 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 159 mov pc, lr 160 161/* 162 * flush_user_cache_range(start, end, flags) 163 * 164 * Invalidate a range of cache entries in the specified 165 * address space. 166 * 167 * - start - start address (inclusive) 168 * - end - end address (exclusive) 169 * - flags - vm_flags for this space 170 */ 171ENTRY(arm1020_flush_user_cache_range) 172 mov ip, #0 173 sub r3, r1, r0 @ calculate total size 174 cmp r3, #CACHE_DLIMIT 175 bhs __flush_whole_cache 176 177#ifndef CONFIG_CPU_DCACHE_DISABLE 178 mcr p15, 0, ip, c7, c10, 4 1791: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 180 mcr p15, 0, ip, c7, c10, 4 @ drain WB 181 add r0, r0, #CACHE_DLINESIZE 182 cmp r0, r1 183 blo 1b 184#endif 185 tst r2, #VM_EXEC 186#ifndef CONFIG_CPU_ICACHE_DISABLE 187 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 188#endif 189 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 190 mov pc, lr 191 192/* 193 * coherent_kern_range(start, end) 194 * 195 * Ensure coherency between the Icache and the Dcache in the 196 * region described by start. If you have non-snooping 197 * Harvard caches, you need to implement this function. 198 * 199 * - start - virtual start address 200 * - end - virtual end address 201 */ 202ENTRY(arm1020_coherent_kern_range) 203 /* FALLTRHOUGH */ 204 205/* 206 * coherent_user_range(start, end) 207 * 208 * Ensure coherency between the Icache and the Dcache in the 209 * region described by start. If you have non-snooping 210 * Harvard caches, you need to implement this function. 211 * 212 * - start - virtual start address 213 * - end - virtual end address 214 */ 215ENTRY(arm1020_coherent_user_range) 216 mov ip, #0 217 bic r0, r0, #CACHE_DLINESIZE - 1 218 mcr p15, 0, ip, c7, c10, 4 2191: 220#ifndef CONFIG_CPU_DCACHE_DISABLE 221 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 222 mcr p15, 0, ip, c7, c10, 4 @ drain WB 223#endif 224#ifndef CONFIG_CPU_ICACHE_DISABLE 225 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 226#endif 227 add r0, r0, #CACHE_DLINESIZE 228 cmp r0, r1 229 blo 1b 230 mcr p15, 0, ip, c7, c10, 4 @ drain WB 231 mov pc, lr 232 233/* 234 * flush_kern_dcache_area(void *addr, size_t size) 235 * 236 * Ensure no D cache aliasing occurs, either with itself or 237 * the I cache 238 * 239 * - addr - kernel address 240 * - size - region size 241 */ 242ENTRY(arm1020_flush_kern_dcache_area) 243 mov ip, #0 244#ifndef CONFIG_CPU_DCACHE_DISABLE 245 add r1, r0, r1 2461: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 247 mcr p15, 0, ip, c7, c10, 4 @ drain WB 248 add r0, r0, #CACHE_DLINESIZE 249 cmp r0, r1 250 blo 1b 251#endif 252 mcr p15, 0, ip, c7, c10, 4 @ drain WB 253 mov pc, lr 254 255/* 256 * dma_inv_range(start, end) 257 * 258 * Invalidate (discard) the specified virtual address range. 259 * May not write back any entries. If 'start' or 'end' 260 * are not cache line aligned, those lines must be written 261 * back. 262 * 263 * - start - virtual start address 264 * - end - virtual end address 265 * 266 * (same as v4wb) 267 */ 268ENTRY(arm1020_dma_inv_range) 269 mov ip, #0 270#ifndef CONFIG_CPU_DCACHE_DISABLE 271 tst r0, #CACHE_DLINESIZE - 1 272 bic r0, r0, #CACHE_DLINESIZE - 1 273 mcrne p15, 0, ip, c7, c10, 4 274 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 275 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 276 tst r1, #CACHE_DLINESIZE - 1 277 mcrne p15, 0, ip, c7, c10, 4 278 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 279 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 2801: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 281 add r0, r0, #CACHE_DLINESIZE 282 cmp r0, r1 283 blo 1b 284#endif 285 mcr p15, 0, ip, c7, c10, 4 @ drain WB 286 mov pc, lr 287 288/* 289 * dma_clean_range(start, end) 290 * 291 * Clean the specified virtual address range. 292 * 293 * - start - virtual start address 294 * - end - virtual end address 295 * 296 * (same as v4wb) 297 */ 298ENTRY(arm1020_dma_clean_range) 299 mov ip, #0 300#ifndef CONFIG_CPU_DCACHE_DISABLE 301 bic r0, r0, #CACHE_DLINESIZE - 1 3021: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 303 mcr p15, 0, ip, c7, c10, 4 @ drain WB 304 add r0, r0, #CACHE_DLINESIZE 305 cmp r0, r1 306 blo 1b 307#endif 308 mcr p15, 0, ip, c7, c10, 4 @ drain WB 309 mov pc, lr 310 311/* 312 * dma_flush_range(start, end) 313 * 314 * Clean and invalidate the specified virtual address range. 315 * 316 * - start - virtual start address 317 * - end - virtual end address 318 */ 319ENTRY(arm1020_dma_flush_range) 320 mov ip, #0 321#ifndef CONFIG_CPU_DCACHE_DISABLE 322 bic r0, r0, #CACHE_DLINESIZE - 1 323 mcr p15, 0, ip, c7, c10, 4 3241: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 325 mcr p15, 0, ip, c7, c10, 4 @ drain WB 326 add r0, r0, #CACHE_DLINESIZE 327 cmp r0, r1 328 blo 1b 329#endif 330 mcr p15, 0, ip, c7, c10, 4 @ drain WB 331 mov pc, lr 332 333ENTRY(arm1020_cache_fns) 334 .long arm1020_flush_kern_cache_all 335 .long arm1020_flush_user_cache_all 336 .long arm1020_flush_user_cache_range 337 .long arm1020_coherent_kern_range 338 .long arm1020_coherent_user_range 339 .long arm1020_flush_kern_dcache_area 340 .long arm1020_dma_inv_range 341 .long arm1020_dma_clean_range 342 .long arm1020_dma_flush_range 343 344 .align 5 345ENTRY(cpu_arm1020_dcache_clean_area) 346#ifndef CONFIG_CPU_DCACHE_DISABLE 347 mov ip, #0 3481: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 349 mcr p15, 0, ip, c7, c10, 4 @ drain WB 350 add r0, r0, #CACHE_DLINESIZE 351 subs r1, r1, #CACHE_DLINESIZE 352 bhi 1b 353#endif 354 mov pc, lr 355 356/* =============================== PageTable ============================== */ 357 358/* 359 * cpu_arm1020_switch_mm(pgd) 360 * 361 * Set the translation base pointer to be as described by pgd. 362 * 363 * pgd: new page tables 364 */ 365 .align 5 366ENTRY(cpu_arm1020_switch_mm) 367#ifdef CONFIG_MMU 368#ifndef CONFIG_CPU_DCACHE_DISABLE 369 mcr p15, 0, r3, c7, c10, 4 370 mov r1, #0xF @ 16 segments 3711: mov r3, #0x3F @ 64 entries 3722: mov ip, r3, LSL #26 @ shift up entry 373 orr ip, ip, r1, LSL #5 @ shift in/up index 374 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry 375 mov ip, #0 376 mcr p15, 0, ip, c7, c10, 4 377 subs r3, r3, #1 378 cmp r3, #0 379 bge 2b @ entries 3F to 0 380 subs r1, r1, #1 381 cmp r1, #0 382 bge 1b @ segments 15 to 0 383 384#endif 385 mov r1, #0 386#ifndef CONFIG_CPU_ICACHE_DISABLE 387 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 388#endif 389 mcr p15, 0, r1, c7, c10, 4 @ drain WB 390 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 391 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 392#endif /* CONFIG_MMU */ 393 mov pc, lr 394 395/* 396 * cpu_arm1020_set_pte(ptep, pte) 397 * 398 * Set a PTE and flush it out 399 */ 400 .align 5 401ENTRY(cpu_arm1020_set_pte_ext) 402#ifdef CONFIG_MMU 403 armv3_set_pte_ext 404 mov r0, r0 405#ifndef CONFIG_CPU_DCACHE_DISABLE 406 mcr p15, 0, r0, c7, c10, 4 407 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 408#endif 409 mcr p15, 0, r0, c7, c10, 4 @ drain WB 410#endif /* CONFIG_MMU */ 411 mov pc, lr 412 413 __INIT 414 415 .type __arm1020_setup, #function 416__arm1020_setup: 417 mov r0, #0 418 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 419 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 420#ifdef CONFIG_MMU 421 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 422#endif 423 424 adr r5, arm1020_crval 425 ldmia r5, {r5, r6} 426 mrc p15, 0, r0, c1, c0 @ get control register v4 427 bic r0, r0, r5 428 orr r0, r0, r6 429#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 430 orr r0, r0, #0x4000 @ .R.. .... .... .... 431#endif 432 mov pc, lr 433 .size __arm1020_setup, . - __arm1020_setup 434 435 /* 436 * R 437 * .RVI ZFRS BLDP WCAM 438 * .011 1001 ..11 0101 439 */ 440 .type arm1020_crval, #object 441arm1020_crval: 442 crval clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930 443 444 __INITDATA 445 446/* 447 * Purpose : Function pointers used to access above functions - all calls 448 * come through these 449 */ 450 .type arm1020_processor_functions, #object 451arm1020_processor_functions: 452 .word v4t_early_abort 453 .word legacy_pabort 454 .word cpu_arm1020_proc_init 455 .word cpu_arm1020_proc_fin 456 .word cpu_arm1020_reset 457 .word cpu_arm1020_do_idle 458 .word cpu_arm1020_dcache_clean_area 459 .word cpu_arm1020_switch_mm 460 .word cpu_arm1020_set_pte_ext 461 .size arm1020_processor_functions, . - arm1020_processor_functions 462 463 .section ".rodata" 464 465 .type cpu_arch_name, #object 466cpu_arch_name: 467 .asciz "armv5t" 468 .size cpu_arch_name, . - cpu_arch_name 469 470 .type cpu_elf_name, #object 471cpu_elf_name: 472 .asciz "v5" 473 .size cpu_elf_name, . - cpu_elf_name 474 475 .type cpu_arm1020_name, #object 476cpu_arm1020_name: 477 .ascii "ARM1020" 478#ifndef CONFIG_CPU_ICACHE_DISABLE 479 .ascii "i" 480#endif 481#ifndef CONFIG_CPU_DCACHE_DISABLE 482 .ascii "d" 483#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 484 .ascii "(wt)" 485#else 486 .ascii "(wb)" 487#endif 488#endif 489#ifndef CONFIG_CPU_BPREDICT_DISABLE 490 .ascii "B" 491#endif 492#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 493 .ascii "RR" 494#endif 495 .ascii "\0" 496 .size cpu_arm1020_name, . - cpu_arm1020_name 497 498 .align 499 500 .section ".proc.info.init", #alloc, #execinstr 501 502 .type __arm1020_proc_info,#object 503__arm1020_proc_info: 504 .long 0x4104a200 @ ARM 1020T (Architecture v5T) 505 .long 0xff0ffff0 506 .long PMD_TYPE_SECT | \ 507 PMD_SECT_AP_WRITE | \ 508 PMD_SECT_AP_READ 509 .long PMD_TYPE_SECT | \ 510 PMD_SECT_AP_WRITE | \ 511 PMD_SECT_AP_READ 512 b __arm1020_setup 513 .long cpu_arch_name 514 .long cpu_elf_name 515 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB 516 .long cpu_arm1020_name 517 .long arm1020_processor_functions 518 .long v4wbi_tlb_fns 519 .long v4wb_user_fns 520 .long arm1020_cache_fns 521 .size __arm1020_proc_info, . - __arm1020_proc_info 522