1/* 2 * linux/arch/arm/mm/proc-arm1020.S: MMU functions for ARM1020 3 * 4 * Copyright (C) 2000 ARM Limited 5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 6 * hacked for non-paged-MM by Hyok S. Choi, 2003. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * 22 * 23 * These are the low level assembler for performing cache and TLB 24 * functions on the arm1020. 25 * 26 * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt 27 */ 28#include <linux/linkage.h> 29#include <linux/init.h> 30#include <asm/assembler.h> 31#include <asm/asm-offsets.h> 32#include <asm/hwcap.h> 33#include <asm/pgtable-hwdef.h> 34#include <asm/pgtable.h> 35#include <asm/ptrace.h> 36 37#include "proc-macros.S" 38 39/* 40 * This is the maximum size of an area which will be invalidated 41 * using the single invalidate entry instructions. Anything larger 42 * than this, and we go for the whole cache. 43 * 44 * This value should be chosen such that we choose the cheapest 45 * alternative. 46 */ 47#define MAX_AREA_SIZE 32768 48 49/* 50 * The size of one data cache line. 51 */ 52#define CACHE_DLINESIZE 32 53 54/* 55 * The number of data cache segments. 56 */ 57#define CACHE_DSEGMENTS 16 58 59/* 60 * The number of lines in a cache segment. 61 */ 62#define CACHE_DENTRIES 64 63 64/* 65 * This is the size at which it becomes more efficient to 66 * clean the whole cache, rather than using the individual 67 * cache line maintainence instructions. 68 */ 69#define CACHE_DLIMIT 32768 70 71 .text 72/* 73 * cpu_arm1020_proc_init() 74 */ 75ENTRY(cpu_arm1020_proc_init) 76 mov pc, lr 77 78/* 79 * cpu_arm1020_proc_fin() 80 */ 81ENTRY(cpu_arm1020_proc_fin) 82 stmfd sp!, {lr} 83 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE 84 msr cpsr_c, ip 85 bl arm1020_flush_kern_cache_all 86 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 87 bic r0, r0, #0x1000 @ ...i............ 88 bic r0, r0, #0x000e @ ............wca. 89 mcr p15, 0, r0, c1, c0, 0 @ disable caches 90 ldmfd sp!, {pc} 91 92/* 93 * cpu_arm1020_reset(loc) 94 * 95 * Perform a soft reset of the system. Put the CPU into the 96 * same state as it would be if it had been reset, and branch 97 * to what would be the reset vector. 98 * 99 * loc: location to jump to for soft reset 100 */ 101 .align 5 102ENTRY(cpu_arm1020_reset) 103 mov ip, #0 104 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 105 mcr p15, 0, ip, c7, c10, 4 @ drain WB 106#ifdef CONFIG_MMU 107 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 108#endif 109 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 110 bic ip, ip, #0x000f @ ............wcam 111 bic ip, ip, #0x1100 @ ...i...s........ 112 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 113 mov pc, r0 114 115/* 116 * cpu_arm1020_do_idle() 117 */ 118 .align 5 119ENTRY(cpu_arm1020_do_idle) 120 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 121 mov pc, lr 122 123/* ================================= CACHE ================================ */ 124 125 .align 5 126/* 127 * flush_user_cache_all() 128 * 129 * Invalidate all cache entries in a particular address 130 * space. 131 */ 132ENTRY(arm1020_flush_user_cache_all) 133 /* FALLTHROUGH */ 134/* 135 * flush_kern_cache_all() 136 * 137 * Clean and invalidate the entire cache. 138 */ 139ENTRY(arm1020_flush_kern_cache_all) 140 mov r2, #VM_EXEC 141 mov ip, #0 142__flush_whole_cache: 143#ifndef CONFIG_CPU_DCACHE_DISABLE 144 mcr p15, 0, ip, c7, c10, 4 @ drain WB 145 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments 1461: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 1472: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 148 mcr p15, 0, ip, c7, c10, 4 @ drain WB 149 subs r3, r3, #1 << 26 150 bcs 2b @ entries 63 to 0 151 subs r1, r1, #1 << 5 152 bcs 1b @ segments 15 to 0 153#endif 154 tst r2, #VM_EXEC 155#ifndef CONFIG_CPU_ICACHE_DISABLE 156 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 157#endif 158 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 159 mov pc, lr 160 161/* 162 * flush_user_cache_range(start, end, flags) 163 * 164 * Invalidate a range of cache entries in the specified 165 * address space. 166 * 167 * - start - start address (inclusive) 168 * - end - end address (exclusive) 169 * - flags - vm_flags for this space 170 */ 171ENTRY(arm1020_flush_user_cache_range) 172 mov ip, #0 173 sub r3, r1, r0 @ calculate total size 174 cmp r3, #CACHE_DLIMIT 175 bhs __flush_whole_cache 176 177#ifndef CONFIG_CPU_DCACHE_DISABLE 178 mcr p15, 0, ip, c7, c10, 4 1791: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 180 mcr p15, 0, ip, c7, c10, 4 @ drain WB 181 add r0, r0, #CACHE_DLINESIZE 182 cmp r0, r1 183 blo 1b 184#endif 185 tst r2, #VM_EXEC 186#ifndef CONFIG_CPU_ICACHE_DISABLE 187 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 188#endif 189 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 190 mov pc, lr 191 192/* 193 * coherent_kern_range(start, end) 194 * 195 * Ensure coherency between the Icache and the Dcache in the 196 * region described by start. If you have non-snooping 197 * Harvard caches, you need to implement this function. 198 * 199 * - start - virtual start address 200 * - end - virtual end address 201 */ 202ENTRY(arm1020_coherent_kern_range) 203 /* FALLTRHOUGH */ 204 205/* 206 * coherent_user_range(start, end) 207 * 208 * Ensure coherency between the Icache and the Dcache in the 209 * region described by start. If you have non-snooping 210 * Harvard caches, you need to implement this function. 211 * 212 * - start - virtual start address 213 * - end - virtual end address 214 */ 215ENTRY(arm1020_coherent_user_range) 216 mov ip, #0 217 bic r0, r0, #CACHE_DLINESIZE - 1 218 mcr p15, 0, ip, c7, c10, 4 2191: 220#ifndef CONFIG_CPU_DCACHE_DISABLE 221 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 222 mcr p15, 0, ip, c7, c10, 4 @ drain WB 223#endif 224#ifndef CONFIG_CPU_ICACHE_DISABLE 225 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 226#endif 227 add r0, r0, #CACHE_DLINESIZE 228 cmp r0, r1 229 blo 1b 230 mcr p15, 0, ip, c7, c10, 4 @ drain WB 231 mov pc, lr 232 233/* 234 * flush_kern_dcache_page(void *page) 235 * 236 * Ensure no D cache aliasing occurs, either with itself or 237 * the I cache 238 * 239 * - page - page aligned address 240 */ 241ENTRY(arm1020_flush_kern_dcache_page) 242 mov ip, #0 243#ifndef CONFIG_CPU_DCACHE_DISABLE 244 add r1, r0, #PAGE_SZ 2451: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 246 mcr p15, 0, ip, c7, c10, 4 @ drain WB 247 add r0, r0, #CACHE_DLINESIZE 248 cmp r0, r1 249 blo 1b 250#endif 251 mcr p15, 0, ip, c7, c10, 4 @ drain WB 252 mov pc, lr 253 254/* 255 * dma_inv_range(start, end) 256 * 257 * Invalidate (discard) the specified virtual address range. 258 * May not write back any entries. If 'start' or 'end' 259 * are not cache line aligned, those lines must be written 260 * back. 261 * 262 * - start - virtual start address 263 * - end - virtual end address 264 * 265 * (same as v4wb) 266 */ 267ENTRY(arm1020_dma_inv_range) 268 mov ip, #0 269#ifndef CONFIG_CPU_DCACHE_DISABLE 270 tst r0, #CACHE_DLINESIZE - 1 271 bic r0, r0, #CACHE_DLINESIZE - 1 272 mcrne p15, 0, ip, c7, c10, 4 273 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 274 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 275 tst r1, #CACHE_DLINESIZE - 1 276 mcrne p15, 0, ip, c7, c10, 4 277 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 278 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 2791: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 280 add r0, r0, #CACHE_DLINESIZE 281 cmp r0, r1 282 blo 1b 283#endif 284 mcr p15, 0, ip, c7, c10, 4 @ drain WB 285 mov pc, lr 286 287/* 288 * dma_clean_range(start, end) 289 * 290 * Clean the specified virtual address range. 291 * 292 * - start - virtual start address 293 * - end - virtual end address 294 * 295 * (same as v4wb) 296 */ 297ENTRY(arm1020_dma_clean_range) 298 mov ip, #0 299#ifndef CONFIG_CPU_DCACHE_DISABLE 300 bic r0, r0, #CACHE_DLINESIZE - 1 3011: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 302 mcr p15, 0, ip, c7, c10, 4 @ drain WB 303 add r0, r0, #CACHE_DLINESIZE 304 cmp r0, r1 305 blo 1b 306#endif 307 mcr p15, 0, ip, c7, c10, 4 @ drain WB 308 mov pc, lr 309 310/* 311 * dma_flush_range(start, end) 312 * 313 * Clean and invalidate the specified virtual address range. 314 * 315 * - start - virtual start address 316 * - end - virtual end address 317 */ 318ENTRY(arm1020_dma_flush_range) 319 mov ip, #0 320#ifndef CONFIG_CPU_DCACHE_DISABLE 321 bic r0, r0, #CACHE_DLINESIZE - 1 322 mcr p15, 0, ip, c7, c10, 4 3231: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 324 mcr p15, 0, ip, c7, c10, 4 @ drain WB 325 add r0, r0, #CACHE_DLINESIZE 326 cmp r0, r1 327 blo 1b 328#endif 329 mcr p15, 0, ip, c7, c10, 4 @ drain WB 330 mov pc, lr 331 332ENTRY(arm1020_cache_fns) 333 .long arm1020_flush_kern_cache_all 334 .long arm1020_flush_user_cache_all 335 .long arm1020_flush_user_cache_range 336 .long arm1020_coherent_kern_range 337 .long arm1020_coherent_user_range 338 .long arm1020_flush_kern_dcache_page 339 .long arm1020_dma_inv_range 340 .long arm1020_dma_clean_range 341 .long arm1020_dma_flush_range 342 343 .align 5 344ENTRY(cpu_arm1020_dcache_clean_area) 345#ifndef CONFIG_CPU_DCACHE_DISABLE 346 mov ip, #0 3471: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 348 mcr p15, 0, ip, c7, c10, 4 @ drain WB 349 add r0, r0, #CACHE_DLINESIZE 350 subs r1, r1, #CACHE_DLINESIZE 351 bhi 1b 352#endif 353 mov pc, lr 354 355/* =============================== PageTable ============================== */ 356 357/* 358 * cpu_arm1020_switch_mm(pgd) 359 * 360 * Set the translation base pointer to be as described by pgd. 361 * 362 * pgd: new page tables 363 */ 364 .align 5 365ENTRY(cpu_arm1020_switch_mm) 366#ifdef CONFIG_MMU 367#ifndef CONFIG_CPU_DCACHE_DISABLE 368 mcr p15, 0, r3, c7, c10, 4 369 mov r1, #0xF @ 16 segments 3701: mov r3, #0x3F @ 64 entries 3712: mov ip, r3, LSL #26 @ shift up entry 372 orr ip, ip, r1, LSL #5 @ shift in/up index 373 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry 374 mov ip, #0 375 mcr p15, 0, ip, c7, c10, 4 376 subs r3, r3, #1 377 cmp r3, #0 378 bge 2b @ entries 3F to 0 379 subs r1, r1, #1 380 cmp r1, #0 381 bge 1b @ segments 15 to 0 382 383#endif 384 mov r1, #0 385#ifndef CONFIG_CPU_ICACHE_DISABLE 386 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 387#endif 388 mcr p15, 0, r1, c7, c10, 4 @ drain WB 389 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 390 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 391#endif /* CONFIG_MMU */ 392 mov pc, lr 393 394/* 395 * cpu_arm1020_set_pte(ptep, pte) 396 * 397 * Set a PTE and flush it out 398 */ 399 .align 5 400ENTRY(cpu_arm1020_set_pte_ext) 401#ifdef CONFIG_MMU 402 armv3_set_pte_ext 403 mov r0, r0 404#ifndef CONFIG_CPU_DCACHE_DISABLE 405 mcr p15, 0, r0, c7, c10, 4 406 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 407#endif 408 mcr p15, 0, r0, c7, c10, 4 @ drain WB 409#endif /* CONFIG_MMU */ 410 mov pc, lr 411 412 __INIT 413 414 .type __arm1020_setup, #function 415__arm1020_setup: 416 mov r0, #0 417 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 418 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 419#ifdef CONFIG_MMU 420 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 421#endif 422 423 adr r5, arm1020_crval 424 ldmia r5, {r5, r6} 425 mrc p15, 0, r0, c1, c0 @ get control register v4 426 bic r0, r0, r5 427 orr r0, r0, r6 428#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 429 orr r0, r0, #0x4000 @ .R.. .... .... .... 430#endif 431 mov pc, lr 432 .size __arm1020_setup, . - __arm1020_setup 433 434 /* 435 * R 436 * .RVI ZFRS BLDP WCAM 437 * .011 1001 ..11 0101 438 */ 439 .type arm1020_crval, #object 440arm1020_crval: 441 crval clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930 442 443 __INITDATA 444 445/* 446 * Purpose : Function pointers used to access above functions - all calls 447 * come through these 448 */ 449 .type arm1020_processor_functions, #object 450arm1020_processor_functions: 451 .word v4t_early_abort 452 .word pabort_noifar 453 .word cpu_arm1020_proc_init 454 .word cpu_arm1020_proc_fin 455 .word cpu_arm1020_reset 456 .word cpu_arm1020_do_idle 457 .word cpu_arm1020_dcache_clean_area 458 .word cpu_arm1020_switch_mm 459 .word cpu_arm1020_set_pte_ext 460 .size arm1020_processor_functions, . - arm1020_processor_functions 461 462 .section ".rodata" 463 464 .type cpu_arch_name, #object 465cpu_arch_name: 466 .asciz "armv5t" 467 .size cpu_arch_name, . - cpu_arch_name 468 469 .type cpu_elf_name, #object 470cpu_elf_name: 471 .asciz "v5" 472 .size cpu_elf_name, . - cpu_elf_name 473 474 .type cpu_arm1020_name, #object 475cpu_arm1020_name: 476 .ascii "ARM1020" 477#ifndef CONFIG_CPU_ICACHE_DISABLE 478 .ascii "i" 479#endif 480#ifndef CONFIG_CPU_DCACHE_DISABLE 481 .ascii "d" 482#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 483 .ascii "(wt)" 484#else 485 .ascii "(wb)" 486#endif 487#endif 488#ifndef CONFIG_CPU_BPREDICT_DISABLE 489 .ascii "B" 490#endif 491#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 492 .ascii "RR" 493#endif 494 .ascii "\0" 495 .size cpu_arm1020_name, . - cpu_arm1020_name 496 497 .align 498 499 .section ".proc.info.init", #alloc, #execinstr 500 501 .type __arm1020_proc_info,#object 502__arm1020_proc_info: 503 .long 0x4104a200 @ ARM 1020T (Architecture v5T) 504 .long 0xff0ffff0 505 .long PMD_TYPE_SECT | \ 506 PMD_SECT_AP_WRITE | \ 507 PMD_SECT_AP_READ 508 .long PMD_TYPE_SECT | \ 509 PMD_SECT_AP_WRITE | \ 510 PMD_SECT_AP_READ 511 b __arm1020_setup 512 .long cpu_arch_name 513 .long cpu_elf_name 514 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB 515 .long cpu_arm1020_name 516 .long arm1020_processor_functions 517 .long v4wbi_tlb_fns 518 .long v4wb_user_fns 519 .long arm1020_cache_fns 520 .size __arm1020_proc_info, . - __arm1020_proc_info 521