1/* 2 * linux/arch/arm/mm/proc-arm1020.S: MMU functions for ARM1020 3 * 4 * Copyright (C) 2000 ARM Limited 5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 6 * hacked for non-paged-MM by Hyok S. Choi, 2003. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * 22 * 23 * These are the low level assembler for performing cache and TLB 24 * functions on the arm1020. 25 * 26 * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt 27 */ 28#include <linux/linkage.h> 29#include <linux/init.h> 30#include <asm/assembler.h> 31#include <asm/asm-offsets.h> 32#include <asm/hwcap.h> 33#include <asm/pgtable-hwdef.h> 34#include <asm/pgtable.h> 35#include <asm/ptrace.h> 36 37#include "proc-macros.S" 38 39/* 40 * This is the maximum size of an area which will be invalidated 41 * using the single invalidate entry instructions. Anything larger 42 * than this, and we go for the whole cache. 43 * 44 * This value should be chosen such that we choose the cheapest 45 * alternative. 46 */ 47#define MAX_AREA_SIZE 32768 48 49/* 50 * The size of one data cache line. 51 */ 52#define CACHE_DLINESIZE 32 53 54/* 55 * The number of data cache segments. 56 */ 57#define CACHE_DSEGMENTS 16 58 59/* 60 * The number of lines in a cache segment. 61 */ 62#define CACHE_DENTRIES 64 63 64/* 65 * This is the size at which it becomes more efficient to 66 * clean the whole cache, rather than using the individual 67 * cache line maintenance instructions. 68 */ 69#define CACHE_DLIMIT 32768 70 71 .text 72/* 73 * cpu_arm1020_proc_init() 74 */ 75ENTRY(cpu_arm1020_proc_init) 76 mov pc, lr 77 78/* 79 * cpu_arm1020_proc_fin() 80 */ 81ENTRY(cpu_arm1020_proc_fin) 82 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 83 bic r0, r0, #0x1000 @ ...i............ 84 bic r0, r0, #0x000e @ ............wca. 85 mcr p15, 0, r0, c1, c0, 0 @ disable caches 86 mov pc, lr 87 88/* 89 * cpu_arm1020_reset(loc) 90 * 91 * Perform a soft reset of the system. Put the CPU into the 92 * same state as it would be if it had been reset, and branch 93 * to what would be the reset vector. 94 * 95 * loc: location to jump to for soft reset 96 */ 97 .align 5 98 .pushsection .idmap.text, "ax" 99ENTRY(cpu_arm1020_reset) 100 mov ip, #0 101 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 102 mcr p15, 0, ip, c7, c10, 4 @ drain WB 103#ifdef CONFIG_MMU 104 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 105#endif 106 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 107 bic ip, ip, #0x000f @ ............wcam 108 bic ip, ip, #0x1100 @ ...i...s........ 109 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 110 mov pc, r0 111ENDPROC(cpu_arm1020_reset) 112 .popsection 113 114/* 115 * cpu_arm1020_do_idle() 116 */ 117 .align 5 118ENTRY(cpu_arm1020_do_idle) 119 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 120 mov pc, lr 121 122/* ================================= CACHE ================================ */ 123 124 .align 5 125 126/* 127 * flush_icache_all() 128 * 129 * Unconditionally clean and invalidate the entire icache. 130 */ 131ENTRY(arm1020_flush_icache_all) 132#ifndef CONFIG_CPU_ICACHE_DISABLE 133 mov r0, #0 134 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 135#endif 136 mov pc, lr 137ENDPROC(arm1020_flush_icache_all) 138 139/* 140 * flush_user_cache_all() 141 * 142 * Invalidate all cache entries in a particular address 143 * space. 144 */ 145ENTRY(arm1020_flush_user_cache_all) 146 /* FALLTHROUGH */ 147/* 148 * flush_kern_cache_all() 149 * 150 * Clean and invalidate the entire cache. 151 */ 152ENTRY(arm1020_flush_kern_cache_all) 153 mov r2, #VM_EXEC 154 mov ip, #0 155__flush_whole_cache: 156#ifndef CONFIG_CPU_DCACHE_DISABLE 157 mcr p15, 0, ip, c7, c10, 4 @ drain WB 158 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments 1591: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 1602: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 161 mcr p15, 0, ip, c7, c10, 4 @ drain WB 162 subs r3, r3, #1 << 26 163 bcs 2b @ entries 63 to 0 164 subs r1, r1, #1 << 5 165 bcs 1b @ segments 15 to 0 166#endif 167 tst r2, #VM_EXEC 168#ifndef CONFIG_CPU_ICACHE_DISABLE 169 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 170#endif 171 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 172 mov pc, lr 173 174/* 175 * flush_user_cache_range(start, end, flags) 176 * 177 * Invalidate a range of cache entries in the specified 178 * address space. 179 * 180 * - start - start address (inclusive) 181 * - end - end address (exclusive) 182 * - flags - vm_flags for this space 183 */ 184ENTRY(arm1020_flush_user_cache_range) 185 mov ip, #0 186 sub r3, r1, r0 @ calculate total size 187 cmp r3, #CACHE_DLIMIT 188 bhs __flush_whole_cache 189 190#ifndef CONFIG_CPU_DCACHE_DISABLE 191 mcr p15, 0, ip, c7, c10, 4 1921: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 193 mcr p15, 0, ip, c7, c10, 4 @ drain WB 194 add r0, r0, #CACHE_DLINESIZE 195 cmp r0, r1 196 blo 1b 197#endif 198 tst r2, #VM_EXEC 199#ifndef CONFIG_CPU_ICACHE_DISABLE 200 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 201#endif 202 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 203 mov pc, lr 204 205/* 206 * coherent_kern_range(start, end) 207 * 208 * Ensure coherency between the Icache and the Dcache in the 209 * region described by start. If you have non-snooping 210 * Harvard caches, you need to implement this function. 211 * 212 * - start - virtual start address 213 * - end - virtual end address 214 */ 215ENTRY(arm1020_coherent_kern_range) 216 /* FALLTRHOUGH */ 217 218/* 219 * coherent_user_range(start, end) 220 * 221 * Ensure coherency between the Icache and the Dcache in the 222 * region described by start. If you have non-snooping 223 * Harvard caches, you need to implement this function. 224 * 225 * - start - virtual start address 226 * - end - virtual end address 227 */ 228ENTRY(arm1020_coherent_user_range) 229 mov ip, #0 230 bic r0, r0, #CACHE_DLINESIZE - 1 231 mcr p15, 0, ip, c7, c10, 4 2321: 233#ifndef CONFIG_CPU_DCACHE_DISABLE 234 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 235 mcr p15, 0, ip, c7, c10, 4 @ drain WB 236#endif 237#ifndef CONFIG_CPU_ICACHE_DISABLE 238 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 239#endif 240 add r0, r0, #CACHE_DLINESIZE 241 cmp r0, r1 242 blo 1b 243 mcr p15, 0, ip, c7, c10, 4 @ drain WB 244 mov pc, lr 245 246/* 247 * flush_kern_dcache_area(void *addr, size_t size) 248 * 249 * Ensure no D cache aliasing occurs, either with itself or 250 * the I cache 251 * 252 * - addr - kernel address 253 * - size - region size 254 */ 255ENTRY(arm1020_flush_kern_dcache_area) 256 mov ip, #0 257#ifndef CONFIG_CPU_DCACHE_DISABLE 258 add r1, r0, r1 2591: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 260 mcr p15, 0, ip, c7, c10, 4 @ drain WB 261 add r0, r0, #CACHE_DLINESIZE 262 cmp r0, r1 263 blo 1b 264#endif 265 mcr p15, 0, ip, c7, c10, 4 @ drain WB 266 mov pc, lr 267 268/* 269 * dma_inv_range(start, end) 270 * 271 * Invalidate (discard) the specified virtual address range. 272 * May not write back any entries. If 'start' or 'end' 273 * are not cache line aligned, those lines must be written 274 * back. 275 * 276 * - start - virtual start address 277 * - end - virtual end address 278 * 279 * (same as v4wb) 280 */ 281arm1020_dma_inv_range: 282 mov ip, #0 283#ifndef CONFIG_CPU_DCACHE_DISABLE 284 tst r0, #CACHE_DLINESIZE - 1 285 bic r0, r0, #CACHE_DLINESIZE - 1 286 mcrne p15, 0, ip, c7, c10, 4 287 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 288 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 289 tst r1, #CACHE_DLINESIZE - 1 290 mcrne p15, 0, ip, c7, c10, 4 291 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 292 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 2931: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 294 add r0, r0, #CACHE_DLINESIZE 295 cmp r0, r1 296 blo 1b 297#endif 298 mcr p15, 0, ip, c7, c10, 4 @ drain WB 299 mov pc, lr 300 301/* 302 * dma_clean_range(start, end) 303 * 304 * Clean the specified virtual address range. 305 * 306 * - start - virtual start address 307 * - end - virtual end address 308 * 309 * (same as v4wb) 310 */ 311arm1020_dma_clean_range: 312 mov ip, #0 313#ifndef CONFIG_CPU_DCACHE_DISABLE 314 bic r0, r0, #CACHE_DLINESIZE - 1 3151: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 316 mcr p15, 0, ip, c7, c10, 4 @ drain WB 317 add r0, r0, #CACHE_DLINESIZE 318 cmp r0, r1 319 blo 1b 320#endif 321 mcr p15, 0, ip, c7, c10, 4 @ drain WB 322 mov pc, lr 323 324/* 325 * dma_flush_range(start, end) 326 * 327 * Clean and invalidate the specified virtual address range. 328 * 329 * - start - virtual start address 330 * - end - virtual end address 331 */ 332ENTRY(arm1020_dma_flush_range) 333 mov ip, #0 334#ifndef CONFIG_CPU_DCACHE_DISABLE 335 bic r0, r0, #CACHE_DLINESIZE - 1 336 mcr p15, 0, ip, c7, c10, 4 3371: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 338 mcr p15, 0, ip, c7, c10, 4 @ drain WB 339 add r0, r0, #CACHE_DLINESIZE 340 cmp r0, r1 341 blo 1b 342#endif 343 mcr p15, 0, ip, c7, c10, 4 @ drain WB 344 mov pc, lr 345 346/* 347 * dma_map_area(start, size, dir) 348 * - start - kernel virtual start address 349 * - size - size of region 350 * - dir - DMA direction 351 */ 352ENTRY(arm1020_dma_map_area) 353 add r1, r1, r0 354 cmp r2, #DMA_TO_DEVICE 355 beq arm1020_dma_clean_range 356 bcs arm1020_dma_inv_range 357 b arm1020_dma_flush_range 358ENDPROC(arm1020_dma_map_area) 359 360/* 361 * dma_unmap_area(start, size, dir) 362 * - start - kernel virtual start address 363 * - size - size of region 364 * - dir - DMA direction 365 */ 366ENTRY(arm1020_dma_unmap_area) 367 mov pc, lr 368ENDPROC(arm1020_dma_unmap_area) 369 370 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) 371 define_cache_functions arm1020 372 373 .align 5 374ENTRY(cpu_arm1020_dcache_clean_area) 375#ifndef CONFIG_CPU_DCACHE_DISABLE 376 mov ip, #0 3771: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 378 mcr p15, 0, ip, c7, c10, 4 @ drain WB 379 add r0, r0, #CACHE_DLINESIZE 380 subs r1, r1, #CACHE_DLINESIZE 381 bhi 1b 382#endif 383 mov pc, lr 384 385/* =============================== PageTable ============================== */ 386 387/* 388 * cpu_arm1020_switch_mm(pgd) 389 * 390 * Set the translation base pointer to be as described by pgd. 391 * 392 * pgd: new page tables 393 */ 394 .align 5 395ENTRY(cpu_arm1020_switch_mm) 396#ifdef CONFIG_MMU 397#ifndef CONFIG_CPU_DCACHE_DISABLE 398 mcr p15, 0, r3, c7, c10, 4 399 mov r1, #0xF @ 16 segments 4001: mov r3, #0x3F @ 64 entries 4012: mov ip, r3, LSL #26 @ shift up entry 402 orr ip, ip, r1, LSL #5 @ shift in/up index 403 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry 404 mov ip, #0 405 mcr p15, 0, ip, c7, c10, 4 406 subs r3, r3, #1 407 cmp r3, #0 408 bge 2b @ entries 3F to 0 409 subs r1, r1, #1 410 cmp r1, #0 411 bge 1b @ segments 15 to 0 412 413#endif 414 mov r1, #0 415#ifndef CONFIG_CPU_ICACHE_DISABLE 416 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 417#endif 418 mcr p15, 0, r1, c7, c10, 4 @ drain WB 419 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 420 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 421#endif /* CONFIG_MMU */ 422 mov pc, lr 423 424/* 425 * cpu_arm1020_set_pte(ptep, pte) 426 * 427 * Set a PTE and flush it out 428 */ 429 .align 5 430ENTRY(cpu_arm1020_set_pte_ext) 431#ifdef CONFIG_MMU 432 armv3_set_pte_ext 433 mov r0, r0 434#ifndef CONFIG_CPU_DCACHE_DISABLE 435 mcr p15, 0, r0, c7, c10, 4 436 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 437#endif 438 mcr p15, 0, r0, c7, c10, 4 @ drain WB 439#endif /* CONFIG_MMU */ 440 mov pc, lr 441 442 __CPUINIT 443 444 .type __arm1020_setup, #function 445__arm1020_setup: 446 mov r0, #0 447 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 448 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 449#ifdef CONFIG_MMU 450 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 451#endif 452 453 adr r5, arm1020_crval 454 ldmia r5, {r5, r6} 455 mrc p15, 0, r0, c1, c0 @ get control register v4 456 bic r0, r0, r5 457 orr r0, r0, r6 458#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 459 orr r0, r0, #0x4000 @ .R.. .... .... .... 460#endif 461 mov pc, lr 462 .size __arm1020_setup, . - __arm1020_setup 463 464 /* 465 * R 466 * .RVI ZFRS BLDP WCAM 467 * .011 1001 ..11 0101 468 */ 469 .type arm1020_crval, #object 470arm1020_crval: 471 crval clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930 472 473 __INITDATA 474 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) 475 define_processor_functions arm1020, dabort=v4t_early_abort, pabort=legacy_pabort 476 477 478 .section ".rodata" 479 480 string cpu_arch_name, "armv5t" 481 string cpu_elf_name, "v5" 482 483 .type cpu_arm1020_name, #object 484cpu_arm1020_name: 485 .ascii "ARM1020" 486#ifndef CONFIG_CPU_ICACHE_DISABLE 487 .ascii "i" 488#endif 489#ifndef CONFIG_CPU_DCACHE_DISABLE 490 .ascii "d" 491#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 492 .ascii "(wt)" 493#else 494 .ascii "(wb)" 495#endif 496#endif 497#ifndef CONFIG_CPU_BPREDICT_DISABLE 498 .ascii "B" 499#endif 500#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 501 .ascii "RR" 502#endif 503 .ascii "\0" 504 .size cpu_arm1020_name, . - cpu_arm1020_name 505 506 .align 507 508 .section ".proc.info.init", #alloc, #execinstr 509 510 .type __arm1020_proc_info,#object 511__arm1020_proc_info: 512 .long 0x4104a200 @ ARM 1020T (Architecture v5T) 513 .long 0xff0ffff0 514 .long PMD_TYPE_SECT | \ 515 PMD_SECT_AP_WRITE | \ 516 PMD_SECT_AP_READ 517 .long PMD_TYPE_SECT | \ 518 PMD_SECT_AP_WRITE | \ 519 PMD_SECT_AP_READ 520 b __arm1020_setup 521 .long cpu_arch_name 522 .long cpu_elf_name 523 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB 524 .long cpu_arm1020_name 525 .long arm1020_processor_functions 526 .long v4wbi_tlb_fns 527 .long v4wb_user_fns 528 .long arm1020_cache_fns 529 .size __arm1020_proc_info, . - __arm1020_proc_info 530