1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * linux/arch/arm/mm/proc-arm1020.S: MMU functions for ARM1020 4 * 5 * Copyright (C) 2000 ARM Limited 6 * Copyright (C) 2000 Deep Blue Solutions Ltd. 7 * hacked for non-paged-MM by Hyok S. Choi, 2003. 8 * 9 * These are the low level assembler for performing cache and TLB 10 * functions on the arm1020. 11 */ 12#include <linux/linkage.h> 13#include <linux/init.h> 14#include <linux/pgtable.h> 15#include <asm/assembler.h> 16#include <asm/asm-offsets.h> 17#include <asm/hwcap.h> 18#include <asm/pgtable-hwdef.h> 19#include <asm/ptrace.h> 20 21#include "proc-macros.S" 22 23/* 24 * This is the maximum size of an area which will be invalidated 25 * using the single invalidate entry instructions. Anything larger 26 * than this, and we go for the whole cache. 27 * 28 * This value should be chosen such that we choose the cheapest 29 * alternative. 30 */ 31#define MAX_AREA_SIZE 32768 32 33/* 34 * The size of one data cache line. 35 */ 36#define CACHE_DLINESIZE 32 37 38/* 39 * The number of data cache segments. 40 */ 41#define CACHE_DSEGMENTS 16 42 43/* 44 * The number of lines in a cache segment. 45 */ 46#define CACHE_DENTRIES 64 47 48/* 49 * This is the size at which it becomes more efficient to 50 * clean the whole cache, rather than using the individual 51 * cache line maintenance instructions. 52 */ 53#define CACHE_DLIMIT 32768 54 55 .text 56/* 57 * cpu_arm1020_proc_init() 58 */ 59ENTRY(cpu_arm1020_proc_init) 60 ret lr 61 62/* 63 * cpu_arm1020_proc_fin() 64 */ 65ENTRY(cpu_arm1020_proc_fin) 66 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 67 bic r0, r0, #0x1000 @ ...i............ 68 bic r0, r0, #0x000e @ ............wca. 69 mcr p15, 0, r0, c1, c0, 0 @ disable caches 70 ret lr 71 72/* 73 * cpu_arm1020_reset(loc) 74 * 75 * Perform a soft reset of the system. Put the CPU into the 76 * same state as it would be if it had been reset, and branch 77 * to what would be the reset vector. 78 * 79 * loc: location to jump to for soft reset 80 */ 81 .align 5 82 .pushsection .idmap.text, "ax" 83ENTRY(cpu_arm1020_reset) 84 mov ip, #0 85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 86 mcr p15, 0, ip, c7, c10, 4 @ drain WB 87#ifdef CONFIG_MMU 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 89#endif 90 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 91 bic ip, ip, #0x000f @ ............wcam 92 bic ip, ip, #0x1100 @ ...i...s........ 93 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 94 ret r0 95ENDPROC(cpu_arm1020_reset) 96 .popsection 97 98/* 99 * cpu_arm1020_do_idle() 100 */ 101 .align 5 102ENTRY(cpu_arm1020_do_idle) 103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 104 ret lr 105 106/* ================================= CACHE ================================ */ 107 108 .align 5 109 110/* 111 * flush_icache_all() 112 * 113 * Unconditionally clean and invalidate the entire icache. 114 */ 115ENTRY(arm1020_flush_icache_all) 116#ifndef CONFIG_CPU_ICACHE_DISABLE 117 mov r0, #0 118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 119#endif 120 ret lr 121ENDPROC(arm1020_flush_icache_all) 122 123/* 124 * flush_user_cache_all() 125 * 126 * Invalidate all cache entries in a particular address 127 * space. 128 */ 129ENTRY(arm1020_flush_user_cache_all) 130 /* FALLTHROUGH */ 131/* 132 * flush_kern_cache_all() 133 * 134 * Clean and invalidate the entire cache. 135 */ 136ENTRY(arm1020_flush_kern_cache_all) 137 mov r2, #VM_EXEC 138 mov ip, #0 139__flush_whole_cache: 140#ifndef CONFIG_CPU_DCACHE_DISABLE 141 mcr p15, 0, ip, c7, c10, 4 @ drain WB 142 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments 1431: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 1442: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 145 mcr p15, 0, ip, c7, c10, 4 @ drain WB 146 subs r3, r3, #1 << 26 147 bcs 2b @ entries 63 to 0 148 subs r1, r1, #1 << 5 149 bcs 1b @ segments 15 to 0 150#endif 151 tst r2, #VM_EXEC 152#ifndef CONFIG_CPU_ICACHE_DISABLE 153 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 154#endif 155 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 156 ret lr 157 158/* 159 * flush_user_cache_range(start, end, flags) 160 * 161 * Invalidate a range of cache entries in the specified 162 * address space. 163 * 164 * - start - start address (inclusive) 165 * - end - end address (exclusive) 166 * - flags - vm_flags for this space 167 */ 168ENTRY(arm1020_flush_user_cache_range) 169 mov ip, #0 170 sub r3, r1, r0 @ calculate total size 171 cmp r3, #CACHE_DLIMIT 172 bhs __flush_whole_cache 173 174#ifndef CONFIG_CPU_DCACHE_DISABLE 175 mcr p15, 0, ip, c7, c10, 4 1761: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 177 mcr p15, 0, ip, c7, c10, 4 @ drain WB 178 add r0, r0, #CACHE_DLINESIZE 179 cmp r0, r1 180 blo 1b 181#endif 182 tst r2, #VM_EXEC 183#ifndef CONFIG_CPU_ICACHE_DISABLE 184 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 185#endif 186 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 187 ret lr 188 189/* 190 * coherent_kern_range(start, end) 191 * 192 * Ensure coherency between the Icache and the Dcache in the 193 * region described by start. If you have non-snooping 194 * Harvard caches, you need to implement this function. 195 * 196 * - start - virtual start address 197 * - end - virtual end address 198 */ 199ENTRY(arm1020_coherent_kern_range) 200 /* FALLTRHOUGH */ 201 202/* 203 * coherent_user_range(start, end) 204 * 205 * Ensure coherency between the Icache and the Dcache in the 206 * region described by start. If you have non-snooping 207 * Harvard caches, you need to implement this function. 208 * 209 * - start - virtual start address 210 * - end - virtual end address 211 */ 212ENTRY(arm1020_coherent_user_range) 213 mov ip, #0 214 bic r0, r0, #CACHE_DLINESIZE - 1 215 mcr p15, 0, ip, c7, c10, 4 2161: 217#ifndef CONFIG_CPU_DCACHE_DISABLE 218 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 219 mcr p15, 0, ip, c7, c10, 4 @ drain WB 220#endif 221#ifndef CONFIG_CPU_ICACHE_DISABLE 222 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 223#endif 224 add r0, r0, #CACHE_DLINESIZE 225 cmp r0, r1 226 blo 1b 227 mcr p15, 0, ip, c7, c10, 4 @ drain WB 228 mov r0, #0 229 ret lr 230 231/* 232 * flush_kern_dcache_area(void *addr, size_t size) 233 * 234 * Ensure no D cache aliasing occurs, either with itself or 235 * the I cache 236 * 237 * - addr - kernel address 238 * - size - region size 239 */ 240ENTRY(arm1020_flush_kern_dcache_area) 241 mov ip, #0 242#ifndef CONFIG_CPU_DCACHE_DISABLE 243 add r1, r0, r1 2441: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 245 mcr p15, 0, ip, c7, c10, 4 @ drain WB 246 add r0, r0, #CACHE_DLINESIZE 247 cmp r0, r1 248 blo 1b 249#endif 250 mcr p15, 0, ip, c7, c10, 4 @ drain WB 251 ret lr 252 253/* 254 * dma_inv_range(start, end) 255 * 256 * Invalidate (discard) the specified virtual address range. 257 * May not write back any entries. If 'start' or 'end' 258 * are not cache line aligned, those lines must be written 259 * back. 260 * 261 * - start - virtual start address 262 * - end - virtual end address 263 * 264 * (same as v4wb) 265 */ 266arm1020_dma_inv_range: 267 mov ip, #0 268#ifndef CONFIG_CPU_DCACHE_DISABLE 269 tst r0, #CACHE_DLINESIZE - 1 270 bic r0, r0, #CACHE_DLINESIZE - 1 271 mcrne p15, 0, ip, c7, c10, 4 272 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 273 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 274 tst r1, #CACHE_DLINESIZE - 1 275 mcrne p15, 0, ip, c7, c10, 4 276 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 277 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 2781: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 279 add r0, r0, #CACHE_DLINESIZE 280 cmp r0, r1 281 blo 1b 282#endif 283 mcr p15, 0, ip, c7, c10, 4 @ drain WB 284 ret lr 285 286/* 287 * dma_clean_range(start, end) 288 * 289 * Clean the specified virtual address range. 290 * 291 * - start - virtual start address 292 * - end - virtual end address 293 * 294 * (same as v4wb) 295 */ 296arm1020_dma_clean_range: 297 mov ip, #0 298#ifndef CONFIG_CPU_DCACHE_DISABLE 299 bic r0, r0, #CACHE_DLINESIZE - 1 3001: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 301 mcr p15, 0, ip, c7, c10, 4 @ drain WB 302 add r0, r0, #CACHE_DLINESIZE 303 cmp r0, r1 304 blo 1b 305#endif 306 mcr p15, 0, ip, c7, c10, 4 @ drain WB 307 ret lr 308 309/* 310 * dma_flush_range(start, end) 311 * 312 * Clean and invalidate the specified virtual address range. 313 * 314 * - start - virtual start address 315 * - end - virtual end address 316 */ 317ENTRY(arm1020_dma_flush_range) 318 mov ip, #0 319#ifndef CONFIG_CPU_DCACHE_DISABLE 320 bic r0, r0, #CACHE_DLINESIZE - 1 321 mcr p15, 0, ip, c7, c10, 4 3221: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 323 mcr p15, 0, ip, c7, c10, 4 @ drain WB 324 add r0, r0, #CACHE_DLINESIZE 325 cmp r0, r1 326 blo 1b 327#endif 328 mcr p15, 0, ip, c7, c10, 4 @ drain WB 329 ret lr 330 331/* 332 * dma_map_area(start, size, dir) 333 * - start - kernel virtual start address 334 * - size - size of region 335 * - dir - DMA direction 336 */ 337ENTRY(arm1020_dma_map_area) 338 add r1, r1, r0 339 cmp r2, #DMA_TO_DEVICE 340 beq arm1020_dma_clean_range 341 bcs arm1020_dma_inv_range 342 b arm1020_dma_flush_range 343ENDPROC(arm1020_dma_map_area) 344 345/* 346 * dma_unmap_area(start, size, dir) 347 * - start - kernel virtual start address 348 * - size - size of region 349 * - dir - DMA direction 350 */ 351ENTRY(arm1020_dma_unmap_area) 352 ret lr 353ENDPROC(arm1020_dma_unmap_area) 354 355 .globl arm1020_flush_kern_cache_louis 356 .equ arm1020_flush_kern_cache_louis, arm1020_flush_kern_cache_all 357 358 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) 359 define_cache_functions arm1020 360 361 .align 5 362ENTRY(cpu_arm1020_dcache_clean_area) 363#ifndef CONFIG_CPU_DCACHE_DISABLE 364 mov ip, #0 3651: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 366 mcr p15, 0, ip, c7, c10, 4 @ drain WB 367 add r0, r0, #CACHE_DLINESIZE 368 subs r1, r1, #CACHE_DLINESIZE 369 bhi 1b 370#endif 371 ret lr 372 373/* =============================== PageTable ============================== */ 374 375/* 376 * cpu_arm1020_switch_mm(pgd) 377 * 378 * Set the translation base pointer to be as described by pgd. 379 * 380 * pgd: new page tables 381 */ 382 .align 5 383ENTRY(cpu_arm1020_switch_mm) 384#ifdef CONFIG_MMU 385#ifndef CONFIG_CPU_DCACHE_DISABLE 386 mcr p15, 0, r3, c7, c10, 4 387 mov r1, #0xF @ 16 segments 3881: mov r3, #0x3F @ 64 entries 3892: mov ip, r3, LSL #26 @ shift up entry 390 orr ip, ip, r1, LSL #5 @ shift in/up index 391 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry 392 mov ip, #0 393 mcr p15, 0, ip, c7, c10, 4 394 subs r3, r3, #1 395 cmp r3, #0 396 bge 2b @ entries 3F to 0 397 subs r1, r1, #1 398 cmp r1, #0 399 bge 1b @ segments 15 to 0 400 401#endif 402 mov r1, #0 403#ifndef CONFIG_CPU_ICACHE_DISABLE 404 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 405#endif 406 mcr p15, 0, r1, c7, c10, 4 @ drain WB 407 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 408 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 409#endif /* CONFIG_MMU */ 410 ret lr 411 412/* 413 * cpu_arm1020_set_pte(ptep, pte) 414 * 415 * Set a PTE and flush it out 416 */ 417 .align 5 418ENTRY(cpu_arm1020_set_pte_ext) 419#ifdef CONFIG_MMU 420 armv3_set_pte_ext 421 mov r0, r0 422#ifndef CONFIG_CPU_DCACHE_DISABLE 423 mcr p15, 0, r0, c7, c10, 4 424 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 425#endif 426 mcr p15, 0, r0, c7, c10, 4 @ drain WB 427#endif /* CONFIG_MMU */ 428 ret lr 429 430 .type __arm1020_setup, #function 431__arm1020_setup: 432 mov r0, #0 433 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 434 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 435#ifdef CONFIG_MMU 436 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 437#endif 438 439 adr r5, arm1020_crval 440 ldmia r5, {r5, r6} 441 mrc p15, 0, r0, c1, c0 @ get control register v4 442 bic r0, r0, r5 443 orr r0, r0, r6 444#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 445 orr r0, r0, #0x4000 @ .R.. .... .... .... 446#endif 447 ret lr 448 .size __arm1020_setup, . - __arm1020_setup 449 450 /* 451 * R 452 * .RVI ZFRS BLDP WCAM 453 * .011 1001 ..11 0101 454 */ 455 .type arm1020_crval, #object 456arm1020_crval: 457 crval clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930 458 459 __INITDATA 460 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) 461 define_processor_functions arm1020, dabort=v4t_early_abort, pabort=legacy_pabort 462 463 464 .section ".rodata" 465 466 string cpu_arch_name, "armv5t" 467 string cpu_elf_name, "v5" 468 469 .type cpu_arm1020_name, #object 470cpu_arm1020_name: 471 .ascii "ARM1020" 472#ifndef CONFIG_CPU_ICACHE_DISABLE 473 .ascii "i" 474#endif 475#ifndef CONFIG_CPU_DCACHE_DISABLE 476 .ascii "d" 477#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 478 .ascii "(wt)" 479#else 480 .ascii "(wb)" 481#endif 482#endif 483#ifndef CONFIG_CPU_BPREDICT_DISABLE 484 .ascii "B" 485#endif 486#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 487 .ascii "RR" 488#endif 489 .ascii "\0" 490 .size cpu_arm1020_name, . - cpu_arm1020_name 491 492 .align 493 494 .section ".proc.info.init", "a" 495 496 .type __arm1020_proc_info,#object 497__arm1020_proc_info: 498 .long 0x4104a200 @ ARM 1020T (Architecture v5T) 499 .long 0xff0ffff0 500 .long PMD_TYPE_SECT | \ 501 PMD_SECT_AP_WRITE | \ 502 PMD_SECT_AP_READ 503 .long PMD_TYPE_SECT | \ 504 PMD_SECT_AP_WRITE | \ 505 PMD_SECT_AP_READ 506 initfn __arm1020_setup, __arm1020_proc_info 507 .long cpu_arch_name 508 .long cpu_elf_name 509 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB 510 .long cpu_arm1020_name 511 .long arm1020_processor_functions 512 .long v4wbi_tlb_fns 513 .long v4wb_user_fns 514 .long arm1020_cache_fns 515 .size __arm1020_proc_info, . - __arm1020_proc_info 516