1 /* 2 * linux/arch/arm/mm/nommu.c 3 * 4 * ARM uCLinux supporting functions. 5 */ 6 #include <linux/module.h> 7 #include <linux/mm.h> 8 #include <linux/pagemap.h> 9 #include <linux/io.h> 10 #include <linux/memblock.h> 11 #include <linux/kernel.h> 12 13 #include <asm/cacheflush.h> 14 #include <asm/cp15.h> 15 #include <asm/sections.h> 16 #include <asm/page.h> 17 #include <asm/setup.h> 18 #include <asm/traps.h> 19 #include <asm/mach/arch.h> 20 #include <asm/cputype.h> 21 #include <asm/mpu.h> 22 #include <asm/procinfo.h> 23 24 #include "mm.h" 25 26 unsigned long vectors_base; 27 28 #ifdef CONFIG_ARM_MPU 29 struct mpu_rgn_info mpu_rgn_info; 30 #endif 31 32 #ifdef CONFIG_CPU_CP15 33 #ifdef CONFIG_CPU_HIGH_VECTOR 34 unsigned long setup_vectors_base(void) 35 { 36 unsigned long reg = get_cr(); 37 38 set_cr(reg | CR_V); 39 return 0xffff0000; 40 } 41 #else /* CONFIG_CPU_HIGH_VECTOR */ 42 /* Write exception base address to VBAR */ 43 static inline void set_vbar(unsigned long val) 44 { 45 asm("mcr p15, 0, %0, c12, c0, 0" : : "r" (val) : "cc"); 46 } 47 48 /* 49 * Security extensions, bits[7:4], permitted values, 50 * 0b0000 - not implemented, 0b0001/0b0010 - implemented 51 */ 52 static inline bool security_extensions_enabled(void) 53 { 54 /* Check CPUID Identification Scheme before ID_PFR1 read */ 55 if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) 56 return cpuid_feature_extract(CPUID_EXT_PFR1, 4) || 57 cpuid_feature_extract(CPUID_EXT_PFR1, 20); 58 return 0; 59 } 60 61 unsigned long setup_vectors_base(void) 62 { 63 unsigned long base = 0, reg = get_cr(); 64 65 set_cr(reg & ~CR_V); 66 if (security_extensions_enabled()) { 67 if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM)) 68 base = CONFIG_DRAM_BASE; 69 set_vbar(base); 70 } else if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM)) { 71 if (CONFIG_DRAM_BASE != 0) 72 pr_err("Security extensions not enabled, vectors cannot be remapped to RAM, vectors base will be 0x00000000\n"); 73 } 74 75 return base; 76 } 77 #endif /* CONFIG_CPU_HIGH_VECTOR */ 78 #endif /* CONFIG_CPU_CP15 */ 79 80 void __init arm_mm_memblock_reserve(void) 81 { 82 #ifndef CONFIG_CPU_V7M 83 vectors_base = IS_ENABLED(CONFIG_CPU_CP15) ? setup_vectors_base() : 0; 84 /* 85 * Register the exception vector page. 86 * some architectures which the DRAM is the exception vector to trap, 87 * alloc_page breaks with error, although it is not NULL, but "0." 88 */ 89 memblock_reserve(vectors_base, 2 * PAGE_SIZE); 90 #else /* ifndef CONFIG_CPU_V7M */ 91 /* 92 * There is no dedicated vector page on V7-M. So nothing needs to be 93 * reserved here. 94 */ 95 #endif 96 /* 97 * In any case, always ensure address 0 is never used as many things 98 * get very confused if 0 is returned as a legitimate address. 99 */ 100 memblock_reserve(0, 1); 101 } 102 103 static void __init adjust_lowmem_bounds_mpu(void) 104 { 105 unsigned long pmsa = read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA; 106 107 switch (pmsa) { 108 case MMFR0_PMSAv7: 109 pmsav7_adjust_lowmem_bounds(); 110 break; 111 case MMFR0_PMSAv8: 112 pmsav8_adjust_lowmem_bounds(); 113 break; 114 default: 115 break; 116 } 117 } 118 119 static void __init mpu_setup(void) 120 { 121 unsigned long pmsa = read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA; 122 123 switch (pmsa) { 124 case MMFR0_PMSAv7: 125 pmsav7_setup(); 126 break; 127 case MMFR0_PMSAv8: 128 pmsav8_setup(); 129 break; 130 default: 131 break; 132 } 133 } 134 135 void __init adjust_lowmem_bounds(void) 136 { 137 phys_addr_t end; 138 adjust_lowmem_bounds_mpu(); 139 end = memblock_end_of_DRAM(); 140 high_memory = __va(end - 1) + 1; 141 memblock_set_current_limit(end); 142 } 143 144 /* 145 * paging_init() sets up the page tables, initialises the zone memory 146 * maps, and sets up the zero page, bad page and bad page tables. 147 */ 148 void __init paging_init(const struct machine_desc *mdesc) 149 { 150 early_trap_init((void *)vectors_base); 151 mpu_setup(); 152 bootmem_init(); 153 } 154 155 /* 156 * We don't need to do anything here for nommu machines. 157 */ 158 void setup_mm_for_reboot(void) 159 { 160 } 161 162 void flush_dcache_page(struct page *page) 163 { 164 __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE); 165 } 166 EXPORT_SYMBOL(flush_dcache_page); 167 168 void flush_kernel_dcache_page(struct page *page) 169 { 170 __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE); 171 } 172 EXPORT_SYMBOL(flush_kernel_dcache_page); 173 174 void copy_to_user_page(struct vm_area_struct *vma, struct page *page, 175 unsigned long uaddr, void *dst, const void *src, 176 unsigned long len) 177 { 178 memcpy(dst, src, len); 179 if (vma->vm_flags & VM_EXEC) 180 __cpuc_coherent_user_range(uaddr, uaddr + len); 181 } 182 183 void __iomem *__arm_ioremap_pfn(unsigned long pfn, unsigned long offset, 184 size_t size, unsigned int mtype) 185 { 186 if (pfn >= (0x100000000ULL >> PAGE_SHIFT)) 187 return NULL; 188 return (void __iomem *) (offset + (pfn << PAGE_SHIFT)); 189 } 190 EXPORT_SYMBOL(__arm_ioremap_pfn); 191 192 void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size, 193 unsigned int mtype, void *caller) 194 { 195 return (void __iomem *)phys_addr; 196 } 197 198 void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, unsigned int, void *); 199 200 void __iomem *ioremap(resource_size_t res_cookie, size_t size) 201 { 202 return __arm_ioremap_caller(res_cookie, size, MT_DEVICE, 203 __builtin_return_address(0)); 204 } 205 EXPORT_SYMBOL(ioremap); 206 207 void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size) 208 __alias(ioremap_cached); 209 210 void __iomem *ioremap_cached(resource_size_t res_cookie, size_t size) 211 { 212 return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_CACHED, 213 __builtin_return_address(0)); 214 } 215 EXPORT_SYMBOL(ioremap_cache); 216 EXPORT_SYMBOL(ioremap_cached); 217 218 void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size) 219 { 220 return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_WC, 221 __builtin_return_address(0)); 222 } 223 EXPORT_SYMBOL(ioremap_wc); 224 225 #ifdef CONFIG_PCI 226 227 #include <asm/mach/map.h> 228 229 void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size) 230 { 231 return arch_ioremap_caller(res_cookie, size, MT_UNCACHED, 232 __builtin_return_address(0)); 233 } 234 EXPORT_SYMBOL_GPL(pci_remap_cfgspace); 235 #endif 236 237 void *arch_memremap_wb(phys_addr_t phys_addr, size_t size) 238 { 239 return (void *)phys_addr; 240 } 241 242 void __iounmap(volatile void __iomem *addr) 243 { 244 } 245 EXPORT_SYMBOL(__iounmap); 246 247 void (*arch_iounmap)(volatile void __iomem *); 248 249 void iounmap(volatile void __iomem *addr) 250 { 251 } 252 EXPORT_SYMBOL(iounmap); 253