1 /* 2 * linux/arch/arm/mm/nommu.c 3 * 4 * ARM uCLinux supporting functions. 5 */ 6 #include <linux/module.h> 7 #include <linux/mm.h> 8 #include <linux/pagemap.h> 9 #include <linux/io.h> 10 #include <linux/memblock.h> 11 #include <linux/kernel.h> 12 13 #include <asm/cacheflush.h> 14 #include <asm/cp15.h> 15 #include <asm/sections.h> 16 #include <asm/page.h> 17 #include <asm/setup.h> 18 #include <asm/traps.h> 19 #include <asm/mach/arch.h> 20 #include <asm/cputype.h> 21 #include <asm/mpu.h> 22 #include <asm/procinfo.h> 23 24 #include "mm.h" 25 26 unsigned long vectors_base; 27 28 #ifdef CONFIG_ARM_MPU 29 struct mpu_rgn_info mpu_rgn_info; 30 31 /* Region number */ 32 static void rgnr_write(u32 v) 33 { 34 asm("mcr p15, 0, %0, c6, c2, 0" : : "r" (v)); 35 } 36 37 /* Data-side / unified region attributes */ 38 39 /* Region access control register */ 40 static void dracr_write(u32 v) 41 { 42 asm("mcr p15, 0, %0, c6, c1, 4" : : "r" (v)); 43 } 44 45 /* Region size register */ 46 static void drsr_write(u32 v) 47 { 48 asm("mcr p15, 0, %0, c6, c1, 2" : : "r" (v)); 49 } 50 51 /* Region base address register */ 52 static void drbar_write(u32 v) 53 { 54 asm("mcr p15, 0, %0, c6, c1, 0" : : "r" (v)); 55 } 56 57 static u32 drbar_read(void) 58 { 59 u32 v; 60 asm("mrc p15, 0, %0, c6, c1, 0" : "=r" (v)); 61 return v; 62 } 63 /* Optional instruction-side region attributes */ 64 65 /* I-side Region access control register */ 66 static void iracr_write(u32 v) 67 { 68 asm("mcr p15, 0, %0, c6, c1, 5" : : "r" (v)); 69 } 70 71 /* I-side Region size register */ 72 static void irsr_write(u32 v) 73 { 74 asm("mcr p15, 0, %0, c6, c1, 3" : : "r" (v)); 75 } 76 77 /* I-side Region base address register */ 78 static void irbar_write(u32 v) 79 { 80 asm("mcr p15, 0, %0, c6, c1, 1" : : "r" (v)); 81 } 82 83 static unsigned long irbar_read(void) 84 { 85 unsigned long v; 86 asm("mrc p15, 0, %0, c6, c1, 1" : "=r" (v)); 87 return v; 88 } 89 90 /* MPU initialisation functions */ 91 void __init adjust_lowmem_bounds_mpu(void) 92 { 93 phys_addr_t phys_offset = PHYS_OFFSET; 94 phys_addr_t aligned_region_size, specified_mem_size, rounded_mem_size; 95 struct memblock_region *reg; 96 bool first = true; 97 phys_addr_t mem_start; 98 phys_addr_t mem_end; 99 100 for_each_memblock(memory, reg) { 101 if (first) { 102 /* 103 * Initially only use memory continuous from 104 * PHYS_OFFSET */ 105 if (reg->base != phys_offset) 106 panic("First memory bank must be contiguous from PHYS_OFFSET"); 107 108 mem_start = reg->base; 109 mem_end = reg->base + reg->size; 110 specified_mem_size = reg->size; 111 first = false; 112 } else { 113 /* 114 * memblock auto merges contiguous blocks, remove 115 * all blocks afterwards in one go (we can't remove 116 * blocks separately while iterating) 117 */ 118 pr_notice("Ignoring RAM after %pa, memory at %pa ignored\n", 119 &mem_end, ®->base); 120 memblock_remove(reg->base, 0 - reg->base); 121 break; 122 } 123 } 124 125 /* 126 * MPU has curious alignment requirements: Size must be power of 2, and 127 * region start must be aligned to the region size 128 */ 129 if (phys_offset != 0) 130 pr_info("PHYS_OFFSET != 0 => MPU Region size constrained by alignment requirements\n"); 131 132 /* 133 * Maximum aligned region might overflow phys_addr_t if phys_offset is 134 * 0. Hence we keep everything below 4G until we take the smaller of 135 * the aligned_region_size and rounded_mem_size, one of which is 136 * guaranteed to be smaller than the maximum physical address. 137 */ 138 aligned_region_size = (phys_offset - 1) ^ (phys_offset); 139 /* Find the max power-of-two sized region that fits inside our bank */ 140 rounded_mem_size = (1 << __fls(specified_mem_size)) - 1; 141 142 /* The actual region size is the smaller of the two */ 143 aligned_region_size = aligned_region_size < rounded_mem_size 144 ? aligned_region_size + 1 145 : rounded_mem_size + 1; 146 147 if (aligned_region_size != specified_mem_size) { 148 pr_warn("Truncating memory from %pa to %pa (MPU region constraints)", 149 &specified_mem_size, &aligned_region_size); 150 memblock_remove(mem_start + aligned_region_size, 151 specified_mem_size - aligned_region_size); 152 153 mem_end = mem_start + aligned_region_size; 154 } 155 156 pr_debug("MPU Region from %pa size %pa (end %pa))\n", 157 &phys_offset, &aligned_region_size, &mem_end); 158 159 } 160 161 static int mpu_present(void) 162 { 163 return ((read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA) == MMFR0_PMSAv7); 164 } 165 166 static int mpu_max_regions(void) 167 { 168 /* 169 * We don't support a different number of I/D side regions so if we 170 * have separate instruction and data memory maps then return 171 * whichever side has a smaller number of supported regions. 172 */ 173 u32 dregions, iregions, mpuir; 174 mpuir = read_cpuid(CPUID_MPUIR); 175 176 dregions = iregions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION; 177 178 /* Check for separate d-side and i-side memory maps */ 179 if (mpuir & MPUIR_nU) 180 iregions = (mpuir & MPUIR_IREGION_SZMASK) >> MPUIR_IREGION; 181 182 /* Use the smallest of the two maxima */ 183 return min(dregions, iregions); 184 } 185 186 static int mpu_iside_independent(void) 187 { 188 /* MPUIR.nU specifies whether there is *not* a unified memory map */ 189 return read_cpuid(CPUID_MPUIR) & MPUIR_nU; 190 } 191 192 static int mpu_min_region_order(void) 193 { 194 u32 drbar_result, irbar_result; 195 /* We've kept a region free for this probing */ 196 rgnr_write(MPU_PROBE_REGION); 197 isb(); 198 /* 199 * As per ARM ARM, write 0xFFFFFFFC to DRBAR to find the minimum 200 * region order 201 */ 202 drbar_write(0xFFFFFFFC); 203 drbar_result = irbar_result = drbar_read(); 204 drbar_write(0x0); 205 /* If the MPU is non-unified, we use the larger of the two minima*/ 206 if (mpu_iside_independent()) { 207 irbar_write(0xFFFFFFFC); 208 irbar_result = irbar_read(); 209 irbar_write(0x0); 210 } 211 isb(); /* Ensure that MPU region operations have completed */ 212 /* Return whichever result is larger */ 213 return __ffs(max(drbar_result, irbar_result)); 214 } 215 216 static int mpu_setup_region(unsigned int number, phys_addr_t start, 217 unsigned int size_order, unsigned int properties) 218 { 219 u32 size_data; 220 221 /* We kept a region free for probing resolution of MPU regions*/ 222 if (number > mpu_max_regions() || number == MPU_PROBE_REGION) 223 return -ENOENT; 224 225 if (size_order > 32) 226 return -ENOMEM; 227 228 if (size_order < mpu_min_region_order()) 229 return -ENOMEM; 230 231 /* Writing N to bits 5:1 (RSR_SZ) specifies region size 2^N+1 */ 232 size_data = ((size_order - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN; 233 234 dsb(); /* Ensure all previous data accesses occur with old mappings */ 235 rgnr_write(number); 236 isb(); 237 drbar_write(start); 238 dracr_write(properties); 239 isb(); /* Propagate properties before enabling region */ 240 drsr_write(size_data); 241 242 /* Check for independent I-side registers */ 243 if (mpu_iside_independent()) { 244 irbar_write(start); 245 iracr_write(properties); 246 isb(); 247 irsr_write(size_data); 248 } 249 isb(); 250 251 /* Store region info (we treat i/d side the same, so only store d) */ 252 mpu_rgn_info.rgns[number].dracr = properties; 253 mpu_rgn_info.rgns[number].drbar = start; 254 mpu_rgn_info.rgns[number].drsr = size_data; 255 return 0; 256 } 257 258 /* 259 * Set up default MPU regions, doing nothing if there is no MPU 260 */ 261 void __init mpu_setup(void) 262 { 263 int region_err; 264 if (!mpu_present()) 265 return; 266 267 region_err = mpu_setup_region(MPU_RAM_REGION, PHYS_OFFSET, 268 ilog2(memblock.memory.regions[0].size), 269 MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL); 270 if (region_err) { 271 panic("MPU region initialization failure! %d", region_err); 272 } else { 273 pr_info("Using ARMv7 PMSA Compliant MPU. " 274 "Region independence: %s, Max regions: %d\n", 275 mpu_iside_independent() ? "Yes" : "No", 276 mpu_max_regions()); 277 } 278 } 279 #else 280 static void adjust_lowmem_bounds_mpu(void) {} 281 static void __init mpu_setup(void) {} 282 #endif /* CONFIG_ARM_MPU */ 283 284 #ifdef CONFIG_CPU_CP15 285 #ifdef CONFIG_CPU_HIGH_VECTOR 286 static unsigned long __init setup_vectors_base(void) 287 { 288 unsigned long reg = get_cr(); 289 290 set_cr(reg | CR_V); 291 return 0xffff0000; 292 } 293 #else /* CONFIG_CPU_HIGH_VECTOR */ 294 /* Write exception base address to VBAR */ 295 static inline void set_vbar(unsigned long val) 296 { 297 asm("mcr p15, 0, %0, c12, c0, 0" : : "r" (val) : "cc"); 298 } 299 300 /* 301 * Security extensions, bits[7:4], permitted values, 302 * 0b0000 - not implemented, 0b0001/0b0010 - implemented 303 */ 304 static inline bool security_extensions_enabled(void) 305 { 306 /* Check CPUID Identification Scheme before ID_PFR1 read */ 307 if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) 308 return !!cpuid_feature_extract(CPUID_EXT_PFR1, 4); 309 return 0; 310 } 311 312 static unsigned long __init setup_vectors_base(void) 313 { 314 unsigned long base = 0, reg = get_cr(); 315 316 set_cr(reg & ~CR_V); 317 if (security_extensions_enabled()) { 318 if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM)) 319 base = CONFIG_DRAM_BASE; 320 set_vbar(base); 321 } else if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM)) { 322 if (CONFIG_DRAM_BASE != 0) 323 pr_err("Security extensions not enabled, vectors cannot be remapped to RAM, vectors base will be 0x00000000\n"); 324 } 325 326 return base; 327 } 328 #endif /* CONFIG_CPU_HIGH_VECTOR */ 329 #endif /* CONFIG_CPU_CP15 */ 330 331 void __init arm_mm_memblock_reserve(void) 332 { 333 #ifndef CONFIG_CPU_V7M 334 vectors_base = IS_ENABLED(CONFIG_CPU_CP15) ? setup_vectors_base() : 0; 335 /* 336 * Register the exception vector page. 337 * some architectures which the DRAM is the exception vector to trap, 338 * alloc_page breaks with error, although it is not NULL, but "0." 339 */ 340 memblock_reserve(vectors_base, 2 * PAGE_SIZE); 341 #else /* ifndef CONFIG_CPU_V7M */ 342 /* 343 * There is no dedicated vector page on V7-M. So nothing needs to be 344 * reserved here. 345 */ 346 #endif 347 } 348 349 void __init adjust_lowmem_bounds(void) 350 { 351 phys_addr_t end; 352 adjust_lowmem_bounds_mpu(); 353 end = memblock_end_of_DRAM(); 354 high_memory = __va(end - 1) + 1; 355 memblock_set_current_limit(end); 356 } 357 358 /* 359 * paging_init() sets up the page tables, initialises the zone memory 360 * maps, and sets up the zero page, bad page and bad page tables. 361 */ 362 void __init paging_init(const struct machine_desc *mdesc) 363 { 364 early_trap_init((void *)vectors_base); 365 mpu_setup(); 366 bootmem_init(); 367 } 368 369 /* 370 * We don't need to do anything here for nommu machines. 371 */ 372 void setup_mm_for_reboot(void) 373 { 374 } 375 376 void flush_dcache_page(struct page *page) 377 { 378 __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE); 379 } 380 EXPORT_SYMBOL(flush_dcache_page); 381 382 void flush_kernel_dcache_page(struct page *page) 383 { 384 __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE); 385 } 386 EXPORT_SYMBOL(flush_kernel_dcache_page); 387 388 void copy_to_user_page(struct vm_area_struct *vma, struct page *page, 389 unsigned long uaddr, void *dst, const void *src, 390 unsigned long len) 391 { 392 memcpy(dst, src, len); 393 if (vma->vm_flags & VM_EXEC) 394 __cpuc_coherent_user_range(uaddr, uaddr + len); 395 } 396 397 void __iomem *__arm_ioremap_pfn(unsigned long pfn, unsigned long offset, 398 size_t size, unsigned int mtype) 399 { 400 if (pfn >= (0x100000000ULL >> PAGE_SHIFT)) 401 return NULL; 402 return (void __iomem *) (offset + (pfn << PAGE_SHIFT)); 403 } 404 EXPORT_SYMBOL(__arm_ioremap_pfn); 405 406 void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size, 407 unsigned int mtype, void *caller) 408 { 409 return (void __iomem *)phys_addr; 410 } 411 412 void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, unsigned int, void *); 413 414 void __iomem *ioremap(resource_size_t res_cookie, size_t size) 415 { 416 return __arm_ioremap_caller(res_cookie, size, MT_DEVICE, 417 __builtin_return_address(0)); 418 } 419 EXPORT_SYMBOL(ioremap); 420 421 void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size) 422 __alias(ioremap_cached); 423 424 void __iomem *ioremap_cached(resource_size_t res_cookie, size_t size) 425 { 426 return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_CACHED, 427 __builtin_return_address(0)); 428 } 429 EXPORT_SYMBOL(ioremap_cache); 430 EXPORT_SYMBOL(ioremap_cached); 431 432 void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size) 433 { 434 return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_WC, 435 __builtin_return_address(0)); 436 } 437 EXPORT_SYMBOL(ioremap_wc); 438 439 #ifdef CONFIG_PCI 440 441 #include <asm/mach/map.h> 442 443 void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size) 444 { 445 return arch_ioremap_caller(res_cookie, size, MT_UNCACHED, 446 __builtin_return_address(0)); 447 } 448 EXPORT_SYMBOL_GPL(pci_remap_cfgspace); 449 #endif 450 451 void *arch_memremap_wb(phys_addr_t phys_addr, size_t size) 452 { 453 return (void *)phys_addr; 454 } 455 456 void __iounmap(volatile void __iomem *addr) 457 { 458 } 459 EXPORT_SYMBOL(__iounmap); 460 461 void (*arch_iounmap)(volatile void __iomem *); 462 463 void iounmap(volatile void __iomem *addr) 464 { 465 } 466 EXPORT_SYMBOL(iounmap); 467