1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/arch/arm/mm/mmu.c 4 * 5 * Copyright (C) 1995-2005 Russell King 6 */ 7 #include <linux/module.h> 8 #include <linux/kernel.h> 9 #include <linux/errno.h> 10 #include <linux/init.h> 11 #include <linux/mman.h> 12 #include <linux/nodemask.h> 13 #include <linux/memblock.h> 14 #include <linux/fs.h> 15 #include <linux/vmalloc.h> 16 #include <linux/sizes.h> 17 18 #include <asm/cp15.h> 19 #include <asm/cputype.h> 20 #include <asm/cachetype.h> 21 #include <asm/fixmap.h> 22 #include <asm/sections.h> 23 #include <asm/setup.h> 24 #include <asm/smp_plat.h> 25 #include <asm/tlb.h> 26 #include <asm/highmem.h> 27 #include <asm/system_info.h> 28 #include <asm/traps.h> 29 #include <asm/procinfo.h> 30 #include <asm/memory.h> 31 #include <asm/pgalloc.h> 32 #include <asm/kasan_def.h> 33 34 #include <asm/mach/arch.h> 35 #include <asm/mach/map.h> 36 #include <asm/mach/pci.h> 37 #include <asm/fixmap.h> 38 39 #include "fault.h" 40 #include "mm.h" 41 #include "tcm.h" 42 43 extern unsigned long __atags_pointer; 44 45 /* 46 * empty_zero_page is a special page that is used for 47 * zero-initialized data and COW. 48 */ 49 struct page *empty_zero_page; 50 EXPORT_SYMBOL(empty_zero_page); 51 52 /* 53 * The pmd table for the upper-most set of pages. 54 */ 55 pmd_t *top_pmd; 56 57 pmdval_t user_pmd_table = _PAGE_USER_TABLE; 58 59 #define CPOLICY_UNCACHED 0 60 #define CPOLICY_BUFFERED 1 61 #define CPOLICY_WRITETHROUGH 2 62 #define CPOLICY_WRITEBACK 3 63 #define CPOLICY_WRITEALLOC 4 64 65 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; 66 static unsigned int ecc_mask __initdata = 0; 67 pgprot_t pgprot_user; 68 pgprot_t pgprot_kernel; 69 70 EXPORT_SYMBOL(pgprot_user); 71 EXPORT_SYMBOL(pgprot_kernel); 72 73 struct cachepolicy { 74 const char policy[16]; 75 unsigned int cr_mask; 76 pmdval_t pmd; 77 pteval_t pte; 78 }; 79 80 static struct cachepolicy cache_policies[] __initdata = { 81 { 82 .policy = "uncached", 83 .cr_mask = CR_W|CR_C, 84 .pmd = PMD_SECT_UNCACHED, 85 .pte = L_PTE_MT_UNCACHED, 86 }, { 87 .policy = "buffered", 88 .cr_mask = CR_C, 89 .pmd = PMD_SECT_BUFFERED, 90 .pte = L_PTE_MT_BUFFERABLE, 91 }, { 92 .policy = "writethrough", 93 .cr_mask = 0, 94 .pmd = PMD_SECT_WT, 95 .pte = L_PTE_MT_WRITETHROUGH, 96 }, { 97 .policy = "writeback", 98 .cr_mask = 0, 99 .pmd = PMD_SECT_WB, 100 .pte = L_PTE_MT_WRITEBACK, 101 }, { 102 .policy = "writealloc", 103 .cr_mask = 0, 104 .pmd = PMD_SECT_WBWA, 105 .pte = L_PTE_MT_WRITEALLOC, 106 } 107 }; 108 109 #ifdef CONFIG_CPU_CP15 110 static unsigned long initial_pmd_value __initdata = 0; 111 112 /* 113 * Initialise the cache_policy variable with the initial state specified 114 * via the "pmd" value. This is used to ensure that on ARMv6 and later, 115 * the C code sets the page tables up with the same policy as the head 116 * assembly code, which avoids an illegal state where the TLBs can get 117 * confused. See comments in early_cachepolicy() for more information. 118 */ 119 void __init init_default_cache_policy(unsigned long pmd) 120 { 121 int i; 122 123 initial_pmd_value = pmd; 124 125 pmd &= PMD_SECT_CACHE_MASK; 126 127 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) 128 if (cache_policies[i].pmd == pmd) { 129 cachepolicy = i; 130 break; 131 } 132 133 if (i == ARRAY_SIZE(cache_policies)) 134 pr_err("ERROR: could not find cache policy\n"); 135 } 136 137 /* 138 * These are useful for identifying cache coherency problems by allowing 139 * the cache or the cache and writebuffer to be turned off. (Note: the 140 * write buffer should not be on and the cache off). 141 */ 142 static int __init early_cachepolicy(char *p) 143 { 144 int i, selected = -1; 145 146 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { 147 int len = strlen(cache_policies[i].policy); 148 149 if (memcmp(p, cache_policies[i].policy, len) == 0) { 150 selected = i; 151 break; 152 } 153 } 154 155 if (selected == -1) 156 pr_err("ERROR: unknown or unsupported cache policy\n"); 157 158 /* 159 * This restriction is partly to do with the way we boot; it is 160 * unpredictable to have memory mapped using two different sets of 161 * memory attributes (shared, type, and cache attribs). We can not 162 * change these attributes once the initial assembly has setup the 163 * page tables. 164 */ 165 if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) { 166 pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n", 167 cache_policies[cachepolicy].policy); 168 return 0; 169 } 170 171 if (selected != cachepolicy) { 172 unsigned long cr = __clear_cr(cache_policies[selected].cr_mask); 173 cachepolicy = selected; 174 flush_cache_all(); 175 set_cr(cr); 176 } 177 return 0; 178 } 179 early_param("cachepolicy", early_cachepolicy); 180 181 static int __init early_nocache(char *__unused) 182 { 183 char *p = "buffered"; 184 pr_warn("nocache is deprecated; use cachepolicy=%s\n", p); 185 early_cachepolicy(p); 186 return 0; 187 } 188 early_param("nocache", early_nocache); 189 190 static int __init early_nowrite(char *__unused) 191 { 192 char *p = "uncached"; 193 pr_warn("nowb is deprecated; use cachepolicy=%s\n", p); 194 early_cachepolicy(p); 195 return 0; 196 } 197 early_param("nowb", early_nowrite); 198 199 #ifndef CONFIG_ARM_LPAE 200 static int __init early_ecc(char *p) 201 { 202 if (memcmp(p, "on", 2) == 0) 203 ecc_mask = PMD_PROTECTION; 204 else if (memcmp(p, "off", 3) == 0) 205 ecc_mask = 0; 206 return 0; 207 } 208 early_param("ecc", early_ecc); 209 #endif 210 211 #else /* ifdef CONFIG_CPU_CP15 */ 212 213 static int __init early_cachepolicy(char *p) 214 { 215 pr_warn("cachepolicy kernel parameter not supported without cp15\n"); 216 } 217 early_param("cachepolicy", early_cachepolicy); 218 219 static int __init noalign_setup(char *__unused) 220 { 221 pr_warn("noalign kernel parameter not supported without cp15\n"); 222 } 223 __setup("noalign", noalign_setup); 224 225 #endif /* ifdef CONFIG_CPU_CP15 / else */ 226 227 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN 228 #define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE 229 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE 230 231 static struct mem_type mem_types[] __ro_after_init = { 232 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ 233 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | 234 L_PTE_SHARED, 235 .prot_l1 = PMD_TYPE_TABLE, 236 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S, 237 .domain = DOMAIN_IO, 238 }, 239 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ 240 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, 241 .prot_l1 = PMD_TYPE_TABLE, 242 .prot_sect = PROT_SECT_DEVICE, 243 .domain = DOMAIN_IO, 244 }, 245 [MT_DEVICE_CACHED] = { /* ioremap_cache */ 246 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED, 247 .prot_l1 = PMD_TYPE_TABLE, 248 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, 249 .domain = DOMAIN_IO, 250 }, 251 [MT_DEVICE_WC] = { /* ioremap_wc */ 252 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, 253 .prot_l1 = PMD_TYPE_TABLE, 254 .prot_sect = PROT_SECT_DEVICE, 255 .domain = DOMAIN_IO, 256 }, 257 [MT_UNCACHED] = { 258 .prot_pte = PROT_PTE_DEVICE, 259 .prot_l1 = PMD_TYPE_TABLE, 260 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, 261 .domain = DOMAIN_IO, 262 }, 263 [MT_CACHECLEAN] = { 264 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, 265 .domain = DOMAIN_KERNEL, 266 }, 267 #ifndef CONFIG_ARM_LPAE 268 [MT_MINICLEAN] = { 269 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, 270 .domain = DOMAIN_KERNEL, 271 }, 272 #endif 273 [MT_LOW_VECTORS] = { 274 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 275 L_PTE_RDONLY, 276 .prot_l1 = PMD_TYPE_TABLE, 277 .domain = DOMAIN_VECTORS, 278 }, 279 [MT_HIGH_VECTORS] = { 280 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 281 L_PTE_USER | L_PTE_RDONLY, 282 .prot_l1 = PMD_TYPE_TABLE, 283 .domain = DOMAIN_VECTORS, 284 }, 285 [MT_MEMORY_RWX] = { 286 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, 287 .prot_l1 = PMD_TYPE_TABLE, 288 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 289 .domain = DOMAIN_KERNEL, 290 }, 291 [MT_MEMORY_RW] = { 292 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 293 L_PTE_XN, 294 .prot_l1 = PMD_TYPE_TABLE, 295 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 296 .domain = DOMAIN_KERNEL, 297 }, 298 [MT_ROM] = { 299 .prot_sect = PMD_TYPE_SECT, 300 .domain = DOMAIN_KERNEL, 301 }, 302 [MT_MEMORY_RWX_NONCACHED] = { 303 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 304 L_PTE_MT_BUFFERABLE, 305 .prot_l1 = PMD_TYPE_TABLE, 306 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 307 .domain = DOMAIN_KERNEL, 308 }, 309 [MT_MEMORY_RW_DTCM] = { 310 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 311 L_PTE_XN, 312 .prot_l1 = PMD_TYPE_TABLE, 313 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, 314 .domain = DOMAIN_KERNEL, 315 }, 316 [MT_MEMORY_RWX_ITCM] = { 317 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, 318 .prot_l1 = PMD_TYPE_TABLE, 319 .domain = DOMAIN_KERNEL, 320 }, 321 [MT_MEMORY_RW_SO] = { 322 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 323 L_PTE_MT_UNCACHED | L_PTE_XN, 324 .prot_l1 = PMD_TYPE_TABLE, 325 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S | 326 PMD_SECT_UNCACHED | PMD_SECT_XN, 327 .domain = DOMAIN_KERNEL, 328 }, 329 [MT_MEMORY_DMA_READY] = { 330 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 331 L_PTE_XN, 332 .prot_l1 = PMD_TYPE_TABLE, 333 .domain = DOMAIN_KERNEL, 334 }, 335 }; 336 337 const struct mem_type *get_mem_type(unsigned int type) 338 { 339 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; 340 } 341 EXPORT_SYMBOL(get_mem_type); 342 343 static pte_t *(*pte_offset_fixmap)(pmd_t *dir, unsigned long addr); 344 345 static pte_t bm_pte[PTRS_PER_PTE + PTE_HWTABLE_PTRS] 346 __aligned(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE) __initdata; 347 348 static pte_t * __init pte_offset_early_fixmap(pmd_t *dir, unsigned long addr) 349 { 350 return &bm_pte[pte_index(addr)]; 351 } 352 353 static pte_t *pte_offset_late_fixmap(pmd_t *dir, unsigned long addr) 354 { 355 return pte_offset_kernel(dir, addr); 356 } 357 358 static inline pmd_t * __init fixmap_pmd(unsigned long addr) 359 { 360 return pmd_off_k(addr); 361 } 362 363 void __init early_fixmap_init(void) 364 { 365 pmd_t *pmd; 366 367 /* 368 * The early fixmap range spans multiple pmds, for which 369 * we are not prepared: 370 */ 371 BUILD_BUG_ON((__fix_to_virt(__end_of_early_ioremap_region) >> PMD_SHIFT) 372 != FIXADDR_TOP >> PMD_SHIFT); 373 374 pmd = fixmap_pmd(FIXADDR_TOP); 375 pmd_populate_kernel(&init_mm, pmd, bm_pte); 376 377 pte_offset_fixmap = pte_offset_early_fixmap; 378 } 379 380 /* 381 * To avoid TLB flush broadcasts, this uses local_flush_tlb_kernel_range(). 382 * As a result, this can only be called with preemption disabled, as under 383 * stop_machine(). 384 */ 385 void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot) 386 { 387 unsigned long vaddr = __fix_to_virt(idx); 388 pte_t *pte = pte_offset_fixmap(pmd_off_k(vaddr), vaddr); 389 390 /* Make sure fixmap region does not exceed available allocation. */ 391 BUILD_BUG_ON(FIXADDR_START + (__end_of_fixed_addresses * PAGE_SIZE) > 392 FIXADDR_END); 393 BUG_ON(idx >= __end_of_fixed_addresses); 394 395 /* we only support device mappings until pgprot_kernel has been set */ 396 if (WARN_ON(pgprot_val(prot) != pgprot_val(FIXMAP_PAGE_IO) && 397 pgprot_val(pgprot_kernel) == 0)) 398 return; 399 400 if (pgprot_val(prot)) 401 set_pte_at(NULL, vaddr, pte, 402 pfn_pte(phys >> PAGE_SHIFT, prot)); 403 else 404 pte_clear(NULL, vaddr, pte); 405 local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE); 406 } 407 408 /* 409 * Adjust the PMD section entries according to the CPU in use. 410 */ 411 static void __init build_mem_type_table(void) 412 { 413 struct cachepolicy *cp; 414 unsigned int cr = get_cr(); 415 pteval_t user_pgprot, kern_pgprot, vecs_pgprot; 416 int cpu_arch = cpu_architecture(); 417 int i; 418 419 if (cpu_arch < CPU_ARCH_ARMv6) { 420 #if defined(CONFIG_CPU_DCACHE_DISABLE) 421 if (cachepolicy > CPOLICY_BUFFERED) 422 cachepolicy = CPOLICY_BUFFERED; 423 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) 424 if (cachepolicy > CPOLICY_WRITETHROUGH) 425 cachepolicy = CPOLICY_WRITETHROUGH; 426 #endif 427 } 428 if (cpu_arch < CPU_ARCH_ARMv5) { 429 if (cachepolicy >= CPOLICY_WRITEALLOC) 430 cachepolicy = CPOLICY_WRITEBACK; 431 ecc_mask = 0; 432 } 433 434 if (is_smp()) { 435 if (cachepolicy != CPOLICY_WRITEALLOC) { 436 pr_warn("Forcing write-allocate cache policy for SMP\n"); 437 cachepolicy = CPOLICY_WRITEALLOC; 438 } 439 if (!(initial_pmd_value & PMD_SECT_S)) { 440 pr_warn("Forcing shared mappings for SMP\n"); 441 initial_pmd_value |= PMD_SECT_S; 442 } 443 } 444 445 /* 446 * Strip out features not present on earlier architectures. 447 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those 448 * without extended page tables don't have the 'Shared' bit. 449 */ 450 if (cpu_arch < CPU_ARCH_ARMv5) 451 for (i = 0; i < ARRAY_SIZE(mem_types); i++) 452 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7); 453 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3()) 454 for (i = 0; i < ARRAY_SIZE(mem_types); i++) 455 mem_types[i].prot_sect &= ~PMD_SECT_S; 456 457 /* 458 * ARMv5 and lower, bit 4 must be set for page tables (was: cache 459 * "update-able on write" bit on ARM610). However, Xscale and 460 * Xscale3 require this bit to be cleared. 461 */ 462 if (cpu_is_xscale_family()) { 463 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 464 mem_types[i].prot_sect &= ~PMD_BIT4; 465 mem_types[i].prot_l1 &= ~PMD_BIT4; 466 } 467 } else if (cpu_arch < CPU_ARCH_ARMv6) { 468 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 469 if (mem_types[i].prot_l1) 470 mem_types[i].prot_l1 |= PMD_BIT4; 471 if (mem_types[i].prot_sect) 472 mem_types[i].prot_sect |= PMD_BIT4; 473 } 474 } 475 476 /* 477 * Mark the device areas according to the CPU/architecture. 478 */ 479 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) { 480 if (!cpu_is_xsc3()) { 481 /* 482 * Mark device regions on ARMv6+ as execute-never 483 * to prevent speculative instruction fetches. 484 */ 485 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN; 486 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; 487 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; 488 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; 489 490 /* Also setup NX memory mapping */ 491 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN; 492 } 493 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { 494 /* 495 * For ARMv7 with TEX remapping, 496 * - shared device is SXCB=1100 497 * - nonshared device is SXCB=0100 498 * - write combine device mem is SXCB=0001 499 * (Uncached Normal memory) 500 */ 501 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1); 502 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1); 503 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; 504 } else if (cpu_is_xsc3()) { 505 /* 506 * For Xscale3, 507 * - shared device is TEXCB=00101 508 * - nonshared device is TEXCB=01000 509 * - write combine device mem is TEXCB=00100 510 * (Inner/Outer Uncacheable in xsc3 parlance) 511 */ 512 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED; 513 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); 514 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); 515 } else { 516 /* 517 * For ARMv6 and ARMv7 without TEX remapping, 518 * - shared device is TEXCB=00001 519 * - nonshared device is TEXCB=01000 520 * - write combine device mem is TEXCB=00100 521 * (Uncached Normal in ARMv6 parlance). 522 */ 523 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; 524 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); 525 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); 526 } 527 } else { 528 /* 529 * On others, write combining is "Uncached/Buffered" 530 */ 531 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; 532 } 533 534 /* 535 * Now deal with the memory-type mappings 536 */ 537 cp = &cache_policies[cachepolicy]; 538 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; 539 540 #ifndef CONFIG_ARM_LPAE 541 /* 542 * We don't use domains on ARMv6 (since this causes problems with 543 * v6/v7 kernels), so we must use a separate memory type for user 544 * r/o, kernel r/w to map the vectors page. 545 */ 546 if (cpu_arch == CPU_ARCH_ARMv6) 547 vecs_pgprot |= L_PTE_MT_VECTORS; 548 549 /* 550 * Check is it with support for the PXN bit 551 * in the Short-descriptor translation table format descriptors. 552 */ 553 if (cpu_arch == CPU_ARCH_ARMv7 && 554 (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xF) >= 4) { 555 user_pmd_table |= PMD_PXNTABLE; 556 } 557 #endif 558 559 /* 560 * ARMv6 and above have extended page tables. 561 */ 562 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { 563 #ifndef CONFIG_ARM_LPAE 564 /* 565 * Mark cache clean areas and XIP ROM read only 566 * from SVC mode and no access from userspace. 567 */ 568 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 569 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 570 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 571 #endif 572 573 /* 574 * If the initial page tables were created with the S bit 575 * set, then we need to do the same here for the same 576 * reasons given in early_cachepolicy(). 577 */ 578 if (initial_pmd_value & PMD_SECT_S) { 579 user_pgprot |= L_PTE_SHARED; 580 kern_pgprot |= L_PTE_SHARED; 581 vecs_pgprot |= L_PTE_SHARED; 582 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S; 583 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; 584 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; 585 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; 586 mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S; 587 mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED; 588 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S; 589 mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED; 590 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED; 591 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S; 592 mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED; 593 } 594 } 595 596 /* 597 * Non-cacheable Normal - intended for memory areas that must 598 * not cause dirty cache line writebacks when used 599 */ 600 if (cpu_arch >= CPU_ARCH_ARMv6) { 601 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { 602 /* Non-cacheable Normal is XCB = 001 */ 603 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= 604 PMD_SECT_BUFFERED; 605 } else { 606 /* For both ARMv6 and non-TEX-remapping ARMv7 */ 607 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= 608 PMD_SECT_TEX(1); 609 } 610 } else { 611 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; 612 } 613 614 #ifdef CONFIG_ARM_LPAE 615 /* 616 * Do not generate access flag faults for the kernel mappings. 617 */ 618 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 619 mem_types[i].prot_pte |= PTE_EXT_AF; 620 if (mem_types[i].prot_sect) 621 mem_types[i].prot_sect |= PMD_SECT_AF; 622 } 623 kern_pgprot |= PTE_EXT_AF; 624 vecs_pgprot |= PTE_EXT_AF; 625 626 /* 627 * Set PXN for user mappings 628 */ 629 user_pgprot |= PTE_EXT_PXN; 630 #endif 631 632 for (i = 0; i < 16; i++) { 633 pteval_t v = pgprot_val(protection_map[i]); 634 protection_map[i] = __pgprot(v | user_pgprot); 635 } 636 637 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot; 638 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot; 639 640 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); 641 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | 642 L_PTE_DIRTY | kern_pgprot); 643 644 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; 645 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; 646 mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd; 647 mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot; 648 mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd; 649 mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot; 650 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot; 651 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask; 652 mem_types[MT_ROM].prot_sect |= cp->pmd; 653 654 switch (cp->pmd) { 655 case PMD_SECT_WT: 656 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; 657 break; 658 case PMD_SECT_WB: 659 case PMD_SECT_WBWA: 660 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; 661 break; 662 } 663 pr_info("Memory policy: %sData cache %s\n", 664 ecc_mask ? "ECC enabled, " : "", cp->policy); 665 666 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 667 struct mem_type *t = &mem_types[i]; 668 if (t->prot_l1) 669 t->prot_l1 |= PMD_DOMAIN(t->domain); 670 if (t->prot_sect) 671 t->prot_sect |= PMD_DOMAIN(t->domain); 672 } 673 } 674 675 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE 676 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 677 unsigned long size, pgprot_t vma_prot) 678 { 679 if (!pfn_valid(pfn)) 680 return pgprot_noncached(vma_prot); 681 else if (file->f_flags & O_SYNC) 682 return pgprot_writecombine(vma_prot); 683 return vma_prot; 684 } 685 EXPORT_SYMBOL(phys_mem_access_prot); 686 #endif 687 688 #define vectors_base() (vectors_high() ? 0xffff0000 : 0) 689 690 static void __init *early_alloc(unsigned long sz) 691 { 692 void *ptr = memblock_alloc(sz, sz); 693 694 if (!ptr) 695 panic("%s: Failed to allocate %lu bytes align=0x%lx\n", 696 __func__, sz, sz); 697 698 return ptr; 699 } 700 701 static void *__init late_alloc(unsigned long sz) 702 { 703 void *ptr = (void *)__get_free_pages(GFP_PGTABLE_KERNEL, get_order(sz)); 704 705 if (!ptr || !pgtable_pte_page_ctor(virt_to_page(ptr))) 706 BUG(); 707 return ptr; 708 } 709 710 static pte_t * __init arm_pte_alloc(pmd_t *pmd, unsigned long addr, 711 unsigned long prot, 712 void *(*alloc)(unsigned long sz)) 713 { 714 if (pmd_none(*pmd)) { 715 pte_t *pte = alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE); 716 __pmd_populate(pmd, __pa(pte), prot); 717 } 718 BUG_ON(pmd_bad(*pmd)); 719 return pte_offset_kernel(pmd, addr); 720 } 721 722 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, 723 unsigned long prot) 724 { 725 return arm_pte_alloc(pmd, addr, prot, early_alloc); 726 } 727 728 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, 729 unsigned long end, unsigned long pfn, 730 const struct mem_type *type, 731 void *(*alloc)(unsigned long sz), 732 bool ng) 733 { 734 pte_t *pte = arm_pte_alloc(pmd, addr, type->prot_l1, alloc); 735 do { 736 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 737 ng ? PTE_EXT_NG : 0); 738 pfn++; 739 } while (pte++, addr += PAGE_SIZE, addr != end); 740 } 741 742 static void __init __map_init_section(pmd_t *pmd, unsigned long addr, 743 unsigned long end, phys_addr_t phys, 744 const struct mem_type *type, bool ng) 745 { 746 pmd_t *p = pmd; 747 748 #ifndef CONFIG_ARM_LPAE 749 /* 750 * In classic MMU format, puds and pmds are folded in to 751 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a 752 * group of L1 entries making up one logical pointer to 753 * an L2 table (2MB), where as PMDs refer to the individual 754 * L1 entries (1MB). Hence increment to get the correct 755 * offset for odd 1MB sections. 756 * (See arch/arm/include/asm/pgtable-2level.h) 757 */ 758 if (addr & SECTION_SIZE) 759 pmd++; 760 #endif 761 do { 762 *pmd = __pmd(phys | type->prot_sect | (ng ? PMD_SECT_nG : 0)); 763 phys += SECTION_SIZE; 764 } while (pmd++, addr += SECTION_SIZE, addr != end); 765 766 flush_pmd_entry(p); 767 } 768 769 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr, 770 unsigned long end, phys_addr_t phys, 771 const struct mem_type *type, 772 void *(*alloc)(unsigned long sz), bool ng) 773 { 774 pmd_t *pmd = pmd_offset(pud, addr); 775 unsigned long next; 776 777 do { 778 /* 779 * With LPAE, we must loop over to map 780 * all the pmds for the given range. 781 */ 782 next = pmd_addr_end(addr, end); 783 784 /* 785 * Try a section mapping - addr, next and phys must all be 786 * aligned to a section boundary. 787 */ 788 if (type->prot_sect && 789 ((addr | next | phys) & ~SECTION_MASK) == 0) { 790 __map_init_section(pmd, addr, next, phys, type, ng); 791 } else { 792 alloc_init_pte(pmd, addr, next, 793 __phys_to_pfn(phys), type, alloc, ng); 794 } 795 796 phys += next - addr; 797 798 } while (pmd++, addr = next, addr != end); 799 } 800 801 static void __init alloc_init_pud(p4d_t *p4d, unsigned long addr, 802 unsigned long end, phys_addr_t phys, 803 const struct mem_type *type, 804 void *(*alloc)(unsigned long sz), bool ng) 805 { 806 pud_t *pud = pud_offset(p4d, addr); 807 unsigned long next; 808 809 do { 810 next = pud_addr_end(addr, end); 811 alloc_init_pmd(pud, addr, next, phys, type, alloc, ng); 812 phys += next - addr; 813 } while (pud++, addr = next, addr != end); 814 } 815 816 static void __init alloc_init_p4d(pgd_t *pgd, unsigned long addr, 817 unsigned long end, phys_addr_t phys, 818 const struct mem_type *type, 819 void *(*alloc)(unsigned long sz), bool ng) 820 { 821 p4d_t *p4d = p4d_offset(pgd, addr); 822 unsigned long next; 823 824 do { 825 next = p4d_addr_end(addr, end); 826 alloc_init_pud(p4d, addr, next, phys, type, alloc, ng); 827 phys += next - addr; 828 } while (p4d++, addr = next, addr != end); 829 } 830 831 #ifndef CONFIG_ARM_LPAE 832 static void __init create_36bit_mapping(struct mm_struct *mm, 833 struct map_desc *md, 834 const struct mem_type *type, 835 bool ng) 836 { 837 unsigned long addr, length, end; 838 phys_addr_t phys; 839 pgd_t *pgd; 840 841 addr = md->virtual; 842 phys = __pfn_to_phys(md->pfn); 843 length = PAGE_ALIGN(md->length); 844 845 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { 846 pr_err("MM: CPU does not support supersection mapping for 0x%08llx at 0x%08lx\n", 847 (long long)__pfn_to_phys((u64)md->pfn), addr); 848 return; 849 } 850 851 /* N.B. ARMv6 supersections are only defined to work with domain 0. 852 * Since domain assignments can in fact be arbitrary, the 853 * 'domain == 0' check below is required to insure that ARMv6 854 * supersections are only allocated for domain 0 regardless 855 * of the actual domain assignments in use. 856 */ 857 if (type->domain) { 858 pr_err("MM: invalid domain in supersection mapping for 0x%08llx at 0x%08lx\n", 859 (long long)__pfn_to_phys((u64)md->pfn), addr); 860 return; 861 } 862 863 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { 864 pr_err("MM: cannot create mapping for 0x%08llx at 0x%08lx invalid alignment\n", 865 (long long)__pfn_to_phys((u64)md->pfn), addr); 866 return; 867 } 868 869 /* 870 * Shift bits [35:32] of address into bits [23:20] of PMD 871 * (See ARMv6 spec). 872 */ 873 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); 874 875 pgd = pgd_offset(mm, addr); 876 end = addr + length; 877 do { 878 p4d_t *p4d = p4d_offset(pgd, addr); 879 pud_t *pud = pud_offset(p4d, addr); 880 pmd_t *pmd = pmd_offset(pud, addr); 881 int i; 882 883 for (i = 0; i < 16; i++) 884 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER | 885 (ng ? PMD_SECT_nG : 0)); 886 887 addr += SUPERSECTION_SIZE; 888 phys += SUPERSECTION_SIZE; 889 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; 890 } while (addr != end); 891 } 892 #endif /* !CONFIG_ARM_LPAE */ 893 894 static void __init __create_mapping(struct mm_struct *mm, struct map_desc *md, 895 void *(*alloc)(unsigned long sz), 896 bool ng) 897 { 898 unsigned long addr, length, end; 899 phys_addr_t phys; 900 const struct mem_type *type; 901 pgd_t *pgd; 902 903 type = &mem_types[md->type]; 904 905 #ifndef CONFIG_ARM_LPAE 906 /* 907 * Catch 36-bit addresses 908 */ 909 if (md->pfn >= 0x100000) { 910 create_36bit_mapping(mm, md, type, ng); 911 return; 912 } 913 #endif 914 915 addr = md->virtual & PAGE_MASK; 916 phys = __pfn_to_phys(md->pfn); 917 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); 918 919 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { 920 pr_warn("BUG: map for 0x%08llx at 0x%08lx can not be mapped using pages, ignoring.\n", 921 (long long)__pfn_to_phys(md->pfn), addr); 922 return; 923 } 924 925 pgd = pgd_offset(mm, addr); 926 end = addr + length; 927 do { 928 unsigned long next = pgd_addr_end(addr, end); 929 930 alloc_init_p4d(pgd, addr, next, phys, type, alloc, ng); 931 932 phys += next - addr; 933 addr = next; 934 } while (pgd++, addr != end); 935 } 936 937 /* 938 * Create the page directory entries and any necessary 939 * page tables for the mapping specified by `md'. We 940 * are able to cope here with varying sizes and address 941 * offsets, and we take full advantage of sections and 942 * supersections. 943 */ 944 static void __init create_mapping(struct map_desc *md) 945 { 946 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { 947 pr_warn("BUG: not creating mapping for 0x%08llx at 0x%08lx in user region\n", 948 (long long)__pfn_to_phys((u64)md->pfn), md->virtual); 949 return; 950 } 951 952 if (md->type == MT_DEVICE && 953 md->virtual >= PAGE_OFFSET && md->virtual < FIXADDR_START && 954 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) { 955 pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n", 956 (long long)__pfn_to_phys((u64)md->pfn), md->virtual); 957 } 958 959 __create_mapping(&init_mm, md, early_alloc, false); 960 } 961 962 void __init create_mapping_late(struct mm_struct *mm, struct map_desc *md, 963 bool ng) 964 { 965 #ifdef CONFIG_ARM_LPAE 966 p4d_t *p4d; 967 pud_t *pud; 968 969 p4d = p4d_alloc(mm, pgd_offset(mm, md->virtual), md->virtual); 970 if (WARN_ON(!p4d)) 971 return; 972 pud = pud_alloc(mm, p4d, md->virtual); 973 if (WARN_ON(!pud)) 974 return; 975 pmd_alloc(mm, pud, 0); 976 #endif 977 __create_mapping(mm, md, late_alloc, ng); 978 } 979 980 /* 981 * Create the architecture specific mappings 982 */ 983 void __init iotable_init(struct map_desc *io_desc, int nr) 984 { 985 struct map_desc *md; 986 struct vm_struct *vm; 987 struct static_vm *svm; 988 989 if (!nr) 990 return; 991 992 svm = memblock_alloc(sizeof(*svm) * nr, __alignof__(*svm)); 993 if (!svm) 994 panic("%s: Failed to allocate %zu bytes align=0x%zx\n", 995 __func__, sizeof(*svm) * nr, __alignof__(*svm)); 996 997 for (md = io_desc; nr; md++, nr--) { 998 create_mapping(md); 999 1000 vm = &svm->vm; 1001 vm->addr = (void *)(md->virtual & PAGE_MASK); 1002 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); 1003 vm->phys_addr = __pfn_to_phys(md->pfn); 1004 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; 1005 vm->flags |= VM_ARM_MTYPE(md->type); 1006 vm->caller = iotable_init; 1007 add_static_vm_early(svm++); 1008 } 1009 } 1010 1011 void __init vm_reserve_area_early(unsigned long addr, unsigned long size, 1012 void *caller) 1013 { 1014 struct vm_struct *vm; 1015 struct static_vm *svm; 1016 1017 svm = memblock_alloc(sizeof(*svm), __alignof__(*svm)); 1018 if (!svm) 1019 panic("%s: Failed to allocate %zu bytes align=0x%zx\n", 1020 __func__, sizeof(*svm), __alignof__(*svm)); 1021 1022 vm = &svm->vm; 1023 vm->addr = (void *)addr; 1024 vm->size = size; 1025 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING; 1026 vm->caller = caller; 1027 add_static_vm_early(svm); 1028 } 1029 1030 #ifndef CONFIG_ARM_LPAE 1031 1032 /* 1033 * The Linux PMD is made of two consecutive section entries covering 2MB 1034 * (see definition in include/asm/pgtable-2level.h). However a call to 1035 * create_mapping() may optimize static mappings by using individual 1036 * 1MB section mappings. This leaves the actual PMD potentially half 1037 * initialized if the top or bottom section entry isn't used, leaving it 1038 * open to problems if a subsequent ioremap() or vmalloc() tries to use 1039 * the virtual space left free by that unused section entry. 1040 * 1041 * Let's avoid the issue by inserting dummy vm entries covering the unused 1042 * PMD halves once the static mappings are in place. 1043 */ 1044 1045 static void __init pmd_empty_section_gap(unsigned long addr) 1046 { 1047 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap); 1048 } 1049 1050 static void __init fill_pmd_gaps(void) 1051 { 1052 struct static_vm *svm; 1053 struct vm_struct *vm; 1054 unsigned long addr, next = 0; 1055 pmd_t *pmd; 1056 1057 list_for_each_entry(svm, &static_vmlist, list) { 1058 vm = &svm->vm; 1059 addr = (unsigned long)vm->addr; 1060 if (addr < next) 1061 continue; 1062 1063 /* 1064 * Check if this vm starts on an odd section boundary. 1065 * If so and the first section entry for this PMD is free 1066 * then we block the corresponding virtual address. 1067 */ 1068 if ((addr & ~PMD_MASK) == SECTION_SIZE) { 1069 pmd = pmd_off_k(addr); 1070 if (pmd_none(*pmd)) 1071 pmd_empty_section_gap(addr & PMD_MASK); 1072 } 1073 1074 /* 1075 * Then check if this vm ends on an odd section boundary. 1076 * If so and the second section entry for this PMD is empty 1077 * then we block the corresponding virtual address. 1078 */ 1079 addr += vm->size; 1080 if ((addr & ~PMD_MASK) == SECTION_SIZE) { 1081 pmd = pmd_off_k(addr) + 1; 1082 if (pmd_none(*pmd)) 1083 pmd_empty_section_gap(addr); 1084 } 1085 1086 /* no need to look at any vm entry until we hit the next PMD */ 1087 next = (addr + PMD_SIZE - 1) & PMD_MASK; 1088 } 1089 } 1090 1091 #else 1092 #define fill_pmd_gaps() do { } while (0) 1093 #endif 1094 1095 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H) 1096 static void __init pci_reserve_io(void) 1097 { 1098 struct static_vm *svm; 1099 1100 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE); 1101 if (svm) 1102 return; 1103 1104 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io); 1105 } 1106 #else 1107 #define pci_reserve_io() do { } while (0) 1108 #endif 1109 1110 #ifdef CONFIG_DEBUG_LL 1111 void __init debug_ll_io_init(void) 1112 { 1113 struct map_desc map; 1114 1115 debug_ll_addr(&map.pfn, &map.virtual); 1116 if (!map.pfn || !map.virtual) 1117 return; 1118 map.pfn = __phys_to_pfn(map.pfn); 1119 map.virtual &= PAGE_MASK; 1120 map.length = PAGE_SIZE; 1121 map.type = MT_DEVICE; 1122 iotable_init(&map, 1); 1123 } 1124 #endif 1125 1126 static void * __initdata vmalloc_min = 1127 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET); 1128 1129 /* 1130 * vmalloc=size forces the vmalloc area to be exactly 'size' 1131 * bytes. This can be used to increase (or decrease) the vmalloc 1132 * area - the default is 240m. 1133 */ 1134 static int __init early_vmalloc(char *arg) 1135 { 1136 unsigned long vmalloc_reserve = memparse(arg, NULL); 1137 1138 if (vmalloc_reserve < SZ_16M) { 1139 vmalloc_reserve = SZ_16M; 1140 pr_warn("vmalloc area too small, limiting to %luMB\n", 1141 vmalloc_reserve >> 20); 1142 } 1143 1144 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) { 1145 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M); 1146 pr_warn("vmalloc area is too big, limiting to %luMB\n", 1147 vmalloc_reserve >> 20); 1148 } 1149 1150 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve); 1151 return 0; 1152 } 1153 early_param("vmalloc", early_vmalloc); 1154 1155 phys_addr_t arm_lowmem_limit __initdata = 0; 1156 1157 void __init adjust_lowmem_bounds(void) 1158 { 1159 phys_addr_t block_start, block_end, memblock_limit = 0; 1160 u64 vmalloc_limit, i; 1161 phys_addr_t lowmem_limit = 0; 1162 1163 /* 1164 * Let's use our own (unoptimized) equivalent of __pa() that is 1165 * not affected by wrap-arounds when sizeof(phys_addr_t) == 4. 1166 * The result is used as the upper bound on physical memory address 1167 * and may itself be outside the valid range for which phys_addr_t 1168 * and therefore __pa() is defined. 1169 */ 1170 vmalloc_limit = (u64)(uintptr_t)vmalloc_min - PAGE_OFFSET + PHYS_OFFSET; 1171 1172 /* 1173 * The first usable region must be PMD aligned. Mark its start 1174 * as MEMBLOCK_NOMAP if it isn't 1175 */ 1176 for_each_mem_range(i, &block_start, &block_end) { 1177 if (!IS_ALIGNED(block_start, PMD_SIZE)) { 1178 phys_addr_t len; 1179 1180 len = round_up(block_start, PMD_SIZE) - block_start; 1181 memblock_mark_nomap(block_start, len); 1182 } 1183 break; 1184 } 1185 1186 for_each_mem_range(i, &block_start, &block_end) { 1187 if (block_start < vmalloc_limit) { 1188 if (block_end > lowmem_limit) 1189 /* 1190 * Compare as u64 to ensure vmalloc_limit does 1191 * not get truncated. block_end should always 1192 * fit in phys_addr_t so there should be no 1193 * issue with assignment. 1194 */ 1195 lowmem_limit = min_t(u64, 1196 vmalloc_limit, 1197 block_end); 1198 1199 /* 1200 * Find the first non-pmd-aligned page, and point 1201 * memblock_limit at it. This relies on rounding the 1202 * limit down to be pmd-aligned, which happens at the 1203 * end of this function. 1204 * 1205 * With this algorithm, the start or end of almost any 1206 * bank can be non-pmd-aligned. The only exception is 1207 * that the start of the bank 0 must be section- 1208 * aligned, since otherwise memory would need to be 1209 * allocated when mapping the start of bank 0, which 1210 * occurs before any free memory is mapped. 1211 */ 1212 if (!memblock_limit) { 1213 if (!IS_ALIGNED(block_start, PMD_SIZE)) 1214 memblock_limit = block_start; 1215 else if (!IS_ALIGNED(block_end, PMD_SIZE)) 1216 memblock_limit = lowmem_limit; 1217 } 1218 1219 } 1220 } 1221 1222 arm_lowmem_limit = lowmem_limit; 1223 1224 high_memory = __va(arm_lowmem_limit - 1) + 1; 1225 1226 if (!memblock_limit) 1227 memblock_limit = arm_lowmem_limit; 1228 1229 /* 1230 * Round the memblock limit down to a pmd size. This 1231 * helps to ensure that we will allocate memory from the 1232 * last full pmd, which should be mapped. 1233 */ 1234 memblock_limit = round_down(memblock_limit, PMD_SIZE); 1235 1236 if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) { 1237 if (memblock_end_of_DRAM() > arm_lowmem_limit) { 1238 phys_addr_t end = memblock_end_of_DRAM(); 1239 1240 pr_notice("Ignoring RAM at %pa-%pa\n", 1241 &memblock_limit, &end); 1242 pr_notice("Consider using a HIGHMEM enabled kernel.\n"); 1243 1244 memblock_remove(memblock_limit, end - memblock_limit); 1245 } 1246 } 1247 1248 memblock_set_current_limit(memblock_limit); 1249 } 1250 1251 static inline void prepare_page_table(void) 1252 { 1253 unsigned long addr; 1254 phys_addr_t end; 1255 1256 /* 1257 * Clear out all the mappings below the kernel image. 1258 */ 1259 #ifdef CONFIG_KASAN 1260 /* 1261 * KASan's shadow memory inserts itself between the TASK_SIZE 1262 * and MODULES_VADDR. Do not clear the KASan shadow memory mappings. 1263 */ 1264 for (addr = 0; addr < KASAN_SHADOW_START; addr += PMD_SIZE) 1265 pmd_clear(pmd_off_k(addr)); 1266 /* 1267 * Skip over the KASan shadow area. KASAN_SHADOW_END is sometimes 1268 * equal to MODULES_VADDR and then we exit the pmd clearing. If we 1269 * are using a thumb-compiled kernel, there there will be 8MB more 1270 * to clear as KASan always offset to 16 MB below MODULES_VADDR. 1271 */ 1272 for (addr = KASAN_SHADOW_END; addr < MODULES_VADDR; addr += PMD_SIZE) 1273 pmd_clear(pmd_off_k(addr)); 1274 #else 1275 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE) 1276 pmd_clear(pmd_off_k(addr)); 1277 #endif 1278 1279 #ifdef CONFIG_XIP_KERNEL 1280 /* The XIP kernel is mapped in the module area -- skip over it */ 1281 addr = ((unsigned long)_exiprom + PMD_SIZE - 1) & PMD_MASK; 1282 #endif 1283 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE) 1284 pmd_clear(pmd_off_k(addr)); 1285 1286 /* 1287 * Find the end of the first block of lowmem. 1288 */ 1289 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size; 1290 if (end >= arm_lowmem_limit) 1291 end = arm_lowmem_limit; 1292 1293 /* 1294 * Clear out all the kernel space mappings, except for the first 1295 * memory bank, up to the vmalloc region. 1296 */ 1297 for (addr = __phys_to_virt(end); 1298 addr < VMALLOC_START; addr += PMD_SIZE) 1299 pmd_clear(pmd_off_k(addr)); 1300 } 1301 1302 #ifdef CONFIG_ARM_LPAE 1303 /* the first page is reserved for pgd */ 1304 #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \ 1305 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t)) 1306 #else 1307 #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) 1308 #endif 1309 1310 /* 1311 * Reserve the special regions of memory 1312 */ 1313 void __init arm_mm_memblock_reserve(void) 1314 { 1315 /* 1316 * Reserve the page tables. These are already in use, 1317 * and can only be in node 0. 1318 */ 1319 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE); 1320 1321 #ifdef CONFIG_SA1111 1322 /* 1323 * Because of the SA1111 DMA bug, we want to preserve our 1324 * precious DMA-able memory... 1325 */ 1326 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); 1327 #endif 1328 } 1329 1330 /* 1331 * Set up the device mappings. Since we clear out the page tables for all 1332 * mappings above VMALLOC_START, except early fixmap, we might remove debug 1333 * device mappings. This means earlycon can be used to debug this function 1334 * Any other function or debugging method which may touch any device _will_ 1335 * crash the kernel. 1336 */ 1337 static void __init devicemaps_init(const struct machine_desc *mdesc) 1338 { 1339 struct map_desc map; 1340 unsigned long addr; 1341 void *vectors; 1342 1343 /* 1344 * Allocate the vector page early. 1345 */ 1346 vectors = early_alloc(PAGE_SIZE * 2); 1347 1348 early_trap_init(vectors); 1349 1350 /* 1351 * Clear page table except top pmd used by early fixmaps 1352 */ 1353 for (addr = VMALLOC_START; addr < (FIXADDR_TOP & PMD_MASK); addr += PMD_SIZE) 1354 pmd_clear(pmd_off_k(addr)); 1355 1356 if (__atags_pointer) { 1357 /* create a read-only mapping of the device tree */ 1358 map.pfn = __phys_to_pfn(__atags_pointer & SECTION_MASK); 1359 map.virtual = FDT_FIXED_BASE; 1360 map.length = FDT_FIXED_SIZE; 1361 map.type = MT_ROM; 1362 create_mapping(&map); 1363 } 1364 1365 /* 1366 * Map the kernel if it is XIP. 1367 * It is always first in the modulearea. 1368 */ 1369 #ifdef CONFIG_XIP_KERNEL 1370 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); 1371 map.virtual = MODULES_VADDR; 1372 map.length = ((unsigned long)_exiprom - map.virtual + ~SECTION_MASK) & SECTION_MASK; 1373 map.type = MT_ROM; 1374 create_mapping(&map); 1375 #endif 1376 1377 /* 1378 * Map the cache flushing regions. 1379 */ 1380 #ifdef FLUSH_BASE 1381 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); 1382 map.virtual = FLUSH_BASE; 1383 map.length = SZ_1M; 1384 map.type = MT_CACHECLEAN; 1385 create_mapping(&map); 1386 #endif 1387 #ifdef FLUSH_BASE_MINICACHE 1388 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); 1389 map.virtual = FLUSH_BASE_MINICACHE; 1390 map.length = SZ_1M; 1391 map.type = MT_MINICLEAN; 1392 create_mapping(&map); 1393 #endif 1394 1395 /* 1396 * Create a mapping for the machine vectors at the high-vectors 1397 * location (0xffff0000). If we aren't using high-vectors, also 1398 * create a mapping at the low-vectors virtual address. 1399 */ 1400 map.pfn = __phys_to_pfn(virt_to_phys(vectors)); 1401 map.virtual = 0xffff0000; 1402 map.length = PAGE_SIZE; 1403 #ifdef CONFIG_KUSER_HELPERS 1404 map.type = MT_HIGH_VECTORS; 1405 #else 1406 map.type = MT_LOW_VECTORS; 1407 #endif 1408 create_mapping(&map); 1409 1410 if (!vectors_high()) { 1411 map.virtual = 0; 1412 map.length = PAGE_SIZE * 2; 1413 map.type = MT_LOW_VECTORS; 1414 create_mapping(&map); 1415 } 1416 1417 /* Now create a kernel read-only mapping */ 1418 map.pfn += 1; 1419 map.virtual = 0xffff0000 + PAGE_SIZE; 1420 map.length = PAGE_SIZE; 1421 map.type = MT_LOW_VECTORS; 1422 create_mapping(&map); 1423 1424 /* 1425 * Ask the machine support to map in the statically mapped devices. 1426 */ 1427 if (mdesc->map_io) 1428 mdesc->map_io(); 1429 else 1430 debug_ll_io_init(); 1431 fill_pmd_gaps(); 1432 1433 /* Reserve fixed i/o space in VMALLOC region */ 1434 pci_reserve_io(); 1435 1436 /* 1437 * Finally flush the caches and tlb to ensure that we're in a 1438 * consistent state wrt the writebuffer. This also ensures that 1439 * any write-allocated cache lines in the vector page are written 1440 * back. After this point, we can start to touch devices again. 1441 */ 1442 local_flush_tlb_all(); 1443 flush_cache_all(); 1444 1445 /* Enable asynchronous aborts */ 1446 early_abt_enable(); 1447 } 1448 1449 static void __init kmap_init(void) 1450 { 1451 #ifdef CONFIG_HIGHMEM 1452 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE), 1453 PKMAP_BASE, _PAGE_KERNEL_TABLE); 1454 #endif 1455 1456 early_pte_alloc(pmd_off_k(FIXADDR_START), FIXADDR_START, 1457 _PAGE_KERNEL_TABLE); 1458 } 1459 1460 static void __init map_lowmem(void) 1461 { 1462 phys_addr_t kernel_x_start = round_down(__pa(KERNEL_START), SECTION_SIZE); 1463 phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE); 1464 phys_addr_t start, end; 1465 u64 i; 1466 1467 /* Map all the lowmem memory banks. */ 1468 for_each_mem_range(i, &start, &end) { 1469 struct map_desc map; 1470 1471 if (end > arm_lowmem_limit) 1472 end = arm_lowmem_limit; 1473 if (start >= end) 1474 break; 1475 1476 if (end < kernel_x_start) { 1477 map.pfn = __phys_to_pfn(start); 1478 map.virtual = __phys_to_virt(start); 1479 map.length = end - start; 1480 map.type = MT_MEMORY_RWX; 1481 1482 create_mapping(&map); 1483 } else if (start >= kernel_x_end) { 1484 map.pfn = __phys_to_pfn(start); 1485 map.virtual = __phys_to_virt(start); 1486 map.length = end - start; 1487 map.type = MT_MEMORY_RW; 1488 1489 create_mapping(&map); 1490 } else { 1491 /* This better cover the entire kernel */ 1492 if (start < kernel_x_start) { 1493 map.pfn = __phys_to_pfn(start); 1494 map.virtual = __phys_to_virt(start); 1495 map.length = kernel_x_start - start; 1496 map.type = MT_MEMORY_RW; 1497 1498 create_mapping(&map); 1499 } 1500 1501 map.pfn = __phys_to_pfn(kernel_x_start); 1502 map.virtual = __phys_to_virt(kernel_x_start); 1503 map.length = kernel_x_end - kernel_x_start; 1504 map.type = MT_MEMORY_RWX; 1505 1506 create_mapping(&map); 1507 1508 if (kernel_x_end < end) { 1509 map.pfn = __phys_to_pfn(kernel_x_end); 1510 map.virtual = __phys_to_virt(kernel_x_end); 1511 map.length = end - kernel_x_end; 1512 map.type = MT_MEMORY_RW; 1513 1514 create_mapping(&map); 1515 } 1516 } 1517 } 1518 } 1519 1520 #ifdef CONFIG_ARM_PV_FIXUP 1521 typedef void pgtables_remap(long long offset, unsigned long pgd); 1522 pgtables_remap lpae_pgtables_remap_asm; 1523 1524 /* 1525 * early_paging_init() recreates boot time page table setup, allowing machines 1526 * to switch over to a high (>4G) address space on LPAE systems 1527 */ 1528 static void __init early_paging_init(const struct machine_desc *mdesc) 1529 { 1530 pgtables_remap *lpae_pgtables_remap; 1531 unsigned long pa_pgd; 1532 unsigned int cr, ttbcr; 1533 long long offset; 1534 1535 if (!mdesc->pv_fixup) 1536 return; 1537 1538 offset = mdesc->pv_fixup(); 1539 if (offset == 0) 1540 return; 1541 1542 /* 1543 * Get the address of the remap function in the 1:1 identity 1544 * mapping setup by the early page table assembly code. We 1545 * must get this prior to the pv update. The following barrier 1546 * ensures that this is complete before we fixup any P:V offsets. 1547 */ 1548 lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm); 1549 pa_pgd = __pa(swapper_pg_dir); 1550 barrier(); 1551 1552 pr_info("Switching physical address space to 0x%08llx\n", 1553 (u64)PHYS_OFFSET + offset); 1554 1555 /* Re-set the phys pfn offset, and the pv offset */ 1556 __pv_offset += offset; 1557 __pv_phys_pfn_offset += PFN_DOWN(offset); 1558 1559 /* Run the patch stub to update the constants */ 1560 fixup_pv_table(&__pv_table_begin, 1561 (&__pv_table_end - &__pv_table_begin) << 2); 1562 1563 /* 1564 * We changing not only the virtual to physical mapping, but also 1565 * the physical addresses used to access memory. We need to flush 1566 * all levels of cache in the system with caching disabled to 1567 * ensure that all data is written back, and nothing is prefetched 1568 * into the caches. We also need to prevent the TLB walkers 1569 * allocating into the caches too. Note that this is ARMv7 LPAE 1570 * specific. 1571 */ 1572 cr = get_cr(); 1573 set_cr(cr & ~(CR_I | CR_C)); 1574 asm("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr)); 1575 asm volatile("mcr p15, 0, %0, c2, c0, 2" 1576 : : "r" (ttbcr & ~(3 << 8 | 3 << 10))); 1577 flush_cache_all(); 1578 1579 /* 1580 * Fixup the page tables - this must be in the idmap region as 1581 * we need to disable the MMU to do this safely, and hence it 1582 * needs to be assembly. It's fairly simple, as we're using the 1583 * temporary tables setup by the initial assembly code. 1584 */ 1585 lpae_pgtables_remap(offset, pa_pgd); 1586 1587 /* Re-enable the caches and cacheable TLB walks */ 1588 asm volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr)); 1589 set_cr(cr); 1590 } 1591 1592 #else 1593 1594 static void __init early_paging_init(const struct machine_desc *mdesc) 1595 { 1596 long long offset; 1597 1598 if (!mdesc->pv_fixup) 1599 return; 1600 1601 offset = mdesc->pv_fixup(); 1602 if (offset == 0) 1603 return; 1604 1605 pr_crit("Physical address space modification is only to support Keystone2.\n"); 1606 pr_crit("Please enable ARM_LPAE and ARM_PATCH_PHYS_VIRT support to use this\n"); 1607 pr_crit("feature. Your kernel may crash now, have a good day.\n"); 1608 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1609 } 1610 1611 #endif 1612 1613 static void __init early_fixmap_shutdown(void) 1614 { 1615 int i; 1616 unsigned long va = fix_to_virt(__end_of_permanent_fixed_addresses - 1); 1617 1618 pte_offset_fixmap = pte_offset_late_fixmap; 1619 pmd_clear(fixmap_pmd(va)); 1620 local_flush_tlb_kernel_page(va); 1621 1622 for (i = 0; i < __end_of_permanent_fixed_addresses; i++) { 1623 pte_t *pte; 1624 struct map_desc map; 1625 1626 map.virtual = fix_to_virt(i); 1627 pte = pte_offset_early_fixmap(pmd_off_k(map.virtual), map.virtual); 1628 1629 /* Only i/o device mappings are supported ATM */ 1630 if (pte_none(*pte) || 1631 (pte_val(*pte) & L_PTE_MT_MASK) != L_PTE_MT_DEV_SHARED) 1632 continue; 1633 1634 map.pfn = pte_pfn(*pte); 1635 map.type = MT_DEVICE; 1636 map.length = PAGE_SIZE; 1637 1638 create_mapping(&map); 1639 } 1640 } 1641 1642 /* 1643 * paging_init() sets up the page tables, initialises the zone memory 1644 * maps, and sets up the zero page, bad page and bad page tables. 1645 */ 1646 void __init paging_init(const struct machine_desc *mdesc) 1647 { 1648 void *zero_page; 1649 1650 prepare_page_table(); 1651 map_lowmem(); 1652 memblock_set_current_limit(arm_lowmem_limit); 1653 dma_contiguous_remap(); 1654 early_fixmap_shutdown(); 1655 devicemaps_init(mdesc); 1656 kmap_init(); 1657 tcm_init(); 1658 1659 top_pmd = pmd_off_k(0xffff0000); 1660 1661 /* allocate the zero page. */ 1662 zero_page = early_alloc(PAGE_SIZE); 1663 1664 bootmem_init(); 1665 1666 empty_zero_page = virt_to_page(zero_page); 1667 __flush_dcache_page(NULL, empty_zero_page); 1668 } 1669 1670 void __init early_mm_init(const struct machine_desc *mdesc) 1671 { 1672 build_mem_type_table(); 1673 early_paging_init(mdesc); 1674 } 1675 1676 void set_pte_at(struct mm_struct *mm, unsigned long addr, 1677 pte_t *ptep, pte_t pteval) 1678 { 1679 unsigned long ext = 0; 1680 1681 if (addr < TASK_SIZE && pte_valid_user(pteval)) { 1682 if (!pte_special(pteval)) 1683 __sync_icache_dcache(pteval); 1684 ext |= PTE_EXT_NG; 1685 } 1686 1687 set_pte_ext(ptep, pteval, ext); 1688 } 1689