1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * L2C-310 early resume code. This can be used by platforms to restore 4 * the settings of their L2 cache controller before restoring the 5 * processor state. 6 * 7 * This code can only be used to if you are running in the secure world. 8 */ 9#include <linux/linkage.h> 10#include <asm/assembler.h> 11#include <asm/hardware/cache-l2x0.h> 12 13 .text 14 15ENTRY(l2c310_early_resume) 16 adr r0, 1f 17 ldr r2, [r0] 18 add r0, r2, r0 19 20 ldmia r0, {r1, r2, r3, r4, r5, r6, r7, r8} 21 @ r1 = phys address of L2C-310 controller 22 @ r2 = aux_ctrl 23 @ r3 = tag_latency 24 @ r4 = data_latency 25 @ r5 = filter_start 26 @ r6 = filter_end 27 @ r7 = prefetch_ctrl 28 @ r8 = pwr_ctrl 29 30 @ Check that the address has been initialised 31 teq r1, #0 32 reteq lr 33 34 @ The prefetch and power control registers are revision dependent 35 @ and can be written whether or not the L2 cache is enabled 36 ldr r0, [r1, #L2X0_CACHE_ID] 37 and r0, r0, #L2X0_CACHE_ID_RTL_MASK 38 cmp r0, #L310_CACHE_ID_RTL_R2P0 39 strcs r7, [r1, #L310_PREFETCH_CTRL] 40 cmp r0, #L310_CACHE_ID_RTL_R3P0 41 strcs r8, [r1, #L310_POWER_CTRL] 42 43 @ Don't setup the L2 cache if it is already enabled 44 ldr r0, [r1, #L2X0_CTRL] 45 tst r0, #L2X0_CTRL_EN 46 retne lr 47 48 str r3, [r1, #L310_TAG_LATENCY_CTRL] 49 str r4, [r1, #L310_DATA_LATENCY_CTRL] 50 str r6, [r1, #L310_ADDR_FILTER_END] 51 str r5, [r1, #L310_ADDR_FILTER_START] 52 53 str r2, [r1, #L2X0_AUX_CTRL] 54 mov r9, #L2X0_CTRL_EN 55 str r9, [r1, #L2X0_CTRL] 56 ret lr 57ENDPROC(l2c310_early_resume) 58 59 .align 601: .long l2x0_saved_regs - . 61