1 /* 2 * linux/arch/arm/mm/flush.c 3 * 4 * Copyright (C) 1995-2002 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #include <linux/module.h> 11 #include <linux/mm.h> 12 #include <linux/pagemap.h> 13 14 #include <asm/cacheflush.h> 15 #include <asm/cachetype.h> 16 #include <asm/system.h> 17 #include <asm/tlbflush.h> 18 19 #include "mm.h" 20 21 #ifdef CONFIG_ARM_ERRATA_411920 22 extern void v6_icache_inval_all(void); 23 #endif 24 25 #ifdef CONFIG_CPU_CACHE_VIPT 26 27 #define ALIAS_FLUSH_START 0xffff4000 28 29 static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr) 30 { 31 unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT); 32 const int zero = 0; 33 34 set_pte_ext(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL), 0); 35 flush_tlb_kernel_page(to); 36 37 asm( "mcrr p15, 0, %1, %0, c14\n" 38 " mcr p15, 0, %2, c7, c10, 4\n" 39 #ifndef CONFIG_ARM_ERRATA_411920 40 " mcr p15, 0, %2, c7, c5, 0\n" 41 #endif 42 : 43 : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero) 44 : "cc"); 45 #ifdef CONFIG_ARM_ERRATA_411920 46 v6_icache_inval_all(); 47 #endif 48 } 49 50 void flush_cache_mm(struct mm_struct *mm) 51 { 52 if (cache_is_vivt()) { 53 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm))) 54 __cpuc_flush_user_all(); 55 return; 56 } 57 58 if (cache_is_vipt_aliasing()) { 59 asm( "mcr p15, 0, %0, c7, c14, 0\n" 60 " mcr p15, 0, %0, c7, c10, 4\n" 61 #ifndef CONFIG_ARM_ERRATA_411920 62 " mcr p15, 0, %0, c7, c5, 0\n" 63 #endif 64 : 65 : "r" (0) 66 : "cc"); 67 #ifdef CONFIG_ARM_ERRATA_411920 68 v6_icache_inval_all(); 69 #endif 70 } 71 } 72 73 void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) 74 { 75 if (cache_is_vivt()) { 76 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) 77 __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end), 78 vma->vm_flags); 79 return; 80 } 81 82 if (cache_is_vipt_aliasing()) { 83 asm( "mcr p15, 0, %0, c7, c14, 0\n" 84 " mcr p15, 0, %0, c7, c10, 4\n" 85 #ifndef CONFIG_ARM_ERRATA_411920 86 " mcr p15, 0, %0, c7, c5, 0\n" 87 #endif 88 : 89 : "r" (0) 90 : "cc"); 91 #ifdef CONFIG_ARM_ERRATA_411920 92 v6_icache_inval_all(); 93 #endif 94 } 95 } 96 97 void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn) 98 { 99 if (cache_is_vivt()) { 100 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) { 101 unsigned long addr = user_addr & PAGE_MASK; 102 __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags); 103 } 104 return; 105 } 106 107 if (cache_is_vipt_aliasing()) 108 flush_pfn_alias(pfn, user_addr); 109 } 110 111 void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, 112 unsigned long uaddr, void *kaddr, 113 unsigned long len, int write) 114 { 115 if (cache_is_vivt()) { 116 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) { 117 unsigned long addr = (unsigned long)kaddr; 118 __cpuc_coherent_kern_range(addr, addr + len); 119 } 120 return; 121 } 122 123 if (cache_is_vipt_aliasing()) { 124 flush_pfn_alias(page_to_pfn(page), uaddr); 125 return; 126 } 127 128 /* VIPT non-aliasing cache */ 129 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm)) && 130 vma->vm_flags & VM_EXEC) { 131 unsigned long addr = (unsigned long)kaddr; 132 /* only flushing the kernel mapping on non-aliasing VIPT */ 133 __cpuc_coherent_kern_range(addr, addr + len); 134 } 135 } 136 #else 137 #define flush_pfn_alias(pfn,vaddr) do { } while (0) 138 #endif 139 140 void __flush_dcache_page(struct address_space *mapping, struct page *page) 141 { 142 /* 143 * Writeback any data associated with the kernel mapping of this 144 * page. This ensures that data in the physical page is mutually 145 * coherent with the kernels mapping. 146 */ 147 #ifdef CONFIG_HIGHMEM 148 /* 149 * kmap_atomic() doesn't set the page virtual address, and 150 * kunmap_atomic() takes care of cache flushing already. 151 */ 152 if (page_address(page)) 153 #endif 154 __cpuc_flush_dcache_page(page_address(page)); 155 156 /* 157 * If this is a page cache page, and we have an aliasing VIPT cache, 158 * we only need to do one flush - which would be at the relevant 159 * userspace colour, which is congruent with page->index. 160 */ 161 if (mapping && cache_is_vipt_aliasing()) 162 flush_pfn_alias(page_to_pfn(page), 163 page->index << PAGE_CACHE_SHIFT); 164 } 165 166 static void __flush_dcache_aliases(struct address_space *mapping, struct page *page) 167 { 168 struct mm_struct *mm = current->active_mm; 169 struct vm_area_struct *mpnt; 170 struct prio_tree_iter iter; 171 pgoff_t pgoff; 172 173 /* 174 * There are possible user space mappings of this page: 175 * - VIVT cache: we need to also write back and invalidate all user 176 * data in the current VM view associated with this page. 177 * - aliasing VIPT: we only need to find one mapping of this page. 178 */ 179 pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT); 180 181 flush_dcache_mmap_lock(mapping); 182 vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) { 183 unsigned long offset; 184 185 /* 186 * If this VMA is not in our MM, we can ignore it. 187 */ 188 if (mpnt->vm_mm != mm) 189 continue; 190 if (!(mpnt->vm_flags & VM_MAYSHARE)) 191 continue; 192 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT; 193 flush_cache_page(mpnt, mpnt->vm_start + offset, page_to_pfn(page)); 194 } 195 flush_dcache_mmap_unlock(mapping); 196 } 197 198 /* 199 * Ensure cache coherency between kernel mapping and userspace mapping 200 * of this page. 201 * 202 * We have three cases to consider: 203 * - VIPT non-aliasing cache: fully coherent so nothing required. 204 * - VIVT: fully aliasing, so we need to handle every alias in our 205 * current VM view. 206 * - VIPT aliasing: need to handle one alias in our current VM view. 207 * 208 * If we need to handle aliasing: 209 * If the page only exists in the page cache and there are no user 210 * space mappings, we can be lazy and remember that we may have dirty 211 * kernel cache lines for later. Otherwise, we assume we have 212 * aliasing mappings. 213 * 214 * Note that we disable the lazy flush for SMP. 215 */ 216 void flush_dcache_page(struct page *page) 217 { 218 struct address_space *mapping = page_mapping(page); 219 220 #ifndef CONFIG_SMP 221 if (!PageHighMem(page) && mapping && !mapping_mapped(mapping)) 222 set_bit(PG_dcache_dirty, &page->flags); 223 else 224 #endif 225 { 226 __flush_dcache_page(mapping, page); 227 if (mapping && cache_is_vivt()) 228 __flush_dcache_aliases(mapping, page); 229 else if (mapping) 230 __flush_icache_all(); 231 } 232 } 233 EXPORT_SYMBOL(flush_dcache_page); 234 235 /* 236 * Flush an anonymous page so that users of get_user_pages() 237 * can safely access the data. The expected sequence is: 238 * 239 * get_user_pages() 240 * -> flush_anon_page 241 * memcpy() to/from page 242 * if written to page, flush_dcache_page() 243 */ 244 void __flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr) 245 { 246 unsigned long pfn; 247 248 /* VIPT non-aliasing caches need do nothing */ 249 if (cache_is_vipt_nonaliasing()) 250 return; 251 252 /* 253 * Write back and invalidate userspace mapping. 254 */ 255 pfn = page_to_pfn(page); 256 if (cache_is_vivt()) { 257 flush_cache_page(vma, vmaddr, pfn); 258 } else { 259 /* 260 * For aliasing VIPT, we can flush an alias of the 261 * userspace address only. 262 */ 263 flush_pfn_alias(pfn, vmaddr); 264 } 265 266 /* 267 * Invalidate kernel mapping. No data should be contained 268 * in this mapping of the page. FIXME: this is overkill 269 * since we actually ask for a write-back and invalidate. 270 */ 271 __cpuc_flush_dcache_page(page_address(page)); 272 } 273