1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/arch/arm/mm/copypage-v4wt.S 4 * 5 * Copyright (C) 1995-1999 Russell King 6 * 7 * This is for CPUs with a writethrough cache and 'flush ID cache' is 8 * the only supported cache operation. 9 */ 10 #include <linux/init.h> 11 #include <linux/highmem.h> 12 13 /* 14 * ARMv4 optimised copy_user_highpage 15 * 16 * Since we have writethrough caches, we don't have to worry about 17 * dirty data in the cache. However, we do have to ensure that 18 * subsequent reads are up to date. 19 */ 20 static void v4wt_copy_user_page(void *kto, const void *kfrom) 21 { 22 int tmp; 23 24 asm volatile ("\ 25 .syntax unified\n\ 26 ldmia %1!, {r3, r4, ip, lr} @ 4\n\ 27 1: stmia %0!, {r3, r4, ip, lr} @ 4\n\ 28 ldmia %1!, {r3, r4, ip, lr} @ 4+1\n\ 29 stmia %0!, {r3, r4, ip, lr} @ 4\n\ 30 ldmia %1!, {r3, r4, ip, lr} @ 4\n\ 31 stmia %0!, {r3, r4, ip, lr} @ 4\n\ 32 ldmia %1!, {r3, r4, ip, lr} @ 4\n\ 33 subs %2, %2, #1 @ 1\n\ 34 stmia %0!, {r3, r4, ip, lr} @ 4\n\ 35 ldmiane %1!, {r3, r4, ip, lr} @ 4\n\ 36 bne 1b @ 1\n\ 37 mcr p15, 0, %2, c7, c7, 0 @ flush ID cache" 38 : "+&r" (kto), "+&r" (kfrom), "=&r" (tmp) 39 : "2" (PAGE_SIZE / 64) 40 : "r3", "r4", "ip", "lr"); 41 } 42 43 void v4wt_copy_user_highpage(struct page *to, struct page *from, 44 unsigned long vaddr, struct vm_area_struct *vma) 45 { 46 void *kto, *kfrom; 47 48 kto = kmap_atomic(to); 49 kfrom = kmap_atomic(from); 50 v4wt_copy_user_page(kto, kfrom); 51 kunmap_atomic(kfrom); 52 kunmap_atomic(kto); 53 } 54 55 /* 56 * ARMv4 optimised clear_user_page 57 * 58 * Same story as above. 59 */ 60 void v4wt_clear_user_highpage(struct page *page, unsigned long vaddr) 61 { 62 void *ptr, *kaddr = kmap_atomic(page); 63 asm volatile("\ 64 mov r1, %2 @ 1\n\ 65 mov r2, #0 @ 1\n\ 66 mov r3, #0 @ 1\n\ 67 mov ip, #0 @ 1\n\ 68 mov lr, #0 @ 1\n\ 69 1: stmia %0!, {r2, r3, ip, lr} @ 4\n\ 70 stmia %0!, {r2, r3, ip, lr} @ 4\n\ 71 stmia %0!, {r2, r3, ip, lr} @ 4\n\ 72 stmia %0!, {r2, r3, ip, lr} @ 4\n\ 73 subs r1, r1, #1 @ 1\n\ 74 bne 1b @ 1\n\ 75 mcr p15, 0, r2, c7, c7, 0 @ flush ID cache" 76 : "=r" (ptr) 77 : "0" (kaddr), "I" (PAGE_SIZE / 64) 78 : "r1", "r2", "r3", "ip", "lr"); 79 kunmap_atomic(kaddr); 80 } 81 82 struct cpu_user_fns v4wt_user_fns __initdata = { 83 .cpu_clear_user_highpage = v4wt_clear_user_highpage, 84 .cpu_copy_user_highpage = v4wt_copy_user_highpage, 85 }; 86