1 /* 2 * linux/arch/arm/lib/copypage-armv4mc.S 3 * 4 * Copyright (C) 1995-2005 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This handles the mini data cache, as found on SA11x0 and XScale 11 * processors. When we copy a user page page, we map it in such a way 12 * that accesses to this page will not touch the main data cache, but 13 * will be cached in the mini data cache. This prevents us thrashing 14 * the main data cache on page faults. 15 */ 16 #include <linux/init.h> 17 #include <linux/mm.h> 18 #include <linux/highmem.h> 19 20 #include <asm/pgtable.h> 21 #include <asm/tlbflush.h> 22 #include <asm/cacheflush.h> 23 24 #include "mm.h" 25 26 #define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \ 27 L_PTE_MT_MINICACHE) 28 29 static DEFINE_RAW_SPINLOCK(minicache_lock); 30 31 /* 32 * ARMv4 mini-dcache optimised copy_user_highpage 33 * 34 * We flush the destination cache lines just before we write the data into the 35 * corresponding address. Since the Dcache is read-allocate, this removes the 36 * Dcache aliasing issue. The writes will be forwarded to the write buffer, 37 * and merged as appropriate. 38 * 39 * Note: We rely on all ARMv4 processors implementing the "invalidate D line" 40 * instruction. If your processor does not supply this, you have to write your 41 * own copy_user_highpage that does the right thing. 42 */ 43 static void __naked 44 mc_copy_user_page(void *from, void *to) 45 { 46 asm volatile( 47 "stmfd sp!, {r4, lr} @ 2\n\ 48 mov r4, %2 @ 1\n\ 49 ldmia %0!, {r2, r3, ip, lr} @ 4\n\ 50 1: mcr p15, 0, %1, c7, c6, 1 @ 1 invalidate D line\n\ 51 stmia %1!, {r2, r3, ip, lr} @ 4\n\ 52 ldmia %0!, {r2, r3, ip, lr} @ 4+1\n\ 53 stmia %1!, {r2, r3, ip, lr} @ 4\n\ 54 ldmia %0!, {r2, r3, ip, lr} @ 4\n\ 55 mcr p15, 0, %1, c7, c6, 1 @ 1 invalidate D line\n\ 56 stmia %1!, {r2, r3, ip, lr} @ 4\n\ 57 ldmia %0!, {r2, r3, ip, lr} @ 4\n\ 58 subs r4, r4, #1 @ 1\n\ 59 stmia %1!, {r2, r3, ip, lr} @ 4\n\ 60 ldmneia %0!, {r2, r3, ip, lr} @ 4\n\ 61 bne 1b @ 1\n\ 62 ldmfd sp!, {r4, pc} @ 3" 63 : 64 : "r" (from), "r" (to), "I" (PAGE_SIZE / 64)); 65 } 66 67 void v4_mc_copy_user_highpage(struct page *to, struct page *from, 68 unsigned long vaddr, struct vm_area_struct *vma) 69 { 70 void *kto = kmap_atomic(to); 71 72 if (!test_and_set_bit(PG_dcache_clean, &from->flags)) 73 __flush_dcache_page(page_mapping(from), from); 74 75 raw_spin_lock(&minicache_lock); 76 77 set_top_pte(COPYPAGE_MINICACHE, mk_pte(from, minicache_pgprot)); 78 79 mc_copy_user_page((void *)COPYPAGE_MINICACHE, kto); 80 81 raw_spin_unlock(&minicache_lock); 82 83 kunmap_atomic(kto); 84 } 85 86 /* 87 * ARMv4 optimised clear_user_page 88 */ 89 void v4_mc_clear_user_highpage(struct page *page, unsigned long vaddr) 90 { 91 void *ptr, *kaddr = kmap_atomic(page); 92 asm volatile("\ 93 mov r1, %2 @ 1\n\ 94 mov r2, #0 @ 1\n\ 95 mov r3, #0 @ 1\n\ 96 mov ip, #0 @ 1\n\ 97 mov lr, #0 @ 1\n\ 98 1: mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\ 99 stmia %0!, {r2, r3, ip, lr} @ 4\n\ 100 stmia %0!, {r2, r3, ip, lr} @ 4\n\ 101 mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\ 102 stmia %0!, {r2, r3, ip, lr} @ 4\n\ 103 stmia %0!, {r2, r3, ip, lr} @ 4\n\ 104 subs r1, r1, #1 @ 1\n\ 105 bne 1b @ 1" 106 : "=r" (ptr) 107 : "0" (kaddr), "I" (PAGE_SIZE / 64) 108 : "r1", "r2", "r3", "ip", "lr"); 109 kunmap_atomic(kaddr); 110 } 111 112 struct cpu_user_fns v4_mc_user_fns __initdata = { 113 .cpu_clear_user_highpage = v4_mc_clear_user_highpage, 114 .cpu_copy_user_highpage = v4_mc_copy_user_highpage, 115 }; 116