1/* 2 * linux/arch/arm/mm/cache-v7.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Copyright (C) 2005 ARM Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This is the "shell" of the ARMv7 processor support. 12 */ 13#include <linux/linkage.h> 14#include <linux/init.h> 15#include <asm/assembler.h> 16 17#include "proc-macros.S" 18 19/* 20 * v7_flush_dcache_all() 21 * 22 * Flush the whole D-cache. 23 * 24 * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) 25 * 26 * - mm - mm_struct describing address space 27 */ 28ENTRY(v7_flush_dcache_all) 29 dmb @ ensure ordering with previous memory accesses 30 mrc p15, 1, r0, c0, c0, 1 @ read clidr 31 ands r3, r0, #0x7000000 @ extract loc from clidr 32 mov r3, r3, lsr #23 @ left align loc bit field 33 beq finished @ if loc is 0, then no need to clean 34 mov r10, #0 @ start clean at cache level 0 35loop1: 36 add r2, r10, r10, lsr #1 @ work out 3x current cache level 37 mov r1, r0, lsr r2 @ extract cache type bits from clidr 38 and r1, r1, #7 @ mask of the bits for current cache only 39 cmp r1, #2 @ see what cache we have at this level 40 blt skip @ skip if no cache, or just i-cache 41 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 42 isb @ isb to sych the new cssr&csidr 43 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr 44 and r2, r1, #7 @ extract the length of the cache lines 45 add r2, r2, #4 @ add 4 (line length offset) 46 ldr r4, =0x3ff 47 ands r4, r4, r1, lsr #3 @ find maximum number on the way size 48 clz r5, r4 @ find bit position of way size increment 49 ldr r7, =0x7fff 50 ands r7, r7, r1, lsr #13 @ extract max number of the index size 51loop2: 52 mov r9, r4 @ create working copy of max way size 53loop3: 54 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11 55 THUMB( lsl r6, r9, r5 ) 56 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 57 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11 58 THUMB( lsl r6, r7, r2 ) 59 THUMB( orr r11, r11, r6 ) @ factor index number into r11 60 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 61 subs r9, r9, #1 @ decrement the way 62 bge loop3 63 subs r7, r7, #1 @ decrement the index 64 bge loop2 65skip: 66 add r10, r10, #2 @ increment cache number 67 cmp r3, r10 68 bgt loop1 69finished: 70 mov r10, #0 @ swith back to cache level 0 71 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 72 dsb 73 isb 74 mov pc, lr 75ENDPROC(v7_flush_dcache_all) 76 77/* 78 * v7_flush_cache_all() 79 * 80 * Flush the entire cache system. 81 * The data cache flush is now achieved using atomic clean / invalidates 82 * working outwards from L1 cache. This is done using Set/Way based cache 83 * maintainance instructions. 84 * The instruction cache can still be invalidated back to the point of 85 * unification in a single instruction. 86 * 87 */ 88ENTRY(v7_flush_kern_cache_all) 89 ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} ) 90 THUMB( stmfd sp!, {r4-r7, r9-r11, lr} ) 91 bl v7_flush_dcache_all 92 mov r0, #0 93 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 94 ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} ) 95 THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) 96 mov pc, lr 97ENDPROC(v7_flush_kern_cache_all) 98 99/* 100 * v7_flush_cache_all() 101 * 102 * Flush all TLB entries in a particular address space 103 * 104 * - mm - mm_struct describing address space 105 */ 106ENTRY(v7_flush_user_cache_all) 107 /*FALLTHROUGH*/ 108 109/* 110 * v7_flush_cache_range(start, end, flags) 111 * 112 * Flush a range of TLB entries in the specified address space. 113 * 114 * - start - start address (may not be aligned) 115 * - end - end address (exclusive, may not be aligned) 116 * - flags - vm_area_struct flags describing address space 117 * 118 * It is assumed that: 119 * - we have a VIPT cache. 120 */ 121ENTRY(v7_flush_user_cache_range) 122 mov pc, lr 123ENDPROC(v7_flush_user_cache_all) 124ENDPROC(v7_flush_user_cache_range) 125 126/* 127 * v7_coherent_kern_range(start,end) 128 * 129 * Ensure that the I and D caches are coherent within specified 130 * region. This is typically used when code has been written to 131 * a memory region, and will be executed. 132 * 133 * - start - virtual start address of region 134 * - end - virtual end address of region 135 * 136 * It is assumed that: 137 * - the Icache does not read data from the write buffer 138 */ 139ENTRY(v7_coherent_kern_range) 140 /* FALLTHROUGH */ 141 142/* 143 * v7_coherent_user_range(start,end) 144 * 145 * Ensure that the I and D caches are coherent within specified 146 * region. This is typically used when code has been written to 147 * a memory region, and will be executed. 148 * 149 * - start - virtual start address of region 150 * - end - virtual end address of region 151 * 152 * It is assumed that: 153 * - the Icache does not read data from the write buffer 154 */ 155ENTRY(v7_coherent_user_range) 156 dcache_line_size r2, r3 157 sub r3, r2, #1 158 bic r0, r0, r3 1591: mcr p15, 0, r0, c7, c11, 1 @ clean D line to the point of unification 160 dsb 161 mcr p15, 0, r0, c7, c5, 1 @ invalidate I line 162 add r0, r0, r2 163 cmp r0, r1 164 blo 1b 165 mov r0, #0 166 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB 167 dsb 168 isb 169 mov pc, lr 170ENDPROC(v7_coherent_kern_range) 171ENDPROC(v7_coherent_user_range) 172 173/* 174 * v7_flush_kern_dcache_page(kaddr) 175 * 176 * Ensure that the data held in the page kaddr is written back 177 * to the page in question. 178 * 179 * - kaddr - kernel address (guaranteed to be page aligned) 180 */ 181ENTRY(v7_flush_kern_dcache_page) 182 dcache_line_size r2, r3 183 add r1, r0, #PAGE_SZ 1841: 185 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line 186 add r0, r0, r2 187 cmp r0, r1 188 blo 1b 189 dsb 190 mov pc, lr 191ENDPROC(v7_flush_kern_dcache_page) 192 193/* 194 * v7_dma_inv_range(start,end) 195 * 196 * Invalidate the data cache within the specified region; we will 197 * be performing a DMA operation in this region and we want to 198 * purge old data in the cache. 199 * 200 * - start - virtual start address of region 201 * - end - virtual end address of region 202 */ 203ENTRY(v7_dma_inv_range) 204 dcache_line_size r2, r3 205 sub r3, r2, #1 206 tst r0, r3 207 bic r0, r0, r3 208 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 209 210 tst r1, r3 211 bic r1, r1, r3 212 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line 2131: 214 mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line 215 add r0, r0, r2 216 cmp r0, r1 217 blo 1b 218 dsb 219 mov pc, lr 220ENDPROC(v7_dma_inv_range) 221 222/* 223 * v7_dma_clean_range(start,end) 224 * - start - virtual start address of region 225 * - end - virtual end address of region 226 */ 227ENTRY(v7_dma_clean_range) 228 dcache_line_size r2, r3 229 sub r3, r2, #1 230 bic r0, r0, r3 2311: 232 mcr p15, 0, r0, c7, c10, 1 @ clean D / U line 233 add r0, r0, r2 234 cmp r0, r1 235 blo 1b 236 dsb 237 mov pc, lr 238ENDPROC(v7_dma_clean_range) 239 240/* 241 * v7_dma_flush_range(start,end) 242 * - start - virtual start address of region 243 * - end - virtual end address of region 244 */ 245ENTRY(v7_dma_flush_range) 246 dcache_line_size r2, r3 247 sub r3, r2, #1 248 bic r0, r0, r3 2491: 250 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 251 add r0, r0, r2 252 cmp r0, r1 253 blo 1b 254 dsb 255 mov pc, lr 256ENDPROC(v7_dma_flush_range) 257 258 __INITDATA 259 260 .type v7_cache_fns, #object 261ENTRY(v7_cache_fns) 262 .long v7_flush_kern_cache_all 263 .long v7_flush_user_cache_all 264 .long v7_flush_user_cache_range 265 .long v7_coherent_kern_range 266 .long v7_coherent_user_range 267 .long v7_flush_kern_dcache_page 268 .long v7_dma_inv_range 269 .long v7_dma_clean_range 270 .long v7_dma_flush_range 271 .size v7_cache_fns, . - v7_cache_fns 272