1/* 2 * linux/arch/arm/mm/cache-v7.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Copyright (C) 2005 ARM Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This is the "shell" of the ARMv7 processor support. 12 */ 13#include <linux/linkage.h> 14#include <linux/init.h> 15#include <asm/assembler.h> 16#include <asm/unwind.h> 17 18#include "proc-macros.S" 19 20/* 21 * v7_flush_icache_all() 22 * 23 * Flush the whole I-cache. 24 * 25 * Registers: 26 * r0 - set to 0 27 */ 28ENTRY(v7_flush_icache_all) 29 mov r0, #0 30 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable 31 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate 32 mov pc, lr 33ENDPROC(v7_flush_icache_all) 34 35/* 36 * v7_flush_dcache_all() 37 * 38 * Flush the whole D-cache. 39 * 40 * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) 41 * 42 * - mm - mm_struct describing address space 43 */ 44ENTRY(v7_flush_dcache_all) 45 dmb @ ensure ordering with previous memory accesses 46 mrc p15, 1, r0, c0, c0, 1 @ read clidr 47 ands r3, r0, #0x7000000 @ extract loc from clidr 48 mov r3, r3, lsr #23 @ left align loc bit field 49 beq finished @ if loc is 0, then no need to clean 50 mov r10, #0 @ start clean at cache level 0 51loop1: 52 add r2, r10, r10, lsr #1 @ work out 3x current cache level 53 mov r1, r0, lsr r2 @ extract cache type bits from clidr 54 and r1, r1, #7 @ mask of the bits for current cache only 55 cmp r1, #2 @ see what cache we have at this level 56 blt skip @ skip if no cache, or just i-cache 57 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 58 isb @ isb to sych the new cssr&csidr 59 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr 60 and r2, r1, #7 @ extract the length of the cache lines 61 add r2, r2, #4 @ add 4 (line length offset) 62 ldr r4, =0x3ff 63 ands r4, r4, r1, lsr #3 @ find maximum number on the way size 64 clz r5, r4 @ find bit position of way size increment 65 ldr r7, =0x7fff 66 ands r7, r7, r1, lsr #13 @ extract max number of the index size 67loop2: 68 mov r9, r4 @ create working copy of max way size 69loop3: 70 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11 71 THUMB( lsl r6, r9, r5 ) 72 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 73 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11 74 THUMB( lsl r6, r7, r2 ) 75 THUMB( orr r11, r11, r6 ) @ factor index number into r11 76 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 77 subs r9, r9, #1 @ decrement the way 78 bge loop3 79 subs r7, r7, #1 @ decrement the index 80 bge loop2 81skip: 82 add r10, r10, #2 @ increment cache number 83 cmp r3, r10 84 bgt loop1 85finished: 86 mov r10, #0 @ swith back to cache level 0 87 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 88 dsb 89 isb 90 mov pc, lr 91ENDPROC(v7_flush_dcache_all) 92 93/* 94 * v7_flush_cache_all() 95 * 96 * Flush the entire cache system. 97 * The data cache flush is now achieved using atomic clean / invalidates 98 * working outwards from L1 cache. This is done using Set/Way based cache 99 * maintainance instructions. 100 * The instruction cache can still be invalidated back to the point of 101 * unification in a single instruction. 102 * 103 */ 104ENTRY(v7_flush_kern_cache_all) 105 ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} ) 106 THUMB( stmfd sp!, {r4-r7, r9-r11, lr} ) 107 bl v7_flush_dcache_all 108 mov r0, #0 109 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable 110 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate 111 ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} ) 112 THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) 113 mov pc, lr 114ENDPROC(v7_flush_kern_cache_all) 115 116/* 117 * v7_flush_cache_all() 118 * 119 * Flush all TLB entries in a particular address space 120 * 121 * - mm - mm_struct describing address space 122 */ 123ENTRY(v7_flush_user_cache_all) 124 /*FALLTHROUGH*/ 125 126/* 127 * v7_flush_cache_range(start, end, flags) 128 * 129 * Flush a range of TLB entries in the specified address space. 130 * 131 * - start - start address (may not be aligned) 132 * - end - end address (exclusive, may not be aligned) 133 * - flags - vm_area_struct flags describing address space 134 * 135 * It is assumed that: 136 * - we have a VIPT cache. 137 */ 138ENTRY(v7_flush_user_cache_range) 139 mov pc, lr 140ENDPROC(v7_flush_user_cache_all) 141ENDPROC(v7_flush_user_cache_range) 142 143/* 144 * v7_coherent_kern_range(start,end) 145 * 146 * Ensure that the I and D caches are coherent within specified 147 * region. This is typically used when code has been written to 148 * a memory region, and will be executed. 149 * 150 * - start - virtual start address of region 151 * - end - virtual end address of region 152 * 153 * It is assumed that: 154 * - the Icache does not read data from the write buffer 155 */ 156ENTRY(v7_coherent_kern_range) 157 /* FALLTHROUGH */ 158 159/* 160 * v7_coherent_user_range(start,end) 161 * 162 * Ensure that the I and D caches are coherent within specified 163 * region. This is typically used when code has been written to 164 * a memory region, and will be executed. 165 * 166 * - start - virtual start address of region 167 * - end - virtual end address of region 168 * 169 * It is assumed that: 170 * - the Icache does not read data from the write buffer 171 */ 172ENTRY(v7_coherent_user_range) 173 UNWIND(.fnstart ) 174 dcache_line_size r2, r3 175 sub r3, r2, #1 176 bic r0, r0, r3 1771: 178 USER( mcr p15, 0, r0, c7, c11, 1 ) @ clean D line to the point of unification 179 dsb 180 USER( mcr p15, 0, r0, c7, c5, 1 ) @ invalidate I line 181 add r0, r0, r2 1822: 183 cmp r0, r1 184 blo 1b 185 mov r0, #0 186 ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable 187 ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB 188 dsb 189 isb 190 mov pc, lr 191 192/* 193 * Fault handling for the cache operation above. If the virtual address in r0 194 * isn't mapped, just try the next page. 195 */ 1969001: 197 mov r0, r0, lsr #12 198 mov r0, r0, lsl #12 199 add r0, r0, #4096 200 b 2b 201 UNWIND(.fnend ) 202ENDPROC(v7_coherent_kern_range) 203ENDPROC(v7_coherent_user_range) 204 205/* 206 * v7_flush_kern_dcache_area(void *addr, size_t size) 207 * 208 * Ensure that the data held in the page kaddr is written back 209 * to the page in question. 210 * 211 * - addr - kernel address 212 * - size - region size 213 */ 214ENTRY(v7_flush_kern_dcache_area) 215 dcache_line_size r2, r3 216 add r1, r0, r1 2171: 218 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line 219 add r0, r0, r2 220 cmp r0, r1 221 blo 1b 222 dsb 223 mov pc, lr 224ENDPROC(v7_flush_kern_dcache_area) 225 226/* 227 * v7_dma_inv_range(start,end) 228 * 229 * Invalidate the data cache within the specified region; we will 230 * be performing a DMA operation in this region and we want to 231 * purge old data in the cache. 232 * 233 * - start - virtual start address of region 234 * - end - virtual end address of region 235 */ 236v7_dma_inv_range: 237 dcache_line_size r2, r3 238 sub r3, r2, #1 239 tst r0, r3 240 bic r0, r0, r3 241 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 242 243 tst r1, r3 244 bic r1, r1, r3 245 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line 2461: 247 mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line 248 add r0, r0, r2 249 cmp r0, r1 250 blo 1b 251 dsb 252 mov pc, lr 253ENDPROC(v7_dma_inv_range) 254 255/* 256 * v7_dma_clean_range(start,end) 257 * - start - virtual start address of region 258 * - end - virtual end address of region 259 */ 260v7_dma_clean_range: 261 dcache_line_size r2, r3 262 sub r3, r2, #1 263 bic r0, r0, r3 2641: 265 mcr p15, 0, r0, c7, c10, 1 @ clean D / U line 266 add r0, r0, r2 267 cmp r0, r1 268 blo 1b 269 dsb 270 mov pc, lr 271ENDPROC(v7_dma_clean_range) 272 273/* 274 * v7_dma_flush_range(start,end) 275 * - start - virtual start address of region 276 * - end - virtual end address of region 277 */ 278ENTRY(v7_dma_flush_range) 279 dcache_line_size r2, r3 280 sub r3, r2, #1 281 bic r0, r0, r3 2821: 283 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 284 add r0, r0, r2 285 cmp r0, r1 286 blo 1b 287 dsb 288 mov pc, lr 289ENDPROC(v7_dma_flush_range) 290 291/* 292 * dma_map_area(start, size, dir) 293 * - start - kernel virtual start address 294 * - size - size of region 295 * - dir - DMA direction 296 */ 297ENTRY(v7_dma_map_area) 298 add r1, r1, r0 299 teq r2, #DMA_FROM_DEVICE 300 beq v7_dma_inv_range 301 b v7_dma_clean_range 302ENDPROC(v7_dma_map_area) 303 304/* 305 * dma_unmap_area(start, size, dir) 306 * - start - kernel virtual start address 307 * - size - size of region 308 * - dir - DMA direction 309 */ 310ENTRY(v7_dma_unmap_area) 311 add r1, r1, r0 312 teq r2, #DMA_TO_DEVICE 313 bne v7_dma_inv_range 314 mov pc, lr 315ENDPROC(v7_dma_unmap_area) 316 317 __INITDATA 318 319 .type v7_cache_fns, #object 320ENTRY(v7_cache_fns) 321 .long v7_flush_icache_all 322 .long v7_flush_kern_cache_all 323 .long v7_flush_user_cache_all 324 .long v7_flush_user_cache_range 325 .long v7_coherent_kern_range 326 .long v7_coherent_user_range 327 .long v7_flush_kern_dcache_area 328 .long v7_dma_map_area 329 .long v7_dma_unmap_area 330 .long v7_dma_flush_range 331 .size v7_cache_fns, . - v7_cache_fns 332