1/* 2 * linux/arch/arm/mm/cache-v7.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Copyright (C) 2005 ARM Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This is the "shell" of the ARMv7 processor support. 12 */ 13#include <linux/linkage.h> 14#include <linux/init.h> 15#include <asm/assembler.h> 16 17#include "proc-macros.S" 18 19/* 20 * v7_flush_dcache_all() 21 * 22 * Flush the whole D-cache. 23 * 24 * Corrupted registers: r0-r5, r7, r9-r11 25 * 26 * - mm - mm_struct describing address space 27 */ 28ENTRY(v7_flush_dcache_all) 29 mrc p15, 1, r0, c0, c0, 1 @ read clidr 30 ands r3, r0, #0x7000000 @ extract loc from clidr 31 mov r3, r3, lsr #23 @ left align loc bit field 32 beq finished @ if loc is 0, then no need to clean 33 mov r10, #0 @ start clean at cache level 0 34loop1: 35 add r2, r10, r10, lsr #1 @ work out 3x current cache level 36 mov r1, r0, lsr r2 @ extract cache type bits from clidr 37 and r1, r1, #7 @ mask of the bits for current cache only 38 cmp r1, #2 @ see what cache we have at this level 39 blt skip @ skip if no cache, or just i-cache 40 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 41 isb @ isb to sych the new cssr&csidr 42 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr 43 and r2, r1, #7 @ extract the length of the cache lines 44 add r2, r2, #4 @ add 4 (line length offset) 45 ldr r4, =0x3ff 46 ands r4, r4, r1, lsr #3 @ find maximum number on the way size 47 clz r5, r4 @ find bit position of way size increment 48 ldr r7, =0x7fff 49 ands r7, r7, r1, lsr #13 @ extract max number of the index size 50loop2: 51 mov r9, r4 @ create working copy of max way size 52loop3: 53 orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 54 orr r11, r11, r7, lsl r2 @ factor index number into r11 55 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 56 subs r9, r9, #1 @ decrement the way 57 bge loop3 58 subs r7, r7, #1 @ decrement the index 59 bge loop2 60skip: 61 add r10, r10, #2 @ increment cache number 62 cmp r3, r10 63 bgt loop1 64finished: 65 mov r10, #0 @ swith back to cache level 0 66 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 67 isb 68 mov pc, lr 69 70/* 71 * v7_flush_cache_all() 72 * 73 * Flush the entire cache system. 74 * The data cache flush is now achieved using atomic clean / invalidates 75 * working outwards from L1 cache. This is done using Set/Way based cache 76 * maintainance instructions. 77 * The instruction cache can still be invalidated back to the point of 78 * unification in a single instruction. 79 * 80 */ 81ENTRY(v7_flush_kern_cache_all) 82 stmfd sp!, {r4-r5, r7, r9-r11, lr} 83 bl v7_flush_dcache_all 84 mov r0, #0 85 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 86 ldmfd sp!, {r4-r5, r7, r9-r11, lr} 87 mov pc, lr 88 89/* 90 * v7_flush_cache_all() 91 * 92 * Flush all TLB entries in a particular address space 93 * 94 * - mm - mm_struct describing address space 95 */ 96ENTRY(v7_flush_user_cache_all) 97 /*FALLTHROUGH*/ 98 99/* 100 * v7_flush_cache_range(start, end, flags) 101 * 102 * Flush a range of TLB entries in the specified address space. 103 * 104 * - start - start address (may not be aligned) 105 * - end - end address (exclusive, may not be aligned) 106 * - flags - vm_area_struct flags describing address space 107 * 108 * It is assumed that: 109 * - we have a VIPT cache. 110 */ 111ENTRY(v7_flush_user_cache_range) 112 mov pc, lr 113 114/* 115 * v7_coherent_kern_range(start,end) 116 * 117 * Ensure that the I and D caches are coherent within specified 118 * region. This is typically used when code has been written to 119 * a memory region, and will be executed. 120 * 121 * - start - virtual start address of region 122 * - end - virtual end address of region 123 * 124 * It is assumed that: 125 * - the Icache does not read data from the write buffer 126 */ 127ENTRY(v7_coherent_kern_range) 128 /* FALLTHROUGH */ 129 130/* 131 * v7_coherent_user_range(start,end) 132 * 133 * Ensure that the I and D caches are coherent within specified 134 * region. This is typically used when code has been written to 135 * a memory region, and will be executed. 136 * 137 * - start - virtual start address of region 138 * - end - virtual end address of region 139 * 140 * It is assumed that: 141 * - the Icache does not read data from the write buffer 142 */ 143ENTRY(v7_coherent_user_range) 144 dcache_line_size r2, r3 145 sub r3, r2, #1 146 bic r0, r0, r3 1471: mcr p15, 0, r0, c7, c11, 1 @ clean D line to the point of unification 148 dsb 149 mcr p15, 0, r0, c7, c5, 1 @ invalidate I line 150 add r0, r0, r2 151 cmp r0, r1 152 blo 1b 153 mov r0, #0 154 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB 155 dsb 156 isb 157 mov pc, lr 158 159/* 160 * v7_flush_kern_dcache_page(kaddr) 161 * 162 * Ensure that the data held in the page kaddr is written back 163 * to the page in question. 164 * 165 * - kaddr - kernel address (guaranteed to be page aligned) 166 */ 167ENTRY(v7_flush_kern_dcache_page) 168 dcache_line_size r2, r3 169 add r1, r0, #PAGE_SZ 1701: 171 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line 172 add r0, r0, r2 173 cmp r0, r1 174 blo 1b 175 dsb 176 mov pc, lr 177 178/* 179 * v7_dma_inv_range(start,end) 180 * 181 * Invalidate the data cache within the specified region; we will 182 * be performing a DMA operation in this region and we want to 183 * purge old data in the cache. 184 * 185 * - start - virtual start address of region 186 * - end - virtual end address of region 187 */ 188ENTRY(v7_dma_inv_range) 189 dcache_line_size r2, r3 190 sub r3, r2, #1 191 tst r0, r3 192 bic r0, r0, r3 193 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 194 195 tst r1, r3 196 bic r1, r1, r3 197 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line 1981: 199 mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line 200 add r0, r0, r2 201 cmp r0, r1 202 blo 1b 203 dsb 204 mov pc, lr 205 206/* 207 * v7_dma_clean_range(start,end) 208 * - start - virtual start address of region 209 * - end - virtual end address of region 210 */ 211ENTRY(v7_dma_clean_range) 212 dcache_line_size r2, r3 213 sub r3, r2, #1 214 bic r0, r0, r3 2151: 216 mcr p15, 0, r0, c7, c10, 1 @ clean D / U line 217 add r0, r0, r2 218 cmp r0, r1 219 blo 1b 220 dsb 221 mov pc, lr 222 223/* 224 * v7_dma_flush_range(start,end) 225 * - start - virtual start address of region 226 * - end - virtual end address of region 227 */ 228ENTRY(v7_dma_flush_range) 229 dcache_line_size r2, r3 230 sub r3, r2, #1 231 bic r0, r0, r3 2321: 233 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 234 add r0, r0, r2 235 cmp r0, r1 236 blo 1b 237 dsb 238 mov pc, lr 239 240 __INITDATA 241 242 .type v7_cache_fns, #object 243ENTRY(v7_cache_fns) 244 .long v7_flush_kern_cache_all 245 .long v7_flush_user_cache_all 246 .long v7_flush_user_cache_range 247 .long v7_coherent_kern_range 248 .long v7_coherent_user_range 249 .long v7_flush_kern_dcache_page 250 .long v7_dma_inv_range 251 .long v7_dma_clean_range 252 .long v7_dma_flush_range 253 .size v7_cache_fns, . - v7_cache_fns 254