1bbe88886SCatalin Marinas/* 2bbe88886SCatalin Marinas * linux/arch/arm/mm/cache-v7.S 3bbe88886SCatalin Marinas * 4bbe88886SCatalin Marinas * Copyright (C) 2001 Deep Blue Solutions Ltd. 5bbe88886SCatalin Marinas * Copyright (C) 2005 ARM Ltd. 6bbe88886SCatalin Marinas * 7bbe88886SCatalin Marinas * This program is free software; you can redistribute it and/or modify 8bbe88886SCatalin Marinas * it under the terms of the GNU General Public License version 2 as 9bbe88886SCatalin Marinas * published by the Free Software Foundation. 10bbe88886SCatalin Marinas * 11bbe88886SCatalin Marinas * This is the "shell" of the ARMv7 processor support. 12bbe88886SCatalin Marinas */ 13bbe88886SCatalin Marinas#include <linux/linkage.h> 14bbe88886SCatalin Marinas#include <linux/init.h> 15bbe88886SCatalin Marinas#include <asm/assembler.h> 16bbe88886SCatalin Marinas 17bbe88886SCatalin Marinas#include "proc-macros.S" 18bbe88886SCatalin Marinas 19bbe88886SCatalin Marinas/* 20bbe88886SCatalin Marinas * v7_flush_dcache_all() 21bbe88886SCatalin Marinas * 22bbe88886SCatalin Marinas * Flush the whole D-cache. 23bbe88886SCatalin Marinas * 24bbe88886SCatalin Marinas * Corrupted registers: r0-r5, r7, r9-r11 25bbe88886SCatalin Marinas * 26bbe88886SCatalin Marinas * - mm - mm_struct describing address space 27bbe88886SCatalin Marinas */ 28bbe88886SCatalin MarinasENTRY(v7_flush_dcache_all) 29bbe88886SCatalin Marinas mrc p15, 1, r0, c0, c0, 1 @ read clidr 30bbe88886SCatalin Marinas ands r3, r0, #0x7000000 @ extract loc from clidr 31bbe88886SCatalin Marinas mov r3, r3, lsr #23 @ left align loc bit field 32bbe88886SCatalin Marinas beq finished @ if loc is 0, then no need to clean 33bbe88886SCatalin Marinas mov r10, #0 @ start clean at cache level 0 34bbe88886SCatalin Marinasloop1: 35bbe88886SCatalin Marinas add r2, r10, r10, lsr #1 @ work out 3x current cache level 36bbe88886SCatalin Marinas mov r1, r0, lsr r2 @ extract cache type bits from clidr 37bbe88886SCatalin Marinas and r1, r1, #7 @ mask of the bits for current cache only 38bbe88886SCatalin Marinas cmp r1, #2 @ see what cache we have at this level 39bbe88886SCatalin Marinas blt skip @ skip if no cache, or just i-cache 40bbe88886SCatalin Marinas mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 41bbe88886SCatalin Marinas isb @ isb to sych the new cssr&csidr 42bbe88886SCatalin Marinas mrc p15, 1, r1, c0, c0, 0 @ read the new csidr 43bbe88886SCatalin Marinas and r2, r1, #7 @ extract the length of the cache lines 44bbe88886SCatalin Marinas add r2, r2, #4 @ add 4 (line length offset) 45bbe88886SCatalin Marinas ldr r4, =0x3ff 46bbe88886SCatalin Marinas ands r4, r4, r1, lsr #3 @ find maximum number on the way size 47bbe88886SCatalin Marinas clz r5, r4 @ find bit position of way size increment 48bbe88886SCatalin Marinas ldr r7, =0x7fff 49bbe88886SCatalin Marinas ands r7, r7, r1, lsr #13 @ extract max number of the index size 50bbe88886SCatalin Marinasloop2: 51bbe88886SCatalin Marinas mov r9, r4 @ create working copy of max way size 52bbe88886SCatalin Marinasloop3: 53bbe88886SCatalin Marinas orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 54bbe88886SCatalin Marinas orr r11, r11, r7, lsl r2 @ factor index number into r11 55bbe88886SCatalin Marinas mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 56bbe88886SCatalin Marinas subs r9, r9, #1 @ decrement the way 57bbe88886SCatalin Marinas bge loop3 58bbe88886SCatalin Marinas subs r7, r7, #1 @ decrement the index 59bbe88886SCatalin Marinas bge loop2 60bbe88886SCatalin Marinasskip: 61bbe88886SCatalin Marinas add r10, r10, #2 @ increment cache number 62bbe88886SCatalin Marinas cmp r3, r10 63bbe88886SCatalin Marinas bgt loop1 64bbe88886SCatalin Marinasfinished: 65bbe88886SCatalin Marinas mov r10, #0 @ swith back to cache level 0 66bbe88886SCatalin Marinas mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 67bbe88886SCatalin Marinas isb 68bbe88886SCatalin Marinas mov pc, lr 69bbe88886SCatalin Marinas 70bbe88886SCatalin Marinas/* 71bbe88886SCatalin Marinas * v7_flush_cache_all() 72bbe88886SCatalin Marinas * 73bbe88886SCatalin Marinas * Flush the entire cache system. 74bbe88886SCatalin Marinas * The data cache flush is now achieved using atomic clean / invalidates 75bbe88886SCatalin Marinas * working outwards from L1 cache. This is done using Set/Way based cache 76bbe88886SCatalin Marinas * maintainance instructions. 77bbe88886SCatalin Marinas * The instruction cache can still be invalidated back to the point of 78bbe88886SCatalin Marinas * unification in a single instruction. 79bbe88886SCatalin Marinas * 80bbe88886SCatalin Marinas */ 81bbe88886SCatalin MarinasENTRY(v7_flush_kern_cache_all) 82bbe88886SCatalin Marinas stmfd sp!, {r4-r5, r7, r9-r11, lr} 83bbe88886SCatalin Marinas bl v7_flush_dcache_all 84bbe88886SCatalin Marinas mov r0, #0 85bbe88886SCatalin Marinas mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 86bbe88886SCatalin Marinas ldmfd sp!, {r4-r5, r7, r9-r11, lr} 87bbe88886SCatalin Marinas mov pc, lr 88bbe88886SCatalin Marinas 89bbe88886SCatalin Marinas/* 90bbe88886SCatalin Marinas * v7_flush_cache_all() 91bbe88886SCatalin Marinas * 92bbe88886SCatalin Marinas * Flush all TLB entries in a particular address space 93bbe88886SCatalin Marinas * 94bbe88886SCatalin Marinas * - mm - mm_struct describing address space 95bbe88886SCatalin Marinas */ 96bbe88886SCatalin MarinasENTRY(v7_flush_user_cache_all) 97bbe88886SCatalin Marinas /*FALLTHROUGH*/ 98bbe88886SCatalin Marinas 99bbe88886SCatalin Marinas/* 100bbe88886SCatalin Marinas * v7_flush_cache_range(start, end, flags) 101bbe88886SCatalin Marinas * 102bbe88886SCatalin Marinas * Flush a range of TLB entries in the specified address space. 103bbe88886SCatalin Marinas * 104bbe88886SCatalin Marinas * - start - start address (may not be aligned) 105bbe88886SCatalin Marinas * - end - end address (exclusive, may not be aligned) 106bbe88886SCatalin Marinas * - flags - vm_area_struct flags describing address space 107bbe88886SCatalin Marinas * 108bbe88886SCatalin Marinas * It is assumed that: 109bbe88886SCatalin Marinas * - we have a VIPT cache. 110bbe88886SCatalin Marinas */ 111bbe88886SCatalin MarinasENTRY(v7_flush_user_cache_range) 112bbe88886SCatalin Marinas mov pc, lr 113bbe88886SCatalin Marinas 114bbe88886SCatalin Marinas/* 115bbe88886SCatalin Marinas * v7_coherent_kern_range(start,end) 116bbe88886SCatalin Marinas * 117bbe88886SCatalin Marinas * Ensure that the I and D caches are coherent within specified 118bbe88886SCatalin Marinas * region. This is typically used when code has been written to 119bbe88886SCatalin Marinas * a memory region, and will be executed. 120bbe88886SCatalin Marinas * 121bbe88886SCatalin Marinas * - start - virtual start address of region 122bbe88886SCatalin Marinas * - end - virtual end address of region 123bbe88886SCatalin Marinas * 124bbe88886SCatalin Marinas * It is assumed that: 125bbe88886SCatalin Marinas * - the Icache does not read data from the write buffer 126bbe88886SCatalin Marinas */ 127bbe88886SCatalin MarinasENTRY(v7_coherent_kern_range) 128bbe88886SCatalin Marinas /* FALLTHROUGH */ 129bbe88886SCatalin Marinas 130bbe88886SCatalin Marinas/* 131bbe88886SCatalin Marinas * v7_coherent_user_range(start,end) 132bbe88886SCatalin Marinas * 133bbe88886SCatalin Marinas * Ensure that the I and D caches are coherent within specified 134bbe88886SCatalin Marinas * region. This is typically used when code has been written to 135bbe88886SCatalin Marinas * a memory region, and will be executed. 136bbe88886SCatalin Marinas * 137bbe88886SCatalin Marinas * - start - virtual start address of region 138bbe88886SCatalin Marinas * - end - virtual end address of region 139bbe88886SCatalin Marinas * 140bbe88886SCatalin Marinas * It is assumed that: 141bbe88886SCatalin Marinas * - the Icache does not read data from the write buffer 142bbe88886SCatalin Marinas */ 143bbe88886SCatalin MarinasENTRY(v7_coherent_user_range) 144bbe88886SCatalin Marinas dcache_line_size r2, r3 145bbe88886SCatalin Marinas sub r3, r2, #1 146bbe88886SCatalin Marinas bic r0, r0, r3 147bbe88886SCatalin Marinas1: mcr p15, 0, r0, c7, c11, 1 @ clean D line to the point of unification 148bbe88886SCatalin Marinas dsb 149bbe88886SCatalin Marinas mcr p15, 0, r0, c7, c5, 1 @ invalidate I line 150bbe88886SCatalin Marinas add r0, r0, r2 151bbe88886SCatalin Marinas cmp r0, r1 152bbe88886SCatalin Marinas blo 1b 153bbe88886SCatalin Marinas mov r0, #0 154bbe88886SCatalin Marinas mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB 155bbe88886SCatalin Marinas dsb 156bbe88886SCatalin Marinas isb 157bbe88886SCatalin Marinas mov pc, lr 158bbe88886SCatalin Marinas 159bbe88886SCatalin Marinas/* 160bbe88886SCatalin Marinas * v7_flush_kern_dcache_page(kaddr) 161bbe88886SCatalin Marinas * 162bbe88886SCatalin Marinas * Ensure that the data held in the page kaddr is written back 163bbe88886SCatalin Marinas * to the page in question. 164bbe88886SCatalin Marinas * 165bbe88886SCatalin Marinas * - kaddr - kernel address (guaranteed to be page aligned) 166bbe88886SCatalin Marinas */ 167bbe88886SCatalin MarinasENTRY(v7_flush_kern_dcache_page) 168bbe88886SCatalin Marinas dcache_line_size r2, r3 169bbe88886SCatalin Marinas add r1, r0, #PAGE_SZ 170bbe88886SCatalin Marinas1: 171bbe88886SCatalin Marinas mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line 172bbe88886SCatalin Marinas add r0, r0, r2 173bbe88886SCatalin Marinas cmp r0, r1 174bbe88886SCatalin Marinas blo 1b 175bbe88886SCatalin Marinas dsb 176bbe88886SCatalin Marinas mov pc, lr 177bbe88886SCatalin Marinas 178bbe88886SCatalin Marinas/* 179bbe88886SCatalin Marinas * v7_dma_inv_range(start,end) 180bbe88886SCatalin Marinas * 181bbe88886SCatalin Marinas * Invalidate the data cache within the specified region; we will 182bbe88886SCatalin Marinas * be performing a DMA operation in this region and we want to 183bbe88886SCatalin Marinas * purge old data in the cache. 184bbe88886SCatalin Marinas * 185bbe88886SCatalin Marinas * - start - virtual start address of region 186bbe88886SCatalin Marinas * - end - virtual end address of region 187bbe88886SCatalin Marinas */ 188bbe88886SCatalin MarinasENTRY(v7_dma_inv_range) 189bbe88886SCatalin Marinas dcache_line_size r2, r3 190bbe88886SCatalin Marinas sub r3, r2, #1 191bbe88886SCatalin Marinas tst r0, r3 192bbe88886SCatalin Marinas bic r0, r0, r3 193bbe88886SCatalin Marinas mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 194bbe88886SCatalin Marinas 195bbe88886SCatalin Marinas tst r1, r3 196bbe88886SCatalin Marinas bic r1, r1, r3 197bbe88886SCatalin Marinas mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line 198bbe88886SCatalin Marinas1: 199bbe88886SCatalin Marinas mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line 200bbe88886SCatalin Marinas add r0, r0, r2 201bbe88886SCatalin Marinas cmp r0, r1 202bbe88886SCatalin Marinas blo 1b 203bbe88886SCatalin Marinas dsb 204bbe88886SCatalin Marinas mov pc, lr 205bbe88886SCatalin Marinas 206bbe88886SCatalin Marinas/* 207bbe88886SCatalin Marinas * v7_dma_clean_range(start,end) 208bbe88886SCatalin Marinas * - start - virtual start address of region 209bbe88886SCatalin Marinas * - end - virtual end address of region 210bbe88886SCatalin Marinas */ 211bbe88886SCatalin MarinasENTRY(v7_dma_clean_range) 212bbe88886SCatalin Marinas dcache_line_size r2, r3 213bbe88886SCatalin Marinas sub r3, r2, #1 214bbe88886SCatalin Marinas bic r0, r0, r3 215bbe88886SCatalin Marinas1: 216bbe88886SCatalin Marinas mcr p15, 0, r0, c7, c10, 1 @ clean D / U line 217bbe88886SCatalin Marinas add r0, r0, r2 218bbe88886SCatalin Marinas cmp r0, r1 219bbe88886SCatalin Marinas blo 1b 220bbe88886SCatalin Marinas dsb 221bbe88886SCatalin Marinas mov pc, lr 222bbe88886SCatalin Marinas 223bbe88886SCatalin Marinas/* 224bbe88886SCatalin Marinas * v7_dma_flush_range(start,end) 225bbe88886SCatalin Marinas * - start - virtual start address of region 226bbe88886SCatalin Marinas * - end - virtual end address of region 227bbe88886SCatalin Marinas */ 228bbe88886SCatalin MarinasENTRY(v7_dma_flush_range) 229bbe88886SCatalin Marinas dcache_line_size r2, r3 230bbe88886SCatalin Marinas sub r3, r2, #1 231bbe88886SCatalin Marinas bic r0, r0, r3 232bbe88886SCatalin Marinas1: 233bbe88886SCatalin Marinas mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 234bbe88886SCatalin Marinas add r0, r0, r2 235bbe88886SCatalin Marinas cmp r0, r1 236bbe88886SCatalin Marinas blo 1b 237bbe88886SCatalin Marinas dsb 238bbe88886SCatalin Marinas mov pc, lr 239bbe88886SCatalin Marinas 240bbe88886SCatalin Marinas __INITDATA 241bbe88886SCatalin Marinas 242bbe88886SCatalin Marinas .type v7_cache_fns, #object 243bbe88886SCatalin MarinasENTRY(v7_cache_fns) 244bbe88886SCatalin Marinas .long v7_flush_kern_cache_all 245bbe88886SCatalin Marinas .long v7_flush_user_cache_all 246bbe88886SCatalin Marinas .long v7_flush_user_cache_range 247bbe88886SCatalin Marinas .long v7_coherent_kern_range 248bbe88886SCatalin Marinas .long v7_coherent_user_range 249bbe88886SCatalin Marinas .long v7_flush_kern_dcache_page 250bbe88886SCatalin Marinas .long v7_dma_inv_range 251bbe88886SCatalin Marinas .long v7_dma_clean_range 252bbe88886SCatalin Marinas .long v7_dma_flush_range 253bbe88886SCatalin Marinas .size v7_cache_fns, . - v7_cache_fns 254