1/* 2 * linux/arch/arm/mm/cache-v6.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This is the "shell" of the ARMv6 processor support. 11 */ 12#include <linux/linkage.h> 13#include <linux/init.h> 14#include <asm/assembler.h> 15 16#include "proc-macros.S" 17 18#define HARVARD_CACHE 19#define CACHE_LINE_SIZE 32 20#define D_CACHE_LINE_SIZE 32 21#define BTB_FLUSH_SIZE 8 22 23#ifdef CONFIG_ARM_ERRATA_411920 24/* 25 * Invalidate the entire I cache (this code is a workaround for the ARM1136 26 * erratum 411920 - Invalidate Instruction Cache operation can fail. This 27 * erratum is present in 1136, 1156 and 1176. It does not affect the MPCore. 28 * 29 * Registers: 30 * r0 - set to 0 31 * r1 - corrupted 32 */ 33ENTRY(v6_icache_inval_all) 34 mov r0, #0 35 mrs r1, cpsr 36 cpsid ifa @ disable interrupts 37 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 38 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 39 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 40 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 41 msr cpsr_cx, r1 @ restore interrupts 42 .rept 11 @ ARM Ltd recommends at least 43 nop @ 11 NOPs 44 .endr 45 mov pc, lr 46#endif 47 48/* 49 * v6_flush_cache_all() 50 * 51 * Flush the entire cache. 52 * 53 * It is assumed that: 54 */ 55ENTRY(v6_flush_kern_cache_all) 56 mov r0, #0 57#ifdef HARVARD_CACHE 58 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate 59#ifndef CONFIG_ARM_ERRATA_411920 60 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 61#else 62 b v6_icache_inval_all 63#endif 64#else 65 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate 66#endif 67 mov pc, lr 68 69/* 70 * v6_flush_cache_all() 71 * 72 * Flush all TLB entries in a particular address space 73 * 74 * - mm - mm_struct describing address space 75 */ 76ENTRY(v6_flush_user_cache_all) 77 /*FALLTHROUGH*/ 78 79/* 80 * v6_flush_cache_range(start, end, flags) 81 * 82 * Flush a range of TLB entries in the specified address space. 83 * 84 * - start - start address (may not be aligned) 85 * - end - end address (exclusive, may not be aligned) 86 * - flags - vm_area_struct flags describing address space 87 * 88 * It is assumed that: 89 * - we have a VIPT cache. 90 */ 91ENTRY(v6_flush_user_cache_range) 92 mov pc, lr 93 94/* 95 * v6_coherent_kern_range(start,end) 96 * 97 * Ensure that the I and D caches are coherent within specified 98 * region. This is typically used when code has been written to 99 * a memory region, and will be executed. 100 * 101 * - start - virtual start address of region 102 * - end - virtual end address of region 103 * 104 * It is assumed that: 105 * - the Icache does not read data from the write buffer 106 */ 107ENTRY(v6_coherent_kern_range) 108 /* FALLTHROUGH */ 109 110/* 111 * v6_coherent_user_range(start,end) 112 * 113 * Ensure that the I and D caches are coherent within specified 114 * region. This is typically used when code has been written to 115 * a memory region, and will be executed. 116 * 117 * - start - virtual start address of region 118 * - end - virtual end address of region 119 * 120 * It is assumed that: 121 * - the Icache does not read data from the write buffer 122 */ 123ENTRY(v6_coherent_user_range) 124 125#ifdef HARVARD_CACHE 126 bic r0, r0, #CACHE_LINE_SIZE - 1 1271: mcr p15, 0, r0, c7, c10, 1 @ clean D line 128 add r0, r0, #CACHE_LINE_SIZE 129 cmp r0, r1 130 blo 1b 131#endif 132 mov r0, #0 133#ifdef HARVARD_CACHE 134 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 135#ifndef CONFIG_ARM_ERRATA_411920 136 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 137#else 138 b v6_icache_inval_all 139#endif 140#else 141 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB 142#endif 143 mov pc, lr 144 145/* 146 * v6_flush_kern_dcache_page(kaddr) 147 * 148 * Ensure that the data held in the page kaddr is written back 149 * to the page in question. 150 * 151 * - kaddr - kernel address (guaranteed to be page aligned) 152 */ 153ENTRY(v6_flush_kern_dcache_page) 154 add r1, r0, #PAGE_SZ 1551: 156#ifdef HARVARD_CACHE 157 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line 158#else 159 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate unified line 160#endif 161 add r0, r0, #D_CACHE_LINE_SIZE 162 cmp r0, r1 163 blo 1b 164#ifdef HARVARD_CACHE 165 mov r0, #0 166 mcr p15, 0, r0, c7, c10, 4 167#endif 168 mov pc, lr 169 170 171/* 172 * v6_dma_inv_range(start,end) 173 * 174 * Invalidate the data cache within the specified region; we will 175 * be performing a DMA operation in this region and we want to 176 * purge old data in the cache. 177 * 178 * - start - virtual start address of region 179 * - end - virtual end address of region 180 */ 181ENTRY(v6_dma_inv_range) 182 tst r0, #D_CACHE_LINE_SIZE - 1 183 bic r0, r0, #D_CACHE_LINE_SIZE - 1 184#ifdef HARVARD_CACHE 185 mcrne p15, 0, r0, c7, c10, 1 @ clean D line 186#else 187 mcrne p15, 0, r0, c7, c11, 1 @ clean unified line 188#endif 189 tst r1, #D_CACHE_LINE_SIZE - 1 190 bic r1, r1, #D_CACHE_LINE_SIZE - 1 191#ifdef HARVARD_CACHE 192 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D line 193#else 194 mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line 195#endif 1961: 197#ifdef HARVARD_CACHE 198 mcr p15, 0, r0, c7, c6, 1 @ invalidate D line 199#else 200 mcr p15, 0, r0, c7, c7, 1 @ invalidate unified line 201#endif 202 add r0, r0, #D_CACHE_LINE_SIZE 203 cmp r0, r1 204 blo 1b 205 mov r0, #0 206 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 207 mov pc, lr 208 209/* 210 * v6_dma_clean_range(start,end) 211 * - start - virtual start address of region 212 * - end - virtual end address of region 213 */ 214ENTRY(v6_dma_clean_range) 215 bic r0, r0, #D_CACHE_LINE_SIZE - 1 2161: 217#ifdef HARVARD_CACHE 218 mcr p15, 0, r0, c7, c10, 1 @ clean D line 219#else 220 mcr p15, 0, r0, c7, c11, 1 @ clean unified line 221#endif 222 add r0, r0, #D_CACHE_LINE_SIZE 223 cmp r0, r1 224 blo 1b 225 mov r0, #0 226 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 227 mov pc, lr 228 229/* 230 * v6_dma_flush_range(start,end) 231 * - start - virtual start address of region 232 * - end - virtual end address of region 233 */ 234ENTRY(v6_dma_flush_range) 235 bic r0, r0, #D_CACHE_LINE_SIZE - 1 2361: 237#ifdef HARVARD_CACHE 238 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line 239#else 240 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate line 241#endif 242 add r0, r0, #D_CACHE_LINE_SIZE 243 cmp r0, r1 244 blo 1b 245 mov r0, #0 246 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 247 mov pc, lr 248 249 __INITDATA 250 251 .type v6_cache_fns, #object 252ENTRY(v6_cache_fns) 253 .long v6_flush_kern_cache_all 254 .long v6_flush_user_cache_all 255 .long v6_flush_user_cache_range 256 .long v6_coherent_kern_range 257 .long v6_coherent_user_range 258 .long v6_flush_kern_dcache_page 259 .long v6_dma_inv_range 260 .long v6_dma_clean_range 261 .long v6_dma_flush_range 262 .size v6_cache_fns, . - v6_cache_fns 263