xref: /openbmc/linux/arch/arm/mm/cache-v4.S (revision b627b4ed) 
1/*
2 *  linux/arch/arm/mm/cache-v4.S
3 *
4 *  Copyright (C) 1997-2002 Russell king
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <linux/init.h>
12#include <asm/page.h>
13#include "proc-macros.S"
14
15/*
16 *	flush_user_cache_all()
17 *
18 *	Invalidate all cache entries in a particular address
19 *	space.
20 *
21 *	- mm	- mm_struct describing address space
22 */
23ENTRY(v4_flush_user_cache_all)
24	/* FALLTHROUGH */
25/*
26 *	flush_kern_cache_all()
27 *
28 *	Clean and invalidate the entire cache.
29 */
30ENTRY(v4_flush_kern_cache_all)
31#ifdef CONFIG_CPU_CP15
32	mov	r0, #0
33	mcr	p15, 0, r0, c7, c7, 0		@ flush ID cache
34	mov	pc, lr
35#else
36	/* FALLTHROUGH */
37#endif
38
39/*
40 *	flush_user_cache_range(start, end, flags)
41 *
42 *	Invalidate a range of cache entries in the specified
43 *	address space.
44 *
45 *	- start - start address (may not be aligned)
46 *	- end	- end address (exclusive, may not be aligned)
47 *	- flags	- vma_area_struct flags describing address space
48 */
49ENTRY(v4_flush_user_cache_range)
50#ifdef CONFIG_CPU_CP15
51	mov	ip, #0
52	mcreq	p15, 0, ip, c7, c7, 0		@ flush ID cache
53	mov	pc, lr
54#else
55	/* FALLTHROUGH */
56#endif
57
58/*
59 *	coherent_kern_range(start, end)
60 *
61 *	Ensure coherency between the Icache and the Dcache in the
62 *	region described by start.  If you have non-snooping
63 *	Harvard caches, you need to implement this function.
64 *
65 *	- start  - virtual start address
66 *	- end	 - virtual end address
67 */
68ENTRY(v4_coherent_kern_range)
69	/* FALLTHROUGH */
70
71/*
72 *	coherent_user_range(start, end)
73 *
74 *	Ensure coherency between the Icache and the Dcache in the
75 *	region described by start.  If you have non-snooping
76 *	Harvard caches, you need to implement this function.
77 *
78 *	- start  - virtual start address
79 *	- end	 - virtual end address
80 */
81ENTRY(v4_coherent_user_range)
82	mov	pc, lr
83
84/*
85 *	flush_kern_dcache_page(void *page)
86 *
87 *	Ensure no D cache aliasing occurs, either with itself or
88 *	the I cache
89 *
90 *	- addr	- page aligned address
91 */
92ENTRY(v4_flush_kern_dcache_page)
93	/* FALLTHROUGH */
94
95/*
96 *	dma_inv_range(start, end)
97 *
98 *	Invalidate (discard) the specified virtual address range.
99 *	May not write back any entries.  If 'start' or 'end'
100 *	are not cache line aligned, those lines must be written
101 *	back.
102 *
103 *	- start  - virtual start address
104 *	- end	 - virtual end address
105 */
106ENTRY(v4_dma_inv_range)
107	/* FALLTHROUGH */
108
109/*
110 *	dma_flush_range(start, end)
111 *
112 *	Clean and invalidate the specified virtual address range.
113 *
114 *	- start  - virtual start address
115 *	- end	 - virtual end address
116 */
117ENTRY(v4_dma_flush_range)
118#ifdef CONFIG_CPU_CP15
119	mov	r0, #0
120	mcr	p15, 0, r0, c7, c7, 0		@ flush ID cache
121#endif
122	/* FALLTHROUGH */
123
124/*
125 *	dma_clean_range(start, end)
126 *
127 *	Clean (write back) the specified virtual address range.
128 *
129 *	- start  - virtual start address
130 *	- end	 - virtual end address
131 */
132ENTRY(v4_dma_clean_range)
133	mov	pc, lr
134
135	__INITDATA
136
137	.type	v4_cache_fns, #object
138ENTRY(v4_cache_fns)
139	.long	v4_flush_kern_cache_all
140	.long	v4_flush_user_cache_all
141	.long	v4_flush_user_cache_range
142	.long	v4_coherent_kern_range
143	.long	v4_coherent_user_range
144	.long	v4_flush_kern_dcache_page
145	.long	v4_dma_inv_range
146	.long	v4_dma_clean_range
147	.long	v4_dma_flush_range
148	.size	v4_cache_fns, . - v4_cache_fns
149