xref: /openbmc/linux/arch/arm/mm/cache-v4.S (revision a36954f5) 
1/*
2 *  linux/arch/arm/mm/cache-v4.S
3 *
4 *  Copyright (C) 1997-2002 Russell king
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <linux/init.h>
12#include <asm/assembler.h>
13#include <asm/page.h>
14#include "proc-macros.S"
15
16/*
17 *	flush_icache_all()
18 *
19 *	Unconditionally clean and invalidate the entire icache.
20 */
21ENTRY(v4_flush_icache_all)
22	ret	lr
23ENDPROC(v4_flush_icache_all)
24
25/*
26 *	flush_user_cache_all()
27 *
28 *	Invalidate all cache entries in a particular address
29 *	space.
30 *
31 *	- mm	- mm_struct describing address space
32 */
33ENTRY(v4_flush_user_cache_all)
34	/* FALLTHROUGH */
35/*
36 *	flush_kern_cache_all()
37 *
38 *	Clean and invalidate the entire cache.
39 */
40ENTRY(v4_flush_kern_cache_all)
41#ifdef CONFIG_CPU_CP15
42	mov	r0, #0
43	mcr	p15, 0, r0, c7, c7, 0		@ flush ID cache
44	ret	lr
45#else
46	/* FALLTHROUGH */
47#endif
48
49/*
50 *	flush_user_cache_range(start, end, flags)
51 *
52 *	Invalidate a range of cache entries in the specified
53 *	address space.
54 *
55 *	- start - start address (may not be aligned)
56 *	- end	- end address (exclusive, may not be aligned)
57 *	- flags	- vma_area_struct flags describing address space
58 */
59ENTRY(v4_flush_user_cache_range)
60#ifdef CONFIG_CPU_CP15
61	mov	ip, #0
62	mcr	p15, 0, ip, c7, c7, 0		@ flush ID cache
63	ret	lr
64#else
65	/* FALLTHROUGH */
66#endif
67
68/*
69 *	coherent_kern_range(start, end)
70 *
71 *	Ensure coherency between the Icache and the Dcache in the
72 *	region described by start.  If you have non-snooping
73 *	Harvard caches, you need to implement this function.
74 *
75 *	- start  - virtual start address
76 *	- end	 - virtual end address
77 */
78ENTRY(v4_coherent_kern_range)
79	/* FALLTHROUGH */
80
81/*
82 *	coherent_user_range(start, end)
83 *
84 *	Ensure coherency between the Icache and the Dcache in the
85 *	region described by start.  If you have non-snooping
86 *	Harvard caches, you need to implement this function.
87 *
88 *	- start  - virtual start address
89 *	- end	 - virtual end address
90 */
91ENTRY(v4_coherent_user_range)
92	mov	r0, #0
93	ret	lr
94
95/*
96 *	flush_kern_dcache_area(void *addr, size_t size)
97 *
98 *	Ensure no D cache aliasing occurs, either with itself or
99 *	the I cache
100 *
101 *	- addr	- kernel address
102 *	- size	- region size
103 */
104ENTRY(v4_flush_kern_dcache_area)
105	/* FALLTHROUGH */
106
107/*
108 *	dma_flush_range(start, end)
109 *
110 *	Clean and invalidate the specified virtual address range.
111 *
112 *	- start  - virtual start address
113 *	- end	 - virtual end address
114 */
115ENTRY(v4_dma_flush_range)
116#ifdef CONFIG_CPU_CP15
117	mov	r0, #0
118	mcr	p15, 0, r0, c7, c7, 0		@ flush ID cache
119#endif
120	ret	lr
121
122/*
123 *	dma_unmap_area(start, size, dir)
124 *	- start	- kernel virtual start address
125 *	- size	- size of region
126 *	- dir	- DMA direction
127 */
128ENTRY(v4_dma_unmap_area)
129	teq	r2, #DMA_TO_DEVICE
130	bne	v4_dma_flush_range
131	/* FALLTHROUGH */
132
133/*
134 *	dma_map_area(start, size, dir)
135 *	- start	- kernel virtual start address
136 *	- size	- size of region
137 *	- dir	- DMA direction
138 */
139ENTRY(v4_dma_map_area)
140	ret	lr
141ENDPROC(v4_dma_unmap_area)
142ENDPROC(v4_dma_map_area)
143
144	.globl	v4_flush_kern_cache_louis
145	.equ	v4_flush_kern_cache_louis, v4_flush_kern_cache_all
146
147	__INITDATA
148
149	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
150	define_cache_functions v4
151