xref: /openbmc/linux/arch/arm/mm/cache-tauros2.c (revision 95e9fd10) 
1 /*
2  * arch/arm/mm/cache-tauros2.c - Tauros2 L2 cache controller support
3  *
4  * Copyright (C) 2008 Marvell Semiconductor
5  *
6  * This file is licensed under the terms of the GNU General Public
7  * License version 2.  This program is licensed "as is" without any
8  * warranty of any kind, whether express or implied.
9  *
10  * References:
11  * - PJ1 CPU Core Datasheet,
12  *   Document ID MV-S104837-01, Rev 0.7, January 24 2008.
13  * - PJ4 CPU Core Datasheet,
14  *   Document ID MV-S105190-00, Rev 0.7, March 14 2008.
15  */
16 
17 #include <linux/init.h>
18 #include <asm/cacheflush.h>
19 #include <asm/cp15.h>
20 #include <asm/hardware/cache-tauros2.h>
21 
22 
23 /*
24  * When Tauros2 is used on a CPU that supports the v7 hierarchical
25  * cache operations, the cache handling code in proc-v7.S takes care
26  * of everything, including handling DMA coherency.
27  *
28  * So, we only need to register outer cache operations here if we're
29  * being used on a pre-v7 CPU, and we only need to build support for
30  * outer cache operations into the kernel image if the kernel has been
31  * configured to support a pre-v7 CPU.
32  */
33 #if __LINUX_ARM_ARCH__ < 7
34 /*
35  * Low-level cache maintenance operations.
36  */
37 static inline void tauros2_clean_pa(unsigned long addr)
38 {
39 	__asm__("mcr p15, 1, %0, c7, c11, 3" : : "r" (addr));
40 }
41 
42 static inline void tauros2_clean_inv_pa(unsigned long addr)
43 {
44 	__asm__("mcr p15, 1, %0, c7, c15, 3" : : "r" (addr));
45 }
46 
47 static inline void tauros2_inv_pa(unsigned long addr)
48 {
49 	__asm__("mcr p15, 1, %0, c7, c7, 3" : : "r" (addr));
50 }
51 
52 
53 /*
54  * Linux primitives.
55  *
56  * Note that the end addresses passed to Linux primitives are
57  * noninclusive.
58  */
59 #define CACHE_LINE_SIZE		32
60 
61 static void tauros2_inv_range(unsigned long start, unsigned long end)
62 {
63 	/*
64 	 * Clean and invalidate partial first cache line.
65 	 */
66 	if (start & (CACHE_LINE_SIZE - 1)) {
67 		tauros2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1));
68 		start = (start | (CACHE_LINE_SIZE - 1)) + 1;
69 	}
70 
71 	/*
72 	 * Clean and invalidate partial last cache line.
73 	 */
74 	if (end & (CACHE_LINE_SIZE - 1)) {
75 		tauros2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
76 		end &= ~(CACHE_LINE_SIZE - 1);
77 	}
78 
79 	/*
80 	 * Invalidate all full cache lines between 'start' and 'end'.
81 	 */
82 	while (start < end) {
83 		tauros2_inv_pa(start);
84 		start += CACHE_LINE_SIZE;
85 	}
86 
87 	dsb();
88 }
89 
90 static void tauros2_clean_range(unsigned long start, unsigned long end)
91 {
92 	start &= ~(CACHE_LINE_SIZE - 1);
93 	while (start < end) {
94 		tauros2_clean_pa(start);
95 		start += CACHE_LINE_SIZE;
96 	}
97 
98 	dsb();
99 }
100 
101 static void tauros2_flush_range(unsigned long start, unsigned long end)
102 {
103 	start &= ~(CACHE_LINE_SIZE - 1);
104 	while (start < end) {
105 		tauros2_clean_inv_pa(start);
106 		start += CACHE_LINE_SIZE;
107 	}
108 
109 	dsb();
110 }
111 
112 static void tauros2_disable(void)
113 {
114 	__asm__ __volatile__ (
115 	"mcr	p15, 1, %0, c7, c11, 0 @L2 Cache Clean All\n\t"
116 	"mrc	p15, 0, %0, c1, c0, 0\n\t"
117 	"bic	%0, %0, #(1 << 26)\n\t"
118 	"mcr	p15, 0, %0, c1, c0, 0  @Disable L2 Cache\n\t"
119 	: : "r" (0x0));
120 }
121 
122 static void tauros2_resume(void)
123 {
124 	__asm__ __volatile__ (
125 	"mcr	p15, 1, %0, c7, c7, 0 @L2 Cache Invalidate All\n\t"
126 	"mrc	p15, 0, %0, c1, c0, 0\n\t"
127 	"orr	%0, %0, #(1 << 26)\n\t"
128 	"mcr	p15, 0, %0, c1, c0, 0 @Enable L2 Cache\n\t"
129 	: : "r" (0x0));
130 }
131 #endif
132 
133 static inline u32 __init read_extra_features(void)
134 {
135 	u32 u;
136 
137 	__asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u));
138 
139 	return u;
140 }
141 
142 static inline void __init write_extra_features(u32 u)
143 {
144 	__asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u));
145 }
146 
147 static void __init disable_l2_prefetch(void)
148 {
149 	u32 u;
150 
151 	/*
152 	 * Read the CPU Extra Features register and verify that the
153 	 * Disable L2 Prefetch bit is set.
154 	 */
155 	u = read_extra_features();
156 	if (!(u & 0x01000000)) {
157 		printk(KERN_INFO "Tauros2: Disabling L2 prefetch.\n");
158 		write_extra_features(u | 0x01000000);
159 	}
160 }
161 
162 static inline int __init cpuid_scheme(void)
163 {
164 	extern int processor_id;
165 
166 	return !!((processor_id & 0x000f0000) == 0x000f0000);
167 }
168 
169 static inline u32 __init read_mmfr3(void)
170 {
171 	u32 mmfr3;
172 
173 	__asm__("mrc p15, 0, %0, c0, c1, 7\n" : "=r" (mmfr3));
174 
175 	return mmfr3;
176 }
177 
178 static inline u32 __init read_actlr(void)
179 {
180 	u32 actlr;
181 
182 	__asm__("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr));
183 
184 	return actlr;
185 }
186 
187 static inline void __init write_actlr(u32 actlr)
188 {
189 	__asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr));
190 }
191 
192 void __init tauros2_init(void)
193 {
194 	extern int processor_id;
195 	char *mode;
196 
197 	disable_l2_prefetch();
198 
199 #ifdef CONFIG_CPU_32v5
200 	if ((processor_id & 0xff0f0000) == 0x56050000) {
201 		u32 feat;
202 
203 		/*
204 		 * v5 CPUs with Tauros2 have the L2 cache enable bit
205 		 * located in the CPU Extra Features register.
206 		 */
207 		feat = read_extra_features();
208 		if (!(feat & 0x00400000)) {
209 			printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
210 			write_extra_features(feat | 0x00400000);
211 		}
212 
213 		mode = "ARMv5";
214 		outer_cache.inv_range = tauros2_inv_range;
215 		outer_cache.clean_range = tauros2_clean_range;
216 		outer_cache.flush_range = tauros2_flush_range;
217 		outer_cache.disable = tauros2_disable;
218 		outer_cache.resume = tauros2_resume;
219 	}
220 #endif
221 
222 #ifdef CONFIG_CPU_32v6
223 	/*
224 	 * Check whether this CPU lacks support for the v7 hierarchical
225 	 * cache ops.  (PJ4 is in its v6 personality mode if the MMFR3
226 	 * register indicates no support for the v7 hierarchical cache
227 	 * ops.)
228 	 */
229 	if (cpuid_scheme() && (read_mmfr3() & 0xf) == 0) {
230 		/*
231 		 * When Tauros2 is used in an ARMv6 system, the L2
232 		 * enable bit is in the ARMv6 ARM-mandated position
233 		 * (bit [26] of the System Control Register).
234 		 */
235 		if (!(get_cr() & 0x04000000)) {
236 			printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
237 			adjust_cr(0x04000000, 0x04000000);
238 		}
239 
240 		mode = "ARMv6";
241 		outer_cache.inv_range = tauros2_inv_range;
242 		outer_cache.clean_range = tauros2_clean_range;
243 		outer_cache.flush_range = tauros2_flush_range;
244 		outer_cache.disable = tauros2_disable;
245 		outer_cache.resume = tauros2_resume;
246 	}
247 #endif
248 
249 #ifdef CONFIG_CPU_32v7
250 	/*
251 	 * Check whether this CPU has support for the v7 hierarchical
252 	 * cache ops.  (PJ4 is in its v7 personality mode if the MMFR3
253 	 * register indicates support for the v7 hierarchical cache
254 	 * ops.)
255 	 *
256 	 * (Although strictly speaking there may exist CPUs that
257 	 * implement the v7 cache ops but are only ARMv6 CPUs (due to
258 	 * not complying with all of the other ARMv7 requirements),
259 	 * there are no real-life examples of Tauros2 being used on
260 	 * such CPUs as of yet.)
261 	 */
262 	if (cpuid_scheme() && (read_mmfr3() & 0xf) == 1) {
263 		u32 actlr;
264 
265 		/*
266 		 * When Tauros2 is used in an ARMv7 system, the L2
267 		 * enable bit is located in the Auxiliary System Control
268 		 * Register (which is the only register allowed by the
269 		 * ARMv7 spec to contain fine-grained cache control bits).
270 		 */
271 		actlr = read_actlr();
272 		if (!(actlr & 0x00000002)) {
273 			printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
274 			write_actlr(actlr | 0x00000002);
275 		}
276 
277 		mode = "ARMv7";
278 	}
279 #endif
280 
281 	if (mode == NULL) {
282 		printk(KERN_CRIT "Tauros2: Unable to detect CPU mode.\n");
283 		return;
284 	}
285 
286 	printk(KERN_INFO "Tauros2: L2 cache support initialised "
287 			 "in %s mode.\n", mode);
288 }
289