1 /* 2 * arch/arm/mm/cache-l2x0.c - L210/L220/L310 cache controller support 3 * 4 * Copyright (C) 2007 ARM Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 #include <linux/cpu.h> 20 #include <linux/err.h> 21 #include <linux/init.h> 22 #include <linux/smp.h> 23 #include <linux/spinlock.h> 24 #include <linux/log2.h> 25 #include <linux/io.h> 26 #include <linux/of.h> 27 #include <linux/of_address.h> 28 29 #include <asm/cacheflush.h> 30 #include <asm/cp15.h> 31 #include <asm/cputype.h> 32 #include <asm/hardware/cache-l2x0.h> 33 #include "cache-tauros3.h" 34 #include "cache-aurora-l2.h" 35 36 struct l2c_init_data { 37 const char *type; 38 unsigned way_size_0; 39 unsigned num_lock; 40 void (*of_parse)(const struct device_node *, u32 *, u32 *); 41 void (*enable)(void __iomem *, u32, unsigned); 42 void (*fixup)(void __iomem *, u32, struct outer_cache_fns *); 43 void (*save)(void __iomem *); 44 void (*configure)(void __iomem *); 45 void (*unlock)(void __iomem *, unsigned); 46 struct outer_cache_fns outer_cache; 47 }; 48 49 #define CACHE_LINE_SIZE 32 50 51 static void __iomem *l2x0_base; 52 static const struct l2c_init_data *l2x0_data; 53 static DEFINE_RAW_SPINLOCK(l2x0_lock); 54 static u32 l2x0_way_mask; /* Bitmask of active ways */ 55 static u32 l2x0_size; 56 static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; 57 58 struct l2x0_regs l2x0_saved_regs; 59 60 /* 61 * Common code for all cache controllers. 62 */ 63 static inline void l2c_wait_mask(void __iomem *reg, unsigned long mask) 64 { 65 /* wait for cache operation by line or way to complete */ 66 while (readl_relaxed(reg) & mask) 67 cpu_relax(); 68 } 69 70 /* 71 * By default, we write directly to secure registers. Platforms must 72 * override this if they are running non-secure. 73 */ 74 static void l2c_write_sec(unsigned long val, void __iomem *base, unsigned reg) 75 { 76 if (val == readl_relaxed(base + reg)) 77 return; 78 if (outer_cache.write_sec) 79 outer_cache.write_sec(val, reg); 80 else 81 writel_relaxed(val, base + reg); 82 } 83 84 /* 85 * This should only be called when we have a requirement that the 86 * register be written due to a work-around, as platforms running 87 * in non-secure mode may not be able to access this register. 88 */ 89 static inline void l2c_set_debug(void __iomem *base, unsigned long val) 90 { 91 l2c_write_sec(val, base, L2X0_DEBUG_CTRL); 92 } 93 94 static void __l2c_op_way(void __iomem *reg) 95 { 96 writel_relaxed(l2x0_way_mask, reg); 97 l2c_wait_mask(reg, l2x0_way_mask); 98 } 99 100 static inline void l2c_unlock(void __iomem *base, unsigned num) 101 { 102 unsigned i; 103 104 for (i = 0; i < num; i++) { 105 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE + 106 i * L2X0_LOCKDOWN_STRIDE); 107 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE + 108 i * L2X0_LOCKDOWN_STRIDE); 109 } 110 } 111 112 static void l2c_configure(void __iomem *base) 113 { 114 l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL); 115 } 116 117 /* 118 * Enable the L2 cache controller. This function must only be 119 * called when the cache controller is known to be disabled. 120 */ 121 static void l2c_enable(void __iomem *base, u32 aux, unsigned num_lock) 122 { 123 unsigned long flags; 124 125 l2x0_saved_regs.aux_ctrl = aux; 126 127 if (outer_cache.configure) 128 outer_cache.configure(&l2x0_saved_regs); 129 else 130 l2x0_data->configure(base); 131 132 l2x0_data->unlock(base, num_lock); 133 134 local_irq_save(flags); 135 __l2c_op_way(base + L2X0_INV_WAY); 136 writel_relaxed(0, base + sync_reg_offset); 137 l2c_wait_mask(base + sync_reg_offset, 1); 138 local_irq_restore(flags); 139 140 l2c_write_sec(L2X0_CTRL_EN, base, L2X0_CTRL); 141 } 142 143 static void l2c_disable(void) 144 { 145 void __iomem *base = l2x0_base; 146 147 outer_cache.flush_all(); 148 l2c_write_sec(0, base, L2X0_CTRL); 149 dsb(st); 150 } 151 152 static void l2c_save(void __iomem *base) 153 { 154 l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); 155 } 156 157 static void l2c_resume(void) 158 { 159 void __iomem *base = l2x0_base; 160 161 /* Do not touch the controller if already enabled. */ 162 if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) 163 l2c_enable(base, l2x0_saved_regs.aux_ctrl, l2x0_data->num_lock); 164 } 165 166 /* 167 * L2C-210 specific code. 168 * 169 * The L2C-2x0 PA, set/way and sync operations are atomic, but we must 170 * ensure that no background operation is running. The way operations 171 * are all background tasks. 172 * 173 * While a background operation is in progress, any new operation is 174 * ignored (unspecified whether this causes an error.) Thankfully, not 175 * used on SMP. 176 * 177 * Never has a different sync register other than L2X0_CACHE_SYNC, but 178 * we use sync_reg_offset here so we can share some of this with L2C-310. 179 */ 180 static void __l2c210_cache_sync(void __iomem *base) 181 { 182 writel_relaxed(0, base + sync_reg_offset); 183 } 184 185 static void __l2c210_op_pa_range(void __iomem *reg, unsigned long start, 186 unsigned long end) 187 { 188 while (start < end) { 189 writel_relaxed(start, reg); 190 start += CACHE_LINE_SIZE; 191 } 192 } 193 194 static void l2c210_inv_range(unsigned long start, unsigned long end) 195 { 196 void __iomem *base = l2x0_base; 197 198 if (start & (CACHE_LINE_SIZE - 1)) { 199 start &= ~(CACHE_LINE_SIZE - 1); 200 writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA); 201 start += CACHE_LINE_SIZE; 202 } 203 204 if (end & (CACHE_LINE_SIZE - 1)) { 205 end &= ~(CACHE_LINE_SIZE - 1); 206 writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA); 207 } 208 209 __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end); 210 __l2c210_cache_sync(base); 211 } 212 213 static void l2c210_clean_range(unsigned long start, unsigned long end) 214 { 215 void __iomem *base = l2x0_base; 216 217 start &= ~(CACHE_LINE_SIZE - 1); 218 __l2c210_op_pa_range(base + L2X0_CLEAN_LINE_PA, start, end); 219 __l2c210_cache_sync(base); 220 } 221 222 static void l2c210_flush_range(unsigned long start, unsigned long end) 223 { 224 void __iomem *base = l2x0_base; 225 226 start &= ~(CACHE_LINE_SIZE - 1); 227 __l2c210_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA, start, end); 228 __l2c210_cache_sync(base); 229 } 230 231 static void l2c210_flush_all(void) 232 { 233 void __iomem *base = l2x0_base; 234 235 BUG_ON(!irqs_disabled()); 236 237 __l2c_op_way(base + L2X0_CLEAN_INV_WAY); 238 __l2c210_cache_sync(base); 239 } 240 241 static void l2c210_sync(void) 242 { 243 __l2c210_cache_sync(l2x0_base); 244 } 245 246 static const struct l2c_init_data l2c210_data __initconst = { 247 .type = "L2C-210", 248 .way_size_0 = SZ_8K, 249 .num_lock = 1, 250 .enable = l2c_enable, 251 .save = l2c_save, 252 .configure = l2c_configure, 253 .unlock = l2c_unlock, 254 .outer_cache = { 255 .inv_range = l2c210_inv_range, 256 .clean_range = l2c210_clean_range, 257 .flush_range = l2c210_flush_range, 258 .flush_all = l2c210_flush_all, 259 .disable = l2c_disable, 260 .sync = l2c210_sync, 261 .resume = l2c_resume, 262 }, 263 }; 264 265 /* 266 * L2C-220 specific code. 267 * 268 * All operations are background operations: they have to be waited for. 269 * Conflicting requests generate a slave error (which will cause an 270 * imprecise abort.) Never uses sync_reg_offset, so we hard-code the 271 * sync register here. 272 * 273 * However, we can re-use the l2c210_resume call. 274 */ 275 static inline void __l2c220_cache_sync(void __iomem *base) 276 { 277 writel_relaxed(0, base + L2X0_CACHE_SYNC); 278 l2c_wait_mask(base + L2X0_CACHE_SYNC, 1); 279 } 280 281 static void l2c220_op_way(void __iomem *base, unsigned reg) 282 { 283 unsigned long flags; 284 285 raw_spin_lock_irqsave(&l2x0_lock, flags); 286 __l2c_op_way(base + reg); 287 __l2c220_cache_sync(base); 288 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 289 } 290 291 static unsigned long l2c220_op_pa_range(void __iomem *reg, unsigned long start, 292 unsigned long end, unsigned long flags) 293 { 294 raw_spinlock_t *lock = &l2x0_lock; 295 296 while (start < end) { 297 unsigned long blk_end = start + min(end - start, 4096UL); 298 299 while (start < blk_end) { 300 l2c_wait_mask(reg, 1); 301 writel_relaxed(start, reg); 302 start += CACHE_LINE_SIZE; 303 } 304 305 if (blk_end < end) { 306 raw_spin_unlock_irqrestore(lock, flags); 307 raw_spin_lock_irqsave(lock, flags); 308 } 309 } 310 311 return flags; 312 } 313 314 static void l2c220_inv_range(unsigned long start, unsigned long end) 315 { 316 void __iomem *base = l2x0_base; 317 unsigned long flags; 318 319 raw_spin_lock_irqsave(&l2x0_lock, flags); 320 if ((start | end) & (CACHE_LINE_SIZE - 1)) { 321 if (start & (CACHE_LINE_SIZE - 1)) { 322 start &= ~(CACHE_LINE_SIZE - 1); 323 writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA); 324 start += CACHE_LINE_SIZE; 325 } 326 327 if (end & (CACHE_LINE_SIZE - 1)) { 328 end &= ~(CACHE_LINE_SIZE - 1); 329 l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1); 330 writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA); 331 } 332 } 333 334 flags = l2c220_op_pa_range(base + L2X0_INV_LINE_PA, 335 start, end, flags); 336 l2c_wait_mask(base + L2X0_INV_LINE_PA, 1); 337 __l2c220_cache_sync(base); 338 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 339 } 340 341 static void l2c220_clean_range(unsigned long start, unsigned long end) 342 { 343 void __iomem *base = l2x0_base; 344 unsigned long flags; 345 346 start &= ~(CACHE_LINE_SIZE - 1); 347 if ((end - start) >= l2x0_size) { 348 l2c220_op_way(base, L2X0_CLEAN_WAY); 349 return; 350 } 351 352 raw_spin_lock_irqsave(&l2x0_lock, flags); 353 flags = l2c220_op_pa_range(base + L2X0_CLEAN_LINE_PA, 354 start, end, flags); 355 l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1); 356 __l2c220_cache_sync(base); 357 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 358 } 359 360 static void l2c220_flush_range(unsigned long start, unsigned long end) 361 { 362 void __iomem *base = l2x0_base; 363 unsigned long flags; 364 365 start &= ~(CACHE_LINE_SIZE - 1); 366 if ((end - start) >= l2x0_size) { 367 l2c220_op_way(base, L2X0_CLEAN_INV_WAY); 368 return; 369 } 370 371 raw_spin_lock_irqsave(&l2x0_lock, flags); 372 flags = l2c220_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA, 373 start, end, flags); 374 l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1); 375 __l2c220_cache_sync(base); 376 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 377 } 378 379 static void l2c220_flush_all(void) 380 { 381 l2c220_op_way(l2x0_base, L2X0_CLEAN_INV_WAY); 382 } 383 384 static void l2c220_sync(void) 385 { 386 unsigned long flags; 387 388 raw_spin_lock_irqsave(&l2x0_lock, flags); 389 __l2c220_cache_sync(l2x0_base); 390 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 391 } 392 393 static void l2c220_enable(void __iomem *base, u32 aux, unsigned num_lock) 394 { 395 /* 396 * Always enable non-secure access to the lockdown registers - 397 * we write to them as part of the L2C enable sequence so they 398 * need to be accessible. 399 */ 400 aux |= L220_AUX_CTRL_NS_LOCKDOWN; 401 402 l2c_enable(base, aux, num_lock); 403 } 404 405 static void l2c220_unlock(void __iomem *base, unsigned num_lock) 406 { 407 if (readl_relaxed(base + L2X0_AUX_CTRL) & L220_AUX_CTRL_NS_LOCKDOWN) 408 l2c_unlock(base, num_lock); 409 } 410 411 static const struct l2c_init_data l2c220_data = { 412 .type = "L2C-220", 413 .way_size_0 = SZ_8K, 414 .num_lock = 1, 415 .enable = l2c220_enable, 416 .save = l2c_save, 417 .configure = l2c_configure, 418 .unlock = l2c220_unlock, 419 .outer_cache = { 420 .inv_range = l2c220_inv_range, 421 .clean_range = l2c220_clean_range, 422 .flush_range = l2c220_flush_range, 423 .flush_all = l2c220_flush_all, 424 .disable = l2c_disable, 425 .sync = l2c220_sync, 426 .resume = l2c_resume, 427 }, 428 }; 429 430 /* 431 * L2C-310 specific code. 432 * 433 * Very similar to L2C-210, the PA, set/way and sync operations are atomic, 434 * and the way operations are all background tasks. However, issuing an 435 * operation while a background operation is in progress results in a 436 * SLVERR response. We can reuse: 437 * 438 * __l2c210_cache_sync (using sync_reg_offset) 439 * l2c210_sync 440 * l2c210_inv_range (if 588369 is not applicable) 441 * l2c210_clean_range 442 * l2c210_flush_range (if 588369 is not applicable) 443 * l2c210_flush_all (if 727915 is not applicable) 444 * 445 * Errata: 446 * 588369: PL310 R0P0->R1P0, fixed R2P0. 447 * Affects: all clean+invalidate operations 448 * clean and invalidate skips the invalidate step, so we need to issue 449 * separate operations. We also require the above debug workaround 450 * enclosing this code fragment on affected parts. On unaffected parts, 451 * we must not use this workaround without the debug register writes 452 * to avoid exposing a problem similar to 727915. 453 * 454 * 727915: PL310 R2P0->R3P0, fixed R3P1. 455 * Affects: clean+invalidate by way 456 * clean and invalidate by way runs in the background, and a store can 457 * hit the line between the clean operation and invalidate operation, 458 * resulting in the store being lost. 459 * 460 * 752271: PL310 R3P0->R3P1-50REL0, fixed R3P2. 461 * Affects: 8x64-bit (double fill) line fetches 462 * double fill line fetches can fail to cause dirty data to be evicted 463 * from the cache before the new data overwrites the second line. 464 * 465 * 753970: PL310 R3P0, fixed R3P1. 466 * Affects: sync 467 * prevents merging writes after the sync operation, until another L2C 468 * operation is performed (or a number of other conditions.) 469 * 470 * 769419: PL310 R0P0->R3P1, fixed R3P2. 471 * Affects: store buffer 472 * store buffer is not automatically drained. 473 */ 474 static void l2c310_inv_range_erratum(unsigned long start, unsigned long end) 475 { 476 void __iomem *base = l2x0_base; 477 478 if ((start | end) & (CACHE_LINE_SIZE - 1)) { 479 unsigned long flags; 480 481 /* Erratum 588369 for both clean+invalidate operations */ 482 raw_spin_lock_irqsave(&l2x0_lock, flags); 483 l2c_set_debug(base, 0x03); 484 485 if (start & (CACHE_LINE_SIZE - 1)) { 486 start &= ~(CACHE_LINE_SIZE - 1); 487 writel_relaxed(start, base + L2X0_CLEAN_LINE_PA); 488 writel_relaxed(start, base + L2X0_INV_LINE_PA); 489 start += CACHE_LINE_SIZE; 490 } 491 492 if (end & (CACHE_LINE_SIZE - 1)) { 493 end &= ~(CACHE_LINE_SIZE - 1); 494 writel_relaxed(end, base + L2X0_CLEAN_LINE_PA); 495 writel_relaxed(end, base + L2X0_INV_LINE_PA); 496 } 497 498 l2c_set_debug(base, 0x00); 499 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 500 } 501 502 __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end); 503 __l2c210_cache_sync(base); 504 } 505 506 static void l2c310_flush_range_erratum(unsigned long start, unsigned long end) 507 { 508 raw_spinlock_t *lock = &l2x0_lock; 509 unsigned long flags; 510 void __iomem *base = l2x0_base; 511 512 raw_spin_lock_irqsave(lock, flags); 513 while (start < end) { 514 unsigned long blk_end = start + min(end - start, 4096UL); 515 516 l2c_set_debug(base, 0x03); 517 while (start < blk_end) { 518 writel_relaxed(start, base + L2X0_CLEAN_LINE_PA); 519 writel_relaxed(start, base + L2X0_INV_LINE_PA); 520 start += CACHE_LINE_SIZE; 521 } 522 l2c_set_debug(base, 0x00); 523 524 if (blk_end < end) { 525 raw_spin_unlock_irqrestore(lock, flags); 526 raw_spin_lock_irqsave(lock, flags); 527 } 528 } 529 raw_spin_unlock_irqrestore(lock, flags); 530 __l2c210_cache_sync(base); 531 } 532 533 static void l2c310_flush_all_erratum(void) 534 { 535 void __iomem *base = l2x0_base; 536 unsigned long flags; 537 538 raw_spin_lock_irqsave(&l2x0_lock, flags); 539 l2c_set_debug(base, 0x03); 540 __l2c_op_way(base + L2X0_CLEAN_INV_WAY); 541 l2c_set_debug(base, 0x00); 542 __l2c210_cache_sync(base); 543 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 544 } 545 546 static void __init l2c310_save(void __iomem *base) 547 { 548 unsigned revision; 549 550 l2c_save(base); 551 552 l2x0_saved_regs.tag_latency = readl_relaxed(base + 553 L310_TAG_LATENCY_CTRL); 554 l2x0_saved_regs.data_latency = readl_relaxed(base + 555 L310_DATA_LATENCY_CTRL); 556 l2x0_saved_regs.filter_end = readl_relaxed(base + 557 L310_ADDR_FILTER_END); 558 l2x0_saved_regs.filter_start = readl_relaxed(base + 559 L310_ADDR_FILTER_START); 560 561 revision = readl_relaxed(base + L2X0_CACHE_ID) & 562 L2X0_CACHE_ID_RTL_MASK; 563 564 /* From r2p0, there is Prefetch offset/control register */ 565 if (revision >= L310_CACHE_ID_RTL_R2P0) 566 l2x0_saved_regs.prefetch_ctrl = readl_relaxed(base + 567 L310_PREFETCH_CTRL); 568 569 /* From r3p0, there is Power control register */ 570 if (revision >= L310_CACHE_ID_RTL_R3P0) 571 l2x0_saved_regs.pwr_ctrl = readl_relaxed(base + 572 L310_POWER_CTRL); 573 } 574 575 static void l2c310_configure(void __iomem *base) 576 { 577 unsigned revision; 578 579 l2c_configure(base); 580 581 /* restore pl310 setup */ 582 l2c_write_sec(l2x0_saved_regs.tag_latency, base, 583 L310_TAG_LATENCY_CTRL); 584 l2c_write_sec(l2x0_saved_regs.data_latency, base, 585 L310_DATA_LATENCY_CTRL); 586 l2c_write_sec(l2x0_saved_regs.filter_end, base, 587 L310_ADDR_FILTER_END); 588 l2c_write_sec(l2x0_saved_regs.filter_start, base, 589 L310_ADDR_FILTER_START); 590 591 revision = readl_relaxed(base + L2X0_CACHE_ID) & 592 L2X0_CACHE_ID_RTL_MASK; 593 594 if (revision >= L310_CACHE_ID_RTL_R2P0) 595 l2c_write_sec(l2x0_saved_regs.prefetch_ctrl, base, 596 L310_PREFETCH_CTRL); 597 if (revision >= L310_CACHE_ID_RTL_R3P0) 598 l2c_write_sec(l2x0_saved_regs.pwr_ctrl, base, 599 L310_POWER_CTRL); 600 } 601 602 static int l2c310_cpu_enable_flz(struct notifier_block *nb, unsigned long act, void *data) 603 { 604 switch (act & ~CPU_TASKS_FROZEN) { 605 case CPU_STARTING: 606 set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1)); 607 break; 608 case CPU_DYING: 609 set_auxcr(get_auxcr() & ~(BIT(3) | BIT(2) | BIT(1))); 610 break; 611 } 612 return NOTIFY_OK; 613 } 614 615 static void __init l2c310_enable(void __iomem *base, u32 aux, unsigned num_lock) 616 { 617 unsigned rev = readl_relaxed(base + L2X0_CACHE_ID) & L2X0_CACHE_ID_RTL_MASK; 618 bool cortex_a9 = read_cpuid_part() == ARM_CPU_PART_CORTEX_A9; 619 620 if (rev >= L310_CACHE_ID_RTL_R2P0) { 621 if (cortex_a9) { 622 aux |= L310_AUX_CTRL_EARLY_BRESP; 623 pr_info("L2C-310 enabling early BRESP for Cortex-A9\n"); 624 } else if (aux & L310_AUX_CTRL_EARLY_BRESP) { 625 pr_warn("L2C-310 early BRESP only supported with Cortex-A9\n"); 626 aux &= ~L310_AUX_CTRL_EARLY_BRESP; 627 } 628 } 629 630 if (cortex_a9) { 631 u32 aux_cur = readl_relaxed(base + L2X0_AUX_CTRL); 632 u32 acr = get_auxcr(); 633 634 pr_debug("Cortex-A9 ACR=0x%08x\n", acr); 635 636 if (acr & BIT(3) && !(aux_cur & L310_AUX_CTRL_FULL_LINE_ZERO)) 637 pr_err("L2C-310: full line of zeros enabled in Cortex-A9 but not L2C-310 - invalid\n"); 638 639 if (aux & L310_AUX_CTRL_FULL_LINE_ZERO && !(acr & BIT(3))) 640 pr_err("L2C-310: enabling full line of zeros but not enabled in Cortex-A9\n"); 641 642 if (!(aux & L310_AUX_CTRL_FULL_LINE_ZERO) && !outer_cache.write_sec) { 643 aux |= L310_AUX_CTRL_FULL_LINE_ZERO; 644 pr_info("L2C-310 full line of zeros enabled for Cortex-A9\n"); 645 } 646 } else if (aux & (L310_AUX_CTRL_FULL_LINE_ZERO | L310_AUX_CTRL_EARLY_BRESP)) { 647 pr_err("L2C-310: disabling Cortex-A9 specific feature bits\n"); 648 aux &= ~(L310_AUX_CTRL_FULL_LINE_ZERO | L310_AUX_CTRL_EARLY_BRESP); 649 } 650 651 /* r3p0 or later has power control register */ 652 if (rev >= L310_CACHE_ID_RTL_R3P0) 653 l2x0_saved_regs.pwr_ctrl = L310_DYNAMIC_CLK_GATING_EN | 654 L310_STNDBY_MODE_EN; 655 656 /* 657 * Always enable non-secure access to the lockdown registers - 658 * we write to them as part of the L2C enable sequence so they 659 * need to be accessible. 660 */ 661 aux |= L310_AUX_CTRL_NS_LOCKDOWN; 662 663 l2c_enable(base, aux, num_lock); 664 665 /* Read back resulting AUX_CTRL value as it could have been altered. */ 666 aux = readl_relaxed(base + L2X0_AUX_CTRL); 667 668 if (aux & (L310_AUX_CTRL_DATA_PREFETCH | L310_AUX_CTRL_INSTR_PREFETCH)) { 669 u32 prefetch = readl_relaxed(base + L310_PREFETCH_CTRL); 670 671 pr_info("L2C-310 %s%s prefetch enabled, offset %u lines\n", 672 aux & L310_AUX_CTRL_INSTR_PREFETCH ? "I" : "", 673 aux & L310_AUX_CTRL_DATA_PREFETCH ? "D" : "", 674 1 + (prefetch & L310_PREFETCH_CTRL_OFFSET_MASK)); 675 } 676 677 /* r3p0 or later has power control register */ 678 if (rev >= L310_CACHE_ID_RTL_R3P0) { 679 u32 power_ctrl; 680 681 power_ctrl = readl_relaxed(base + L310_POWER_CTRL); 682 pr_info("L2C-310 dynamic clock gating %sabled, standby mode %sabled\n", 683 power_ctrl & L310_DYNAMIC_CLK_GATING_EN ? "en" : "dis", 684 power_ctrl & L310_STNDBY_MODE_EN ? "en" : "dis"); 685 } 686 687 if (aux & L310_AUX_CTRL_FULL_LINE_ZERO) { 688 set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1)); 689 cpu_notifier(l2c310_cpu_enable_flz, 0); 690 } 691 } 692 693 static void __init l2c310_fixup(void __iomem *base, u32 cache_id, 694 struct outer_cache_fns *fns) 695 { 696 unsigned revision = cache_id & L2X0_CACHE_ID_RTL_MASK; 697 const char *errata[8]; 698 unsigned n = 0; 699 700 if (IS_ENABLED(CONFIG_PL310_ERRATA_588369) && 701 revision < L310_CACHE_ID_RTL_R2P0 && 702 /* For bcm compatibility */ 703 fns->inv_range == l2c210_inv_range) { 704 fns->inv_range = l2c310_inv_range_erratum; 705 fns->flush_range = l2c310_flush_range_erratum; 706 errata[n++] = "588369"; 707 } 708 709 if (IS_ENABLED(CONFIG_PL310_ERRATA_727915) && 710 revision >= L310_CACHE_ID_RTL_R2P0 && 711 revision < L310_CACHE_ID_RTL_R3P1) { 712 fns->flush_all = l2c310_flush_all_erratum; 713 errata[n++] = "727915"; 714 } 715 716 if (revision >= L310_CACHE_ID_RTL_R3P0 && 717 revision < L310_CACHE_ID_RTL_R3P2) { 718 u32 val = l2x0_saved_regs.prefetch_ctrl; 719 /* I don't think bit23 is required here... but iMX6 does so */ 720 if (val & (BIT(30) | BIT(23))) { 721 val &= ~(BIT(30) | BIT(23)); 722 l2x0_saved_regs.prefetch_ctrl = val; 723 errata[n++] = "752271"; 724 } 725 } 726 727 if (IS_ENABLED(CONFIG_PL310_ERRATA_753970) && 728 revision == L310_CACHE_ID_RTL_R3P0) { 729 sync_reg_offset = L2X0_DUMMY_REG; 730 errata[n++] = "753970"; 731 } 732 733 if (IS_ENABLED(CONFIG_PL310_ERRATA_769419)) 734 errata[n++] = "769419"; 735 736 if (n) { 737 unsigned i; 738 739 pr_info("L2C-310 errat%s", n > 1 ? "a" : "um"); 740 for (i = 0; i < n; i++) 741 pr_cont(" %s", errata[i]); 742 pr_cont(" enabled\n"); 743 } 744 } 745 746 static void l2c310_disable(void) 747 { 748 /* 749 * If full-line-of-zeros is enabled, we must first disable it in the 750 * Cortex-A9 auxiliary control register before disabling the L2 cache. 751 */ 752 if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_FULL_LINE_ZERO) 753 set_auxcr(get_auxcr() & ~(BIT(3) | BIT(2) | BIT(1))); 754 755 l2c_disable(); 756 } 757 758 static void l2c310_resume(void) 759 { 760 l2c_resume(); 761 762 /* Re-enable full-line-of-zeros for Cortex-A9 */ 763 if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_FULL_LINE_ZERO) 764 set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1)); 765 } 766 767 static void l2c310_unlock(void __iomem *base, unsigned num_lock) 768 { 769 if (readl_relaxed(base + L2X0_AUX_CTRL) & L310_AUX_CTRL_NS_LOCKDOWN) 770 l2c_unlock(base, num_lock); 771 } 772 773 static const struct l2c_init_data l2c310_init_fns __initconst = { 774 .type = "L2C-310", 775 .way_size_0 = SZ_8K, 776 .num_lock = 8, 777 .enable = l2c310_enable, 778 .fixup = l2c310_fixup, 779 .save = l2c310_save, 780 .configure = l2c310_configure, 781 .unlock = l2c310_unlock, 782 .outer_cache = { 783 .inv_range = l2c210_inv_range, 784 .clean_range = l2c210_clean_range, 785 .flush_range = l2c210_flush_range, 786 .flush_all = l2c210_flush_all, 787 .disable = l2c310_disable, 788 .sync = l2c210_sync, 789 .resume = l2c310_resume, 790 }, 791 }; 792 793 static int __init __l2c_init(const struct l2c_init_data *data, 794 u32 aux_val, u32 aux_mask, u32 cache_id) 795 { 796 struct outer_cache_fns fns; 797 unsigned way_size_bits, ways; 798 u32 aux, old_aux; 799 800 /* 801 * Save the pointer globally so that callbacks which do not receive 802 * context from callers can access the structure. 803 */ 804 l2x0_data = kmemdup(data, sizeof(*data), GFP_KERNEL); 805 if (!l2x0_data) 806 return -ENOMEM; 807 808 /* 809 * Sanity check the aux values. aux_mask is the bits we preserve 810 * from reading the hardware register, and aux_val is the bits we 811 * set. 812 */ 813 if (aux_val & aux_mask) 814 pr_alert("L2C: platform provided aux values permit register corruption.\n"); 815 816 old_aux = aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); 817 aux &= aux_mask; 818 aux |= aux_val; 819 820 if (old_aux != aux) 821 pr_warn("L2C: DT/platform modifies aux control register: 0x%08x -> 0x%08x\n", 822 old_aux, aux); 823 824 /* Determine the number of ways */ 825 switch (cache_id & L2X0_CACHE_ID_PART_MASK) { 826 case L2X0_CACHE_ID_PART_L310: 827 if ((aux_val | ~aux_mask) & (L2C_AUX_CTRL_WAY_SIZE_MASK | L310_AUX_CTRL_ASSOCIATIVITY_16)) 828 pr_warn("L2C: DT/platform tries to modify or specify cache size\n"); 829 if (aux & (1 << 16)) 830 ways = 16; 831 else 832 ways = 8; 833 break; 834 835 case L2X0_CACHE_ID_PART_L210: 836 case L2X0_CACHE_ID_PART_L220: 837 ways = (aux >> 13) & 0xf; 838 break; 839 840 case AURORA_CACHE_ID: 841 ways = (aux >> 13) & 0xf; 842 ways = 2 << ((ways + 1) >> 2); 843 break; 844 845 default: 846 /* Assume unknown chips have 8 ways */ 847 ways = 8; 848 break; 849 } 850 851 l2x0_way_mask = (1 << ways) - 1; 852 853 /* 854 * way_size_0 is the size that a way_size value of zero would be 855 * given the calculation: way_size = way_size_0 << way_size_bits. 856 * So, if way_size_bits=0 is reserved, but way_size_bits=1 is 16k, 857 * then way_size_0 would be 8k. 858 * 859 * L2 cache size = number of ways * way size. 860 */ 861 way_size_bits = (aux & L2C_AUX_CTRL_WAY_SIZE_MASK) >> 862 L2C_AUX_CTRL_WAY_SIZE_SHIFT; 863 l2x0_size = ways * (data->way_size_0 << way_size_bits); 864 865 fns = data->outer_cache; 866 fns.write_sec = outer_cache.write_sec; 867 fns.configure = outer_cache.configure; 868 if (data->fixup) 869 data->fixup(l2x0_base, cache_id, &fns); 870 871 /* 872 * Check if l2x0 controller is already enabled. If we are booting 873 * in non-secure mode accessing the below registers will fault. 874 */ 875 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) 876 data->enable(l2x0_base, aux, data->num_lock); 877 878 outer_cache = fns; 879 880 /* 881 * It is strange to save the register state before initialisation, 882 * but hey, this is what the DT implementations decided to do. 883 */ 884 if (data->save) 885 data->save(l2x0_base); 886 887 /* Re-read it in case some bits are reserved. */ 888 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); 889 890 pr_info("%s cache controller enabled, %d ways, %d kB\n", 891 data->type, ways, l2x0_size >> 10); 892 pr_info("%s: CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n", 893 data->type, cache_id, aux); 894 895 return 0; 896 } 897 898 void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) 899 { 900 const struct l2c_init_data *data; 901 u32 cache_id; 902 903 l2x0_base = base; 904 905 cache_id = readl_relaxed(base + L2X0_CACHE_ID); 906 907 switch (cache_id & L2X0_CACHE_ID_PART_MASK) { 908 default: 909 case L2X0_CACHE_ID_PART_L210: 910 data = &l2c210_data; 911 break; 912 913 case L2X0_CACHE_ID_PART_L220: 914 data = &l2c220_data; 915 break; 916 917 case L2X0_CACHE_ID_PART_L310: 918 data = &l2c310_init_fns; 919 break; 920 } 921 922 /* Read back current (default) hardware configuration */ 923 if (data->save) 924 data->save(l2x0_base); 925 926 __l2c_init(data, aux_val, aux_mask, cache_id); 927 } 928 929 #ifdef CONFIG_OF 930 static int l2_wt_override; 931 932 /* Aurora don't have the cache ID register available, so we have to 933 * pass it though the device tree */ 934 static u32 cache_id_part_number_from_dt; 935 936 /** 937 * l2x0_cache_size_of_parse() - read cache size parameters from DT 938 * @np: the device tree node for the l2 cache 939 * @aux_val: pointer to machine-supplied auxilary register value, to 940 * be augmented by the call (bits to be set to 1) 941 * @aux_mask: pointer to machine-supplied auxilary register mask, to 942 * be augmented by the call (bits to be set to 0) 943 * @associativity: variable to return the calculated associativity in 944 * @max_way_size: the maximum size in bytes for the cache ways 945 */ 946 static int __init l2x0_cache_size_of_parse(const struct device_node *np, 947 u32 *aux_val, u32 *aux_mask, 948 u32 *associativity, 949 u32 max_way_size) 950 { 951 u32 mask = 0, val = 0; 952 u32 cache_size = 0, sets = 0; 953 u32 way_size_bits = 1; 954 u32 way_size = 0; 955 u32 block_size = 0; 956 u32 line_size = 0; 957 958 of_property_read_u32(np, "cache-size", &cache_size); 959 of_property_read_u32(np, "cache-sets", &sets); 960 of_property_read_u32(np, "cache-block-size", &block_size); 961 of_property_read_u32(np, "cache-line-size", &line_size); 962 963 if (!cache_size || !sets) 964 return -ENODEV; 965 966 /* All these l2 caches have the same line = block size actually */ 967 if (!line_size) { 968 if (block_size) { 969 /* If linesize is not given, it is equal to blocksize */ 970 line_size = block_size; 971 } else { 972 /* Fall back to known size */ 973 pr_warn("L2C OF: no cache block/line size given: " 974 "falling back to default size %d bytes\n", 975 CACHE_LINE_SIZE); 976 line_size = CACHE_LINE_SIZE; 977 } 978 } 979 980 if (line_size != CACHE_LINE_SIZE) 981 pr_warn("L2C OF: DT supplied line size %d bytes does " 982 "not match hardware line size of %d bytes\n", 983 line_size, 984 CACHE_LINE_SIZE); 985 986 /* 987 * Since: 988 * set size = cache size / sets 989 * ways = cache size / (sets * line size) 990 * way size = cache size / (cache size / (sets * line size)) 991 * way size = sets * line size 992 * associativity = ways = cache size / way size 993 */ 994 way_size = sets * line_size; 995 *associativity = cache_size / way_size; 996 997 if (way_size > max_way_size) { 998 pr_err("L2C OF: set size %dKB is too large\n", way_size); 999 return -EINVAL; 1000 } 1001 1002 pr_info("L2C OF: override cache size: %d bytes (%dKB)\n", 1003 cache_size, cache_size >> 10); 1004 pr_info("L2C OF: override line size: %d bytes\n", line_size); 1005 pr_info("L2C OF: override way size: %d bytes (%dKB)\n", 1006 way_size, way_size >> 10); 1007 pr_info("L2C OF: override associativity: %d\n", *associativity); 1008 1009 /* 1010 * Calculates the bits 17:19 to set for way size: 1011 * 512KB -> 6, 256KB -> 5, ... 16KB -> 1 1012 */ 1013 way_size_bits = ilog2(way_size >> 10) - 3; 1014 if (way_size_bits < 1 || way_size_bits > 6) { 1015 pr_err("L2C OF: cache way size illegal: %dKB is not mapped\n", 1016 way_size); 1017 return -EINVAL; 1018 } 1019 1020 mask |= L2C_AUX_CTRL_WAY_SIZE_MASK; 1021 val |= (way_size_bits << L2C_AUX_CTRL_WAY_SIZE_SHIFT); 1022 1023 *aux_val &= ~mask; 1024 *aux_val |= val; 1025 *aux_mask &= ~mask; 1026 1027 return 0; 1028 } 1029 1030 static void __init l2x0_of_parse(const struct device_node *np, 1031 u32 *aux_val, u32 *aux_mask) 1032 { 1033 u32 data[2] = { 0, 0 }; 1034 u32 tag = 0; 1035 u32 dirty = 0; 1036 u32 val = 0, mask = 0; 1037 u32 assoc; 1038 int ret; 1039 1040 of_property_read_u32(np, "arm,tag-latency", &tag); 1041 if (tag) { 1042 mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK; 1043 val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT; 1044 } 1045 1046 of_property_read_u32_array(np, "arm,data-latency", 1047 data, ARRAY_SIZE(data)); 1048 if (data[0] && data[1]) { 1049 mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK | 1050 L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK; 1051 val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) | 1052 ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT); 1053 } 1054 1055 of_property_read_u32(np, "arm,dirty-latency", &dirty); 1056 if (dirty) { 1057 mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK; 1058 val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT; 1059 } 1060 1061 ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_256K); 1062 if (ret) 1063 return; 1064 1065 if (assoc > 8) { 1066 pr_err("l2x0 of: cache setting yield too high associativity\n"); 1067 pr_err("l2x0 of: %d calculated, max 8\n", assoc); 1068 } else { 1069 mask |= L2X0_AUX_CTRL_ASSOC_MASK; 1070 val |= (assoc << L2X0_AUX_CTRL_ASSOC_SHIFT); 1071 } 1072 1073 *aux_val &= ~mask; 1074 *aux_val |= val; 1075 *aux_mask &= ~mask; 1076 } 1077 1078 static const struct l2c_init_data of_l2c210_data __initconst = { 1079 .type = "L2C-210", 1080 .way_size_0 = SZ_8K, 1081 .num_lock = 1, 1082 .of_parse = l2x0_of_parse, 1083 .enable = l2c_enable, 1084 .save = l2c_save, 1085 .configure = l2c_configure, 1086 .unlock = l2c_unlock, 1087 .outer_cache = { 1088 .inv_range = l2c210_inv_range, 1089 .clean_range = l2c210_clean_range, 1090 .flush_range = l2c210_flush_range, 1091 .flush_all = l2c210_flush_all, 1092 .disable = l2c_disable, 1093 .sync = l2c210_sync, 1094 .resume = l2c_resume, 1095 }, 1096 }; 1097 1098 static const struct l2c_init_data of_l2c220_data __initconst = { 1099 .type = "L2C-220", 1100 .way_size_0 = SZ_8K, 1101 .num_lock = 1, 1102 .of_parse = l2x0_of_parse, 1103 .enable = l2c220_enable, 1104 .save = l2c_save, 1105 .configure = l2c_configure, 1106 .unlock = l2c220_unlock, 1107 .outer_cache = { 1108 .inv_range = l2c220_inv_range, 1109 .clean_range = l2c220_clean_range, 1110 .flush_range = l2c220_flush_range, 1111 .flush_all = l2c220_flush_all, 1112 .disable = l2c_disable, 1113 .sync = l2c220_sync, 1114 .resume = l2c_resume, 1115 }, 1116 }; 1117 1118 static void __init l2c310_of_parse(const struct device_node *np, 1119 u32 *aux_val, u32 *aux_mask) 1120 { 1121 u32 data[3] = { 0, 0, 0 }; 1122 u32 tag[3] = { 0, 0, 0 }; 1123 u32 filter[2] = { 0, 0 }; 1124 u32 assoc; 1125 u32 prefetch; 1126 u32 val; 1127 int ret; 1128 1129 of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag)); 1130 if (tag[0] && tag[1] && tag[2]) 1131 l2x0_saved_regs.tag_latency = 1132 L310_LATENCY_CTRL_RD(tag[0] - 1) | 1133 L310_LATENCY_CTRL_WR(tag[1] - 1) | 1134 L310_LATENCY_CTRL_SETUP(tag[2] - 1); 1135 1136 of_property_read_u32_array(np, "arm,data-latency", 1137 data, ARRAY_SIZE(data)); 1138 if (data[0] && data[1] && data[2]) 1139 l2x0_saved_regs.data_latency = 1140 L310_LATENCY_CTRL_RD(data[0] - 1) | 1141 L310_LATENCY_CTRL_WR(data[1] - 1) | 1142 L310_LATENCY_CTRL_SETUP(data[2] - 1); 1143 1144 of_property_read_u32_array(np, "arm,filter-ranges", 1145 filter, ARRAY_SIZE(filter)); 1146 if (filter[1]) { 1147 l2x0_saved_regs.filter_end = 1148 ALIGN(filter[0] + filter[1], SZ_1M); 1149 l2x0_saved_regs.filter_start = (filter[0] & ~(SZ_1M - 1)) 1150 | L310_ADDR_FILTER_EN; 1151 } 1152 1153 ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_512K); 1154 if (!ret) { 1155 switch (assoc) { 1156 case 16: 1157 *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK; 1158 *aux_val |= L310_AUX_CTRL_ASSOCIATIVITY_16; 1159 *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK; 1160 break; 1161 case 8: 1162 *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK; 1163 *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK; 1164 break; 1165 default: 1166 pr_err("L2C-310 OF cache associativity %d invalid, only 8 or 16 permitted\n", 1167 assoc); 1168 break; 1169 } 1170 } 1171 1172 prefetch = l2x0_saved_regs.prefetch_ctrl; 1173 1174 ret = of_property_read_u32(np, "arm,double-linefill", &val); 1175 if (ret == 0) { 1176 if (val) 1177 prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL; 1178 else 1179 prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL; 1180 } else if (ret != -EINVAL) { 1181 pr_err("L2C-310 OF arm,double-linefill property value is missing\n"); 1182 } 1183 1184 ret = of_property_read_u32(np, "arm,double-linefill-incr", &val); 1185 if (ret == 0) { 1186 if (val) 1187 prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_INCR; 1188 else 1189 prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL_INCR; 1190 } else if (ret != -EINVAL) { 1191 pr_err("L2C-310 OF arm,double-linefill-incr property value is missing\n"); 1192 } 1193 1194 ret = of_property_read_u32(np, "arm,double-linefill-wrap", &val); 1195 if (ret == 0) { 1196 if (!val) 1197 prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP; 1198 else 1199 prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP; 1200 } else if (ret != -EINVAL) { 1201 pr_err("L2C-310 OF arm,double-linefill-wrap property value is missing\n"); 1202 } 1203 1204 ret = of_property_read_u32(np, "arm,prefetch-drop", &val); 1205 if (ret == 0) { 1206 if (val) 1207 prefetch |= L310_PREFETCH_CTRL_PREFETCH_DROP; 1208 else 1209 prefetch &= ~L310_PREFETCH_CTRL_PREFETCH_DROP; 1210 } else if (ret != -EINVAL) { 1211 pr_err("L2C-310 OF arm,prefetch-drop property value is missing\n"); 1212 } 1213 1214 ret = of_property_read_u32(np, "arm,prefetch-offset", &val); 1215 if (ret == 0) { 1216 prefetch &= ~L310_PREFETCH_CTRL_OFFSET_MASK; 1217 prefetch |= val & L310_PREFETCH_CTRL_OFFSET_MASK; 1218 } else if (ret != -EINVAL) { 1219 pr_err("L2C-310 OF arm,prefetch-offset property value is missing\n"); 1220 } 1221 1222 l2x0_saved_regs.prefetch_ctrl = prefetch; 1223 } 1224 1225 static const struct l2c_init_data of_l2c310_data __initconst = { 1226 .type = "L2C-310", 1227 .way_size_0 = SZ_8K, 1228 .num_lock = 8, 1229 .of_parse = l2c310_of_parse, 1230 .enable = l2c310_enable, 1231 .fixup = l2c310_fixup, 1232 .save = l2c310_save, 1233 .configure = l2c310_configure, 1234 .unlock = l2c310_unlock, 1235 .outer_cache = { 1236 .inv_range = l2c210_inv_range, 1237 .clean_range = l2c210_clean_range, 1238 .flush_range = l2c210_flush_range, 1239 .flush_all = l2c210_flush_all, 1240 .disable = l2c310_disable, 1241 .sync = l2c210_sync, 1242 .resume = l2c310_resume, 1243 }, 1244 }; 1245 1246 /* 1247 * This is a variant of the of_l2c310_data with .sync set to 1248 * NULL. Outer sync operations are not needed when the system is I/O 1249 * coherent, and potentially harmful in certain situations (PCIe/PL310 1250 * deadlock on Armada 375/38x due to hardware I/O coherency). The 1251 * other operations are kept because they are infrequent (therefore do 1252 * not cause the deadlock in practice) and needed for secondary CPU 1253 * boot and other power management activities. 1254 */ 1255 static const struct l2c_init_data of_l2c310_coherent_data __initconst = { 1256 .type = "L2C-310 Coherent", 1257 .way_size_0 = SZ_8K, 1258 .num_lock = 8, 1259 .of_parse = l2c310_of_parse, 1260 .enable = l2c310_enable, 1261 .fixup = l2c310_fixup, 1262 .save = l2c310_save, 1263 .configure = l2c310_configure, 1264 .unlock = l2c310_unlock, 1265 .outer_cache = { 1266 .inv_range = l2c210_inv_range, 1267 .clean_range = l2c210_clean_range, 1268 .flush_range = l2c210_flush_range, 1269 .flush_all = l2c210_flush_all, 1270 .disable = l2c310_disable, 1271 .resume = l2c310_resume, 1272 }, 1273 }; 1274 1275 /* 1276 * Note that the end addresses passed to Linux primitives are 1277 * noninclusive, while the hardware cache range operations use 1278 * inclusive start and end addresses. 1279 */ 1280 static unsigned long aurora_range_end(unsigned long start, unsigned long end) 1281 { 1282 /* 1283 * Limit the number of cache lines processed at once, 1284 * since cache range operations stall the CPU pipeline 1285 * until completion. 1286 */ 1287 if (end > start + MAX_RANGE_SIZE) 1288 end = start + MAX_RANGE_SIZE; 1289 1290 /* 1291 * Cache range operations can't straddle a page boundary. 1292 */ 1293 if (end > PAGE_ALIGN(start+1)) 1294 end = PAGE_ALIGN(start+1); 1295 1296 return end; 1297 } 1298 1299 static void aurora_pa_range(unsigned long start, unsigned long end, 1300 unsigned long offset) 1301 { 1302 void __iomem *base = l2x0_base; 1303 unsigned long range_end; 1304 unsigned long flags; 1305 1306 /* 1307 * round start and end adresses up to cache line size 1308 */ 1309 start &= ~(CACHE_LINE_SIZE - 1); 1310 end = ALIGN(end, CACHE_LINE_SIZE); 1311 1312 /* 1313 * perform operation on all full cache lines between 'start' and 'end' 1314 */ 1315 while (start < end) { 1316 range_end = aurora_range_end(start, end); 1317 1318 raw_spin_lock_irqsave(&l2x0_lock, flags); 1319 writel_relaxed(start, base + AURORA_RANGE_BASE_ADDR_REG); 1320 writel_relaxed(range_end - CACHE_LINE_SIZE, base + offset); 1321 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 1322 1323 writel_relaxed(0, base + AURORA_SYNC_REG); 1324 start = range_end; 1325 } 1326 } 1327 static void aurora_inv_range(unsigned long start, unsigned long end) 1328 { 1329 aurora_pa_range(start, end, AURORA_INVAL_RANGE_REG); 1330 } 1331 1332 static void aurora_clean_range(unsigned long start, unsigned long end) 1333 { 1334 /* 1335 * If L2 is forced to WT, the L2 will always be clean and we 1336 * don't need to do anything here. 1337 */ 1338 if (!l2_wt_override) 1339 aurora_pa_range(start, end, AURORA_CLEAN_RANGE_REG); 1340 } 1341 1342 static void aurora_flush_range(unsigned long start, unsigned long end) 1343 { 1344 if (l2_wt_override) 1345 aurora_pa_range(start, end, AURORA_INVAL_RANGE_REG); 1346 else 1347 aurora_pa_range(start, end, AURORA_FLUSH_RANGE_REG); 1348 } 1349 1350 static void aurora_flush_all(void) 1351 { 1352 void __iomem *base = l2x0_base; 1353 unsigned long flags; 1354 1355 /* clean all ways */ 1356 raw_spin_lock_irqsave(&l2x0_lock, flags); 1357 __l2c_op_way(base + L2X0_CLEAN_INV_WAY); 1358 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 1359 1360 writel_relaxed(0, base + AURORA_SYNC_REG); 1361 } 1362 1363 static void aurora_cache_sync(void) 1364 { 1365 writel_relaxed(0, l2x0_base + AURORA_SYNC_REG); 1366 } 1367 1368 static void aurora_disable(void) 1369 { 1370 void __iomem *base = l2x0_base; 1371 unsigned long flags; 1372 1373 raw_spin_lock_irqsave(&l2x0_lock, flags); 1374 __l2c_op_way(base + L2X0_CLEAN_INV_WAY); 1375 writel_relaxed(0, base + AURORA_SYNC_REG); 1376 l2c_write_sec(0, base, L2X0_CTRL); 1377 dsb(st); 1378 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 1379 } 1380 1381 static void aurora_save(void __iomem *base) 1382 { 1383 l2x0_saved_regs.ctrl = readl_relaxed(base + L2X0_CTRL); 1384 l2x0_saved_regs.aux_ctrl = readl_relaxed(base + L2X0_AUX_CTRL); 1385 } 1386 1387 /* 1388 * For Aurora cache in no outer mode, enable via the CP15 coprocessor 1389 * broadcasting of cache commands to L2. 1390 */ 1391 static void __init aurora_enable_no_outer(void __iomem *base, u32 aux, 1392 unsigned num_lock) 1393 { 1394 u32 u; 1395 1396 asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u)); 1397 u |= AURORA_CTRL_FW; /* Set the FW bit */ 1398 asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u)); 1399 1400 isb(); 1401 1402 l2c_enable(base, aux, num_lock); 1403 } 1404 1405 static void __init aurora_fixup(void __iomem *base, u32 cache_id, 1406 struct outer_cache_fns *fns) 1407 { 1408 sync_reg_offset = AURORA_SYNC_REG; 1409 } 1410 1411 static void __init aurora_of_parse(const struct device_node *np, 1412 u32 *aux_val, u32 *aux_mask) 1413 { 1414 u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU; 1415 u32 mask = AURORA_ACR_REPLACEMENT_MASK; 1416 1417 of_property_read_u32(np, "cache-id-part", 1418 &cache_id_part_number_from_dt); 1419 1420 /* Determine and save the write policy */ 1421 l2_wt_override = of_property_read_bool(np, "wt-override"); 1422 1423 if (l2_wt_override) { 1424 val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY; 1425 mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK; 1426 } 1427 1428 *aux_val &= ~mask; 1429 *aux_val |= val; 1430 *aux_mask &= ~mask; 1431 } 1432 1433 static const struct l2c_init_data of_aurora_with_outer_data __initconst = { 1434 .type = "Aurora", 1435 .way_size_0 = SZ_4K, 1436 .num_lock = 4, 1437 .of_parse = aurora_of_parse, 1438 .enable = l2c_enable, 1439 .fixup = aurora_fixup, 1440 .save = aurora_save, 1441 .configure = l2c_configure, 1442 .unlock = l2c_unlock, 1443 .outer_cache = { 1444 .inv_range = aurora_inv_range, 1445 .clean_range = aurora_clean_range, 1446 .flush_range = aurora_flush_range, 1447 .flush_all = aurora_flush_all, 1448 .disable = aurora_disable, 1449 .sync = aurora_cache_sync, 1450 .resume = l2c_resume, 1451 }, 1452 }; 1453 1454 static const struct l2c_init_data of_aurora_no_outer_data __initconst = { 1455 .type = "Aurora", 1456 .way_size_0 = SZ_4K, 1457 .num_lock = 4, 1458 .of_parse = aurora_of_parse, 1459 .enable = aurora_enable_no_outer, 1460 .fixup = aurora_fixup, 1461 .save = aurora_save, 1462 .configure = l2c_configure, 1463 .unlock = l2c_unlock, 1464 .outer_cache = { 1465 .resume = l2c_resume, 1466 }, 1467 }; 1468 1469 /* 1470 * For certain Broadcom SoCs, depending on the address range, different offsets 1471 * need to be added to the address before passing it to L2 for 1472 * invalidation/clean/flush 1473 * 1474 * Section Address Range Offset EMI 1475 * 1 0x00000000 - 0x3FFFFFFF 0x80000000 VC 1476 * 2 0x40000000 - 0xBFFFFFFF 0x40000000 SYS 1477 * 3 0xC0000000 - 0xFFFFFFFF 0x80000000 VC 1478 * 1479 * When the start and end addresses have crossed two different sections, we 1480 * need to break the L2 operation into two, each within its own section. 1481 * For example, if we need to invalidate addresses starts at 0xBFFF0000 and 1482 * ends at 0xC0001000, we need do invalidate 1) 0xBFFF0000 - 0xBFFFFFFF and 2) 1483 * 0xC0000000 - 0xC0001000 1484 * 1485 * Note 1: 1486 * By breaking a single L2 operation into two, we may potentially suffer some 1487 * performance hit, but keep in mind the cross section case is very rare 1488 * 1489 * Note 2: 1490 * We do not need to handle the case when the start address is in 1491 * Section 1 and the end address is in Section 3, since it is not a valid use 1492 * case 1493 * 1494 * Note 3: 1495 * Section 1 in practical terms can no longer be used on rev A2. Because of 1496 * that the code does not need to handle section 1 at all. 1497 * 1498 */ 1499 #define BCM_SYS_EMI_START_ADDR 0x40000000UL 1500 #define BCM_VC_EMI_SEC3_START_ADDR 0xC0000000UL 1501 1502 #define BCM_SYS_EMI_OFFSET 0x40000000UL 1503 #define BCM_VC_EMI_OFFSET 0x80000000UL 1504 1505 static inline int bcm_addr_is_sys_emi(unsigned long addr) 1506 { 1507 return (addr >= BCM_SYS_EMI_START_ADDR) && 1508 (addr < BCM_VC_EMI_SEC3_START_ADDR); 1509 } 1510 1511 static inline unsigned long bcm_l2_phys_addr(unsigned long addr) 1512 { 1513 if (bcm_addr_is_sys_emi(addr)) 1514 return addr + BCM_SYS_EMI_OFFSET; 1515 else 1516 return addr + BCM_VC_EMI_OFFSET; 1517 } 1518 1519 static void bcm_inv_range(unsigned long start, unsigned long end) 1520 { 1521 unsigned long new_start, new_end; 1522 1523 BUG_ON(start < BCM_SYS_EMI_START_ADDR); 1524 1525 if (unlikely(end <= start)) 1526 return; 1527 1528 new_start = bcm_l2_phys_addr(start); 1529 new_end = bcm_l2_phys_addr(end); 1530 1531 /* normal case, no cross section between start and end */ 1532 if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { 1533 l2c210_inv_range(new_start, new_end); 1534 return; 1535 } 1536 1537 /* They cross sections, so it can only be a cross from section 1538 * 2 to section 3 1539 */ 1540 l2c210_inv_range(new_start, 1541 bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); 1542 l2c210_inv_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), 1543 new_end); 1544 } 1545 1546 static void bcm_clean_range(unsigned long start, unsigned long end) 1547 { 1548 unsigned long new_start, new_end; 1549 1550 BUG_ON(start < BCM_SYS_EMI_START_ADDR); 1551 1552 if (unlikely(end <= start)) 1553 return; 1554 1555 new_start = bcm_l2_phys_addr(start); 1556 new_end = bcm_l2_phys_addr(end); 1557 1558 /* normal case, no cross section between start and end */ 1559 if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { 1560 l2c210_clean_range(new_start, new_end); 1561 return; 1562 } 1563 1564 /* They cross sections, so it can only be a cross from section 1565 * 2 to section 3 1566 */ 1567 l2c210_clean_range(new_start, 1568 bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); 1569 l2c210_clean_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), 1570 new_end); 1571 } 1572 1573 static void bcm_flush_range(unsigned long start, unsigned long end) 1574 { 1575 unsigned long new_start, new_end; 1576 1577 BUG_ON(start < BCM_SYS_EMI_START_ADDR); 1578 1579 if (unlikely(end <= start)) 1580 return; 1581 1582 if ((end - start) >= l2x0_size) { 1583 outer_cache.flush_all(); 1584 return; 1585 } 1586 1587 new_start = bcm_l2_phys_addr(start); 1588 new_end = bcm_l2_phys_addr(end); 1589 1590 /* normal case, no cross section between start and end */ 1591 if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { 1592 l2c210_flush_range(new_start, new_end); 1593 return; 1594 } 1595 1596 /* They cross sections, so it can only be a cross from section 1597 * 2 to section 3 1598 */ 1599 l2c210_flush_range(new_start, 1600 bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); 1601 l2c210_flush_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), 1602 new_end); 1603 } 1604 1605 /* Broadcom L2C-310 start from ARMs R3P2 or later, and require no fixups */ 1606 static const struct l2c_init_data of_bcm_l2x0_data __initconst = { 1607 .type = "BCM-L2C-310", 1608 .way_size_0 = SZ_8K, 1609 .num_lock = 8, 1610 .of_parse = l2c310_of_parse, 1611 .enable = l2c310_enable, 1612 .save = l2c310_save, 1613 .configure = l2c310_configure, 1614 .unlock = l2c310_unlock, 1615 .outer_cache = { 1616 .inv_range = bcm_inv_range, 1617 .clean_range = bcm_clean_range, 1618 .flush_range = bcm_flush_range, 1619 .flush_all = l2c210_flush_all, 1620 .disable = l2c310_disable, 1621 .sync = l2c210_sync, 1622 .resume = l2c310_resume, 1623 }, 1624 }; 1625 1626 static void __init tauros3_save(void __iomem *base) 1627 { 1628 l2c_save(base); 1629 1630 l2x0_saved_regs.aux2_ctrl = 1631 readl_relaxed(base + TAUROS3_AUX2_CTRL); 1632 l2x0_saved_regs.prefetch_ctrl = 1633 readl_relaxed(base + L310_PREFETCH_CTRL); 1634 } 1635 1636 static void tauros3_configure(void __iomem *base) 1637 { 1638 l2c_configure(base); 1639 writel_relaxed(l2x0_saved_regs.aux2_ctrl, 1640 base + TAUROS3_AUX2_CTRL); 1641 writel_relaxed(l2x0_saved_regs.prefetch_ctrl, 1642 base + L310_PREFETCH_CTRL); 1643 } 1644 1645 static const struct l2c_init_data of_tauros3_data __initconst = { 1646 .type = "Tauros3", 1647 .way_size_0 = SZ_8K, 1648 .num_lock = 8, 1649 .enable = l2c_enable, 1650 .save = tauros3_save, 1651 .configure = tauros3_configure, 1652 .unlock = l2c_unlock, 1653 /* Tauros3 broadcasts L1 cache operations to L2 */ 1654 .outer_cache = { 1655 .resume = l2c_resume, 1656 }, 1657 }; 1658 1659 #define L2C_ID(name, fns) { .compatible = name, .data = (void *)&fns } 1660 static const struct of_device_id l2x0_ids[] __initconst = { 1661 L2C_ID("arm,l210-cache", of_l2c210_data), 1662 L2C_ID("arm,l220-cache", of_l2c220_data), 1663 L2C_ID("arm,pl310-cache", of_l2c310_data), 1664 L2C_ID("brcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data), 1665 L2C_ID("marvell,aurora-outer-cache", of_aurora_with_outer_data), 1666 L2C_ID("marvell,aurora-system-cache", of_aurora_no_outer_data), 1667 L2C_ID("marvell,tauros3-cache", of_tauros3_data), 1668 /* Deprecated IDs */ 1669 L2C_ID("bcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data), 1670 {} 1671 }; 1672 1673 int __init l2x0_of_init(u32 aux_val, u32 aux_mask) 1674 { 1675 const struct l2c_init_data *data; 1676 struct device_node *np; 1677 struct resource res; 1678 u32 cache_id, old_aux; 1679 u32 cache_level = 2; 1680 1681 np = of_find_matching_node(NULL, l2x0_ids); 1682 if (!np) 1683 return -ENODEV; 1684 1685 if (of_address_to_resource(np, 0, &res)) 1686 return -ENODEV; 1687 1688 l2x0_base = ioremap(res.start, resource_size(&res)); 1689 if (!l2x0_base) 1690 return -ENOMEM; 1691 1692 l2x0_saved_regs.phy_base = res.start; 1693 1694 data = of_match_node(l2x0_ids, np)->data; 1695 1696 if (of_device_is_compatible(np, "arm,pl310-cache") && 1697 of_property_read_bool(np, "arm,io-coherent")) 1698 data = &of_l2c310_coherent_data; 1699 1700 old_aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); 1701 if (old_aux != ((old_aux & aux_mask) | aux_val)) { 1702 pr_warn("L2C: platform modifies aux control register: 0x%08x -> 0x%08x\n", 1703 old_aux, (old_aux & aux_mask) | aux_val); 1704 } else if (aux_mask != ~0U && aux_val != 0) { 1705 pr_alert("L2C: platform provided aux values match the hardware, so have no effect. Please remove them.\n"); 1706 } 1707 1708 /* All L2 caches are unified, so this property should be specified */ 1709 if (!of_property_read_bool(np, "cache-unified")) 1710 pr_err("L2C: device tree omits to specify unified cache\n"); 1711 1712 if (of_property_read_u32(np, "cache-level", &cache_level)) 1713 pr_err("L2C: device tree omits to specify cache-level\n"); 1714 1715 if (cache_level != 2) 1716 pr_err("L2C: device tree specifies invalid cache level\n"); 1717 1718 /* Read back current (default) hardware configuration */ 1719 if (data->save) 1720 data->save(l2x0_base); 1721 1722 /* L2 configuration can only be changed if the cache is disabled */ 1723 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) 1724 if (data->of_parse) 1725 data->of_parse(np, &aux_val, &aux_mask); 1726 1727 if (cache_id_part_number_from_dt) 1728 cache_id = cache_id_part_number_from_dt; 1729 else 1730 cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); 1731 1732 return __l2c_init(data, aux_val, aux_mask, cache_id); 1733 } 1734 #endif 1735