1 /* 2 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support 3 * 4 * Copyright (C) 2007 ARM Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 #include <linux/init.h> 20 #include <linux/spinlock.h> 21 #include <linux/io.h> 22 23 #include <asm/cacheflush.h> 24 #include <asm/hardware/cache-l2x0.h> 25 26 #define CACHE_LINE_SIZE 32 27 28 static void __iomem *l2x0_base; 29 static DEFINE_SPINLOCK(l2x0_lock); 30 31 static inline void cache_wait(void __iomem *reg, unsigned long mask) 32 { 33 /* wait for the operation to complete */ 34 while (readl(reg) & mask) 35 ; 36 } 37 38 static inline void cache_sync(void) 39 { 40 void __iomem *base = l2x0_base; 41 writel(0, base + L2X0_CACHE_SYNC); 42 cache_wait(base + L2X0_CACHE_SYNC, 1); 43 } 44 45 static inline void l2x0_inv_all(void) 46 { 47 unsigned long flags; 48 49 /* invalidate all ways */ 50 spin_lock_irqsave(&l2x0_lock, flags); 51 writel(0xff, l2x0_base + L2X0_INV_WAY); 52 cache_wait(l2x0_base + L2X0_INV_WAY, 0xff); 53 cache_sync(); 54 spin_unlock_irqrestore(&l2x0_lock, flags); 55 } 56 57 static void l2x0_inv_range(unsigned long start, unsigned long end) 58 { 59 void __iomem *base = l2x0_base; 60 unsigned long flags; 61 62 spin_lock_irqsave(&l2x0_lock, flags); 63 if (start & (CACHE_LINE_SIZE - 1)) { 64 start &= ~(CACHE_LINE_SIZE - 1); 65 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 66 writel(start, base + L2X0_CLEAN_INV_LINE_PA); 67 start += CACHE_LINE_SIZE; 68 } 69 70 if (end & (CACHE_LINE_SIZE - 1)) { 71 end &= ~(CACHE_LINE_SIZE - 1); 72 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 73 writel(end, base + L2X0_CLEAN_INV_LINE_PA); 74 } 75 76 while (start < end) { 77 unsigned long blk_end = start + min(end - start, 4096UL); 78 79 while (start < blk_end) { 80 cache_wait(base + L2X0_INV_LINE_PA, 1); 81 writel(start, base + L2X0_INV_LINE_PA); 82 start += CACHE_LINE_SIZE; 83 } 84 85 if (blk_end < end) { 86 spin_unlock_irqrestore(&l2x0_lock, flags); 87 spin_lock_irqsave(&l2x0_lock, flags); 88 } 89 } 90 cache_wait(base + L2X0_INV_LINE_PA, 1); 91 cache_sync(); 92 spin_unlock_irqrestore(&l2x0_lock, flags); 93 } 94 95 static void l2x0_clean_range(unsigned long start, unsigned long end) 96 { 97 void __iomem *base = l2x0_base; 98 unsigned long flags; 99 100 spin_lock_irqsave(&l2x0_lock, flags); 101 start &= ~(CACHE_LINE_SIZE - 1); 102 while (start < end) { 103 unsigned long blk_end = start + min(end - start, 4096UL); 104 105 while (start < blk_end) { 106 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 107 writel(start, base + L2X0_CLEAN_LINE_PA); 108 start += CACHE_LINE_SIZE; 109 } 110 111 if (blk_end < end) { 112 spin_unlock_irqrestore(&l2x0_lock, flags); 113 spin_lock_irqsave(&l2x0_lock, flags); 114 } 115 } 116 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 117 cache_sync(); 118 spin_unlock_irqrestore(&l2x0_lock, flags); 119 } 120 121 static void l2x0_flush_range(unsigned long start, unsigned long end) 122 { 123 void __iomem *base = l2x0_base; 124 unsigned long flags; 125 126 spin_lock_irqsave(&l2x0_lock, flags); 127 start &= ~(CACHE_LINE_SIZE - 1); 128 while (start < end) { 129 unsigned long blk_end = start + min(end - start, 4096UL); 130 131 while (start < blk_end) { 132 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 133 writel(start, base + L2X0_CLEAN_INV_LINE_PA); 134 start += CACHE_LINE_SIZE; 135 } 136 137 if (blk_end < end) { 138 spin_unlock_irqrestore(&l2x0_lock, flags); 139 spin_lock_irqsave(&l2x0_lock, flags); 140 } 141 } 142 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 143 cache_sync(); 144 spin_unlock_irqrestore(&l2x0_lock, flags); 145 } 146 147 void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) 148 { 149 __u32 aux; 150 151 l2x0_base = base; 152 153 /* 154 * Check if l2x0 controller is already enabled. 155 * If you are booting from non-secure mode 156 * accessing the below registers will fault. 157 */ 158 if (!(readl(l2x0_base + L2X0_CTRL) & 1)) { 159 160 /* l2x0 controller is disabled */ 161 162 aux = readl(l2x0_base + L2X0_AUX_CTRL); 163 aux &= aux_mask; 164 aux |= aux_val; 165 writel(aux, l2x0_base + L2X0_AUX_CTRL); 166 167 l2x0_inv_all(); 168 169 /* enable L2X0 */ 170 writel(1, l2x0_base + L2X0_CTRL); 171 } 172 173 outer_cache.inv_range = l2x0_inv_range; 174 outer_cache.clean_range = l2x0_clean_range; 175 outer_cache.flush_range = l2x0_flush_range; 176 177 printk(KERN_INFO "L2X0 cache controller enabled\n"); 178 } 179