1 /* 2 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support 3 * 4 * Copyright (C) 2007 ARM Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 #include <linux/init.h> 20 #include <linux/spinlock.h> 21 #include <linux/io.h> 22 23 #include <asm/cacheflush.h> 24 #include <asm/hardware/cache-l2x0.h> 25 26 #define CACHE_LINE_SIZE 32 27 28 static void __iomem *l2x0_base; 29 static DEFINE_SPINLOCK(l2x0_lock); 30 31 static inline void cache_wait(void __iomem *reg, unsigned long mask) 32 { 33 /* wait for the operation to complete */ 34 while (readl(reg) & mask) 35 ; 36 } 37 38 static inline void cache_sync(void) 39 { 40 void __iomem *base = l2x0_base; 41 writel(0, base + L2X0_CACHE_SYNC); 42 cache_wait(base + L2X0_CACHE_SYNC, 1); 43 } 44 45 static inline void l2x0_clean_line(unsigned long addr) 46 { 47 void __iomem *base = l2x0_base; 48 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 49 writel(addr, base + L2X0_CLEAN_LINE_PA); 50 } 51 52 static inline void l2x0_inv_line(unsigned long addr) 53 { 54 void __iomem *base = l2x0_base; 55 cache_wait(base + L2X0_INV_LINE_PA, 1); 56 writel(addr, base + L2X0_INV_LINE_PA); 57 } 58 59 #ifdef CONFIG_PL310_ERRATA_588369 60 static void debug_writel(unsigned long val) 61 { 62 extern void omap_smc1(u32 fn, u32 arg); 63 64 /* 65 * Texas Instrument secure monitor api to modify the 66 * PL310 Debug Control Register. 67 */ 68 omap_smc1(0x100, val); 69 } 70 71 static inline void l2x0_flush_line(unsigned long addr) 72 { 73 void __iomem *base = l2x0_base; 74 75 /* Clean by PA followed by Invalidate by PA */ 76 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 77 writel(addr, base + L2X0_CLEAN_LINE_PA); 78 cache_wait(base + L2X0_INV_LINE_PA, 1); 79 writel(addr, base + L2X0_INV_LINE_PA); 80 } 81 #else 82 83 /* Optimised out for non-errata case */ 84 static inline void debug_writel(unsigned long val) 85 { 86 } 87 88 static inline void l2x0_flush_line(unsigned long addr) 89 { 90 void __iomem *base = l2x0_base; 91 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 92 writel(addr, base + L2X0_CLEAN_INV_LINE_PA); 93 } 94 #endif 95 96 static inline void l2x0_inv_all(void) 97 { 98 unsigned long flags; 99 100 /* invalidate all ways */ 101 spin_lock_irqsave(&l2x0_lock, flags); 102 writel(0xff, l2x0_base + L2X0_INV_WAY); 103 cache_wait(l2x0_base + L2X0_INV_WAY, 0xff); 104 cache_sync(); 105 spin_unlock_irqrestore(&l2x0_lock, flags); 106 } 107 108 static void l2x0_inv_range(unsigned long start, unsigned long end) 109 { 110 void __iomem *base = l2x0_base; 111 unsigned long flags; 112 113 spin_lock_irqsave(&l2x0_lock, flags); 114 if (start & (CACHE_LINE_SIZE - 1)) { 115 start &= ~(CACHE_LINE_SIZE - 1); 116 debug_writel(0x03); 117 l2x0_flush_line(start); 118 debug_writel(0x00); 119 start += CACHE_LINE_SIZE; 120 } 121 122 if (end & (CACHE_LINE_SIZE - 1)) { 123 end &= ~(CACHE_LINE_SIZE - 1); 124 debug_writel(0x03); 125 l2x0_flush_line(end); 126 debug_writel(0x00); 127 } 128 129 while (start < end) { 130 unsigned long blk_end = start + min(end - start, 4096UL); 131 132 while (start < blk_end) { 133 l2x0_inv_line(start); 134 start += CACHE_LINE_SIZE; 135 } 136 137 if (blk_end < end) { 138 spin_unlock_irqrestore(&l2x0_lock, flags); 139 spin_lock_irqsave(&l2x0_lock, flags); 140 } 141 } 142 cache_wait(base + L2X0_INV_LINE_PA, 1); 143 cache_sync(); 144 spin_unlock_irqrestore(&l2x0_lock, flags); 145 } 146 147 static void l2x0_clean_range(unsigned long start, unsigned long end) 148 { 149 void __iomem *base = l2x0_base; 150 unsigned long flags; 151 152 spin_lock_irqsave(&l2x0_lock, flags); 153 start &= ~(CACHE_LINE_SIZE - 1); 154 while (start < end) { 155 unsigned long blk_end = start + min(end - start, 4096UL); 156 157 while (start < blk_end) { 158 l2x0_clean_line(start); 159 start += CACHE_LINE_SIZE; 160 } 161 162 if (blk_end < end) { 163 spin_unlock_irqrestore(&l2x0_lock, flags); 164 spin_lock_irqsave(&l2x0_lock, flags); 165 } 166 } 167 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 168 cache_sync(); 169 spin_unlock_irqrestore(&l2x0_lock, flags); 170 } 171 172 static void l2x0_flush_range(unsigned long start, unsigned long end) 173 { 174 void __iomem *base = l2x0_base; 175 unsigned long flags; 176 177 spin_lock_irqsave(&l2x0_lock, flags); 178 start &= ~(CACHE_LINE_SIZE - 1); 179 while (start < end) { 180 unsigned long blk_end = start + min(end - start, 4096UL); 181 182 debug_writel(0x03); 183 while (start < blk_end) { 184 l2x0_flush_line(start); 185 start += CACHE_LINE_SIZE; 186 } 187 debug_writel(0x00); 188 189 if (blk_end < end) { 190 spin_unlock_irqrestore(&l2x0_lock, flags); 191 spin_lock_irqsave(&l2x0_lock, flags); 192 } 193 } 194 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 195 cache_sync(); 196 spin_unlock_irqrestore(&l2x0_lock, flags); 197 } 198 199 void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) 200 { 201 __u32 aux; 202 203 l2x0_base = base; 204 205 /* 206 * Check if l2x0 controller is already enabled. 207 * If you are booting from non-secure mode 208 * accessing the below registers will fault. 209 */ 210 if (!(readl(l2x0_base + L2X0_CTRL) & 1)) { 211 212 /* l2x0 controller is disabled */ 213 214 aux = readl(l2x0_base + L2X0_AUX_CTRL); 215 aux &= aux_mask; 216 aux |= aux_val; 217 writel(aux, l2x0_base + L2X0_AUX_CTRL); 218 219 l2x0_inv_all(); 220 221 /* enable L2X0 */ 222 writel(1, l2x0_base + L2X0_CTRL); 223 } 224 225 outer_cache.inv_range = l2x0_inv_range; 226 outer_cache.clean_range = l2x0_clean_range; 227 outer_cache.flush_range = l2x0_flush_range; 228 229 printk(KERN_INFO "L2X0 cache controller enabled\n"); 230 } 231