1 /* 2 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support 3 * 4 * Copyright (C) 2007 ARM Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 #include <linux/err.h> 20 #include <linux/init.h> 21 #include <linux/spinlock.h> 22 #include <linux/io.h> 23 #include <linux/of.h> 24 #include <linux/of_address.h> 25 26 #include <asm/cacheflush.h> 27 #include <asm/hardware/cache-l2x0.h> 28 #include "cache-tauros3.h" 29 #include "cache-aurora-l2.h" 30 31 struct l2c_init_data { 32 void (*of_parse)(const struct device_node *, u32 *, u32 *); 33 void (*save)(void); 34 struct outer_cache_fns outer_cache; 35 }; 36 37 #define CACHE_LINE_SIZE 32 38 39 static void __iomem *l2x0_base; 40 static DEFINE_RAW_SPINLOCK(l2x0_lock); 41 static u32 l2x0_way_mask; /* Bitmask of active ways */ 42 static u32 l2x0_size; 43 static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; 44 45 struct l2x0_regs l2x0_saved_regs; 46 47 /* 48 * Common code for all cache controllers. 49 */ 50 static inline void l2c_wait_mask(void __iomem *reg, unsigned long mask) 51 { 52 /* wait for cache operation by line or way to complete */ 53 while (readl_relaxed(reg) & mask) 54 cpu_relax(); 55 } 56 57 /* 58 * This should only be called when we have a requirement that the 59 * register be written due to a work-around, as platforms running 60 * in non-secure mode may not be able to access this register. 61 */ 62 static inline void l2c_set_debug(void __iomem *base, unsigned long val) 63 { 64 outer_cache.set_debug(val); 65 } 66 67 static void __l2c_op_way(void __iomem *reg) 68 { 69 writel_relaxed(l2x0_way_mask, reg); 70 l2c_wait_mask(reg, l2x0_way_mask); 71 } 72 73 static inline void l2c_unlock(void __iomem *base, unsigned num) 74 { 75 unsigned i; 76 77 for (i = 0; i < num; i++) { 78 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE + 79 i * L2X0_LOCKDOWN_STRIDE); 80 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE + 81 i * L2X0_LOCKDOWN_STRIDE); 82 } 83 } 84 85 #ifdef CONFIG_CACHE_PL310 86 static inline void cache_wait(void __iomem *reg, unsigned long mask) 87 { 88 /* cache operations by line are atomic on PL310 */ 89 } 90 #else 91 #define cache_wait l2c_wait_mask 92 #endif 93 94 static inline void cache_sync(void) 95 { 96 void __iomem *base = l2x0_base; 97 98 writel_relaxed(0, base + sync_reg_offset); 99 cache_wait(base + L2X0_CACHE_SYNC, 1); 100 } 101 102 static inline void l2x0_clean_line(unsigned long addr) 103 { 104 void __iomem *base = l2x0_base; 105 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 106 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA); 107 } 108 109 static inline void l2x0_inv_line(unsigned long addr) 110 { 111 void __iomem *base = l2x0_base; 112 cache_wait(base + L2X0_INV_LINE_PA, 1); 113 writel_relaxed(addr, base + L2X0_INV_LINE_PA); 114 } 115 116 #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) 117 static inline void debug_writel(unsigned long val) 118 { 119 if (outer_cache.set_debug) 120 l2c_set_debug(l2x0_base, val); 121 } 122 123 static void pl310_set_debug(unsigned long val) 124 { 125 writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL); 126 } 127 #else 128 /* Optimised out for non-errata case */ 129 static inline void debug_writel(unsigned long val) 130 { 131 } 132 133 #define pl310_set_debug NULL 134 #endif 135 136 #ifdef CONFIG_PL310_ERRATA_588369 137 static inline void l2x0_flush_line(unsigned long addr) 138 { 139 void __iomem *base = l2x0_base; 140 141 /* Clean by PA followed by Invalidate by PA */ 142 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 143 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA); 144 cache_wait(base + L2X0_INV_LINE_PA, 1); 145 writel_relaxed(addr, base + L2X0_INV_LINE_PA); 146 } 147 #else 148 149 static inline void l2x0_flush_line(unsigned long addr) 150 { 151 void __iomem *base = l2x0_base; 152 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 153 writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA); 154 } 155 #endif 156 157 static void l2x0_cache_sync(void) 158 { 159 unsigned long flags; 160 161 raw_spin_lock_irqsave(&l2x0_lock, flags); 162 cache_sync(); 163 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 164 } 165 166 static void __l2x0_flush_all(void) 167 { 168 debug_writel(0x03); 169 __l2c_op_way(l2x0_base + L2X0_CLEAN_INV_WAY); 170 cache_sync(); 171 debug_writel(0x00); 172 } 173 174 static void l2x0_flush_all(void) 175 { 176 unsigned long flags; 177 178 /* clean all ways */ 179 raw_spin_lock_irqsave(&l2x0_lock, flags); 180 __l2x0_flush_all(); 181 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 182 } 183 184 static void l2x0_clean_all(void) 185 { 186 unsigned long flags; 187 188 /* clean all ways */ 189 raw_spin_lock_irqsave(&l2x0_lock, flags); 190 __l2c_op_way(l2x0_base + L2X0_CLEAN_WAY); 191 cache_sync(); 192 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 193 } 194 195 static void l2x0_inv_all(void) 196 { 197 unsigned long flags; 198 199 /* invalidate all ways */ 200 raw_spin_lock_irqsave(&l2x0_lock, flags); 201 /* Invalidating when L2 is enabled is a nono */ 202 BUG_ON(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN); 203 __l2c_op_way(l2x0_base + L2X0_INV_WAY); 204 cache_sync(); 205 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 206 } 207 208 static void l2x0_inv_range(unsigned long start, unsigned long end) 209 { 210 void __iomem *base = l2x0_base; 211 unsigned long flags; 212 213 raw_spin_lock_irqsave(&l2x0_lock, flags); 214 if (start & (CACHE_LINE_SIZE - 1)) { 215 start &= ~(CACHE_LINE_SIZE - 1); 216 debug_writel(0x03); 217 l2x0_flush_line(start); 218 debug_writel(0x00); 219 start += CACHE_LINE_SIZE; 220 } 221 222 if (end & (CACHE_LINE_SIZE - 1)) { 223 end &= ~(CACHE_LINE_SIZE - 1); 224 debug_writel(0x03); 225 l2x0_flush_line(end); 226 debug_writel(0x00); 227 } 228 229 while (start < end) { 230 unsigned long blk_end = start + min(end - start, 4096UL); 231 232 while (start < blk_end) { 233 l2x0_inv_line(start); 234 start += CACHE_LINE_SIZE; 235 } 236 237 if (blk_end < end) { 238 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 239 raw_spin_lock_irqsave(&l2x0_lock, flags); 240 } 241 } 242 cache_wait(base + L2X0_INV_LINE_PA, 1); 243 cache_sync(); 244 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 245 } 246 247 static void l2x0_clean_range(unsigned long start, unsigned long end) 248 { 249 void __iomem *base = l2x0_base; 250 unsigned long flags; 251 252 if ((end - start) >= l2x0_size) { 253 l2x0_clean_all(); 254 return; 255 } 256 257 raw_spin_lock_irqsave(&l2x0_lock, flags); 258 start &= ~(CACHE_LINE_SIZE - 1); 259 while (start < end) { 260 unsigned long blk_end = start + min(end - start, 4096UL); 261 262 while (start < blk_end) { 263 l2x0_clean_line(start); 264 start += CACHE_LINE_SIZE; 265 } 266 267 if (blk_end < end) { 268 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 269 raw_spin_lock_irqsave(&l2x0_lock, flags); 270 } 271 } 272 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 273 cache_sync(); 274 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 275 } 276 277 static void l2x0_flush_range(unsigned long start, unsigned long end) 278 { 279 void __iomem *base = l2x0_base; 280 unsigned long flags; 281 282 if ((end - start) >= l2x0_size) { 283 l2x0_flush_all(); 284 return; 285 } 286 287 raw_spin_lock_irqsave(&l2x0_lock, flags); 288 start &= ~(CACHE_LINE_SIZE - 1); 289 while (start < end) { 290 unsigned long blk_end = start + min(end - start, 4096UL); 291 292 debug_writel(0x03); 293 while (start < blk_end) { 294 l2x0_flush_line(start); 295 start += CACHE_LINE_SIZE; 296 } 297 debug_writel(0x00); 298 299 if (blk_end < end) { 300 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 301 raw_spin_lock_irqsave(&l2x0_lock, flags); 302 } 303 } 304 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 305 cache_sync(); 306 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 307 } 308 309 static void l2x0_disable(void) 310 { 311 unsigned long flags; 312 313 raw_spin_lock_irqsave(&l2x0_lock, flags); 314 __l2x0_flush_all(); 315 writel_relaxed(0, l2x0_base + L2X0_CTRL); 316 dsb(st); 317 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 318 } 319 320 static void l2x0_unlock(u32 cache_id) 321 { 322 int lockregs; 323 324 switch (cache_id & L2X0_CACHE_ID_PART_MASK) { 325 case L2X0_CACHE_ID_PART_L310: 326 lockregs = 8; 327 break; 328 case AURORA_CACHE_ID: 329 lockregs = 4; 330 break; 331 default: 332 /* L210 and unknown types */ 333 lockregs = 1; 334 break; 335 } 336 337 l2c_unlock(l2x0_base, lockregs); 338 } 339 340 static const struct l2c_init_data l2x0_init_fns __initconst = { 341 .outer_cache = { 342 .inv_range = l2x0_inv_range, 343 .clean_range = l2x0_clean_range, 344 .flush_range = l2x0_flush_range, 345 .flush_all = l2x0_flush_all, 346 .disable = l2x0_disable, 347 .sync = l2x0_cache_sync, 348 }, 349 }; 350 351 static void __init __l2c_init(const struct l2c_init_data *data, 352 u32 aux_val, u32 aux_mask, u32 cache_id) 353 { 354 u32 aux; 355 u32 way_size = 0; 356 int ways; 357 int way_size_shift = L2X0_WAY_SIZE_SHIFT; 358 const char *type; 359 360 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); 361 362 aux &= aux_mask; 363 aux |= aux_val; 364 365 /* Determine the number of ways */ 366 switch (cache_id & L2X0_CACHE_ID_PART_MASK) { 367 case L2X0_CACHE_ID_PART_L310: 368 if (aux & (1 << 16)) 369 ways = 16; 370 else 371 ways = 8; 372 type = "L310"; 373 #ifdef CONFIG_PL310_ERRATA_753970 374 /* Unmapped register. */ 375 sync_reg_offset = L2X0_DUMMY_REG; 376 #endif 377 break; 378 case L2X0_CACHE_ID_PART_L210: 379 ways = (aux >> 13) & 0xf; 380 type = "L210"; 381 break; 382 383 case AURORA_CACHE_ID: 384 sync_reg_offset = AURORA_SYNC_REG; 385 ways = (aux >> 13) & 0xf; 386 ways = 2 << ((ways + 1) >> 2); 387 way_size_shift = AURORA_WAY_SIZE_SHIFT; 388 type = "Aurora"; 389 break; 390 default: 391 /* Assume unknown chips have 8 ways */ 392 ways = 8; 393 type = "L2x0 series"; 394 break; 395 } 396 397 l2x0_way_mask = (1 << ways) - 1; 398 399 /* 400 * L2 cache Size = Way size * Number of ways 401 */ 402 way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17; 403 way_size = 1 << (way_size + way_size_shift); 404 405 l2x0_size = ways * way_size * SZ_1K; 406 407 /* 408 * Check if l2x0 controller is already enabled. 409 * If you are booting from non-secure mode 410 * accessing the below registers will fault. 411 */ 412 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { 413 /* Make sure that I&D is not locked down when starting */ 414 l2x0_unlock(cache_id); 415 416 /* l2x0 controller is disabled */ 417 writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL); 418 419 l2x0_inv_all(); 420 421 /* enable L2X0 */ 422 writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL); 423 } 424 425 /* Re-read it in case some bits are reserved. */ 426 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); 427 428 /* Save the value for resuming. */ 429 l2x0_saved_regs.aux_ctrl = aux; 430 431 outer_cache = data->outer_cache; 432 433 if ((cache_id & L2X0_CACHE_ID_PART_MASK) == L2X0_CACHE_ID_PART_L310 && 434 (cache_id & L2X0_CACHE_ID_RTL_MASK) <= L310_CACHE_ID_RTL_R3P0) 435 outer_cache.set_debug = pl310_set_debug; 436 437 pr_info("%s cache controller enabled\n", type); 438 pr_info("l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d kB\n", 439 ways, cache_id, aux, l2x0_size >> 10); 440 } 441 442 void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) 443 { 444 u32 cache_id; 445 446 l2x0_base = base; 447 448 cache_id = readl_relaxed(base + L2X0_CACHE_ID); 449 450 __l2c_init(&l2x0_init_fns, aux_val, aux_mask, cache_id); 451 } 452 453 #ifdef CONFIG_OF 454 static int l2_wt_override; 455 456 /* Aurora don't have the cache ID register available, so we have to 457 * pass it though the device tree */ 458 static u32 cache_id_part_number_from_dt; 459 460 /* 461 * Note that the end addresses passed to Linux primitives are 462 * noninclusive, while the hardware cache range operations use 463 * inclusive start and end addresses. 464 */ 465 static unsigned long calc_range_end(unsigned long start, unsigned long end) 466 { 467 /* 468 * Limit the number of cache lines processed at once, 469 * since cache range operations stall the CPU pipeline 470 * until completion. 471 */ 472 if (end > start + MAX_RANGE_SIZE) 473 end = start + MAX_RANGE_SIZE; 474 475 /* 476 * Cache range operations can't straddle a page boundary. 477 */ 478 if (end > PAGE_ALIGN(start+1)) 479 end = PAGE_ALIGN(start+1); 480 481 return end; 482 } 483 484 /* 485 * Make sure 'start' and 'end' reference the same page, as L2 is PIPT 486 * and range operations only do a TLB lookup on the start address. 487 */ 488 static void aurora_pa_range(unsigned long start, unsigned long end, 489 unsigned long offset) 490 { 491 unsigned long flags; 492 493 raw_spin_lock_irqsave(&l2x0_lock, flags); 494 writel_relaxed(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG); 495 writel_relaxed(end, l2x0_base + offset); 496 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 497 498 cache_sync(); 499 } 500 501 static void aurora_inv_range(unsigned long start, unsigned long end) 502 { 503 /* 504 * round start and end adresses up to cache line size 505 */ 506 start &= ~(CACHE_LINE_SIZE - 1); 507 end = ALIGN(end, CACHE_LINE_SIZE); 508 509 /* 510 * Invalidate all full cache lines between 'start' and 'end'. 511 */ 512 while (start < end) { 513 unsigned long range_end = calc_range_end(start, end); 514 aurora_pa_range(start, range_end - CACHE_LINE_SIZE, 515 AURORA_INVAL_RANGE_REG); 516 start = range_end; 517 } 518 } 519 520 static void aurora_clean_range(unsigned long start, unsigned long end) 521 { 522 /* 523 * If L2 is forced to WT, the L2 will always be clean and we 524 * don't need to do anything here. 525 */ 526 if (!l2_wt_override) { 527 start &= ~(CACHE_LINE_SIZE - 1); 528 end = ALIGN(end, CACHE_LINE_SIZE); 529 while (start != end) { 530 unsigned long range_end = calc_range_end(start, end); 531 aurora_pa_range(start, range_end - CACHE_LINE_SIZE, 532 AURORA_CLEAN_RANGE_REG); 533 start = range_end; 534 } 535 } 536 } 537 538 static void aurora_flush_range(unsigned long start, unsigned long end) 539 { 540 start &= ~(CACHE_LINE_SIZE - 1); 541 end = ALIGN(end, CACHE_LINE_SIZE); 542 while (start != end) { 543 unsigned long range_end = calc_range_end(start, end); 544 /* 545 * If L2 is forced to WT, the L2 will always be clean and we 546 * just need to invalidate. 547 */ 548 if (l2_wt_override) 549 aurora_pa_range(start, range_end - CACHE_LINE_SIZE, 550 AURORA_INVAL_RANGE_REG); 551 else 552 aurora_pa_range(start, range_end - CACHE_LINE_SIZE, 553 AURORA_FLUSH_RANGE_REG); 554 start = range_end; 555 } 556 } 557 558 /* 559 * For certain Broadcom SoCs, depending on the address range, different offsets 560 * need to be added to the address before passing it to L2 for 561 * invalidation/clean/flush 562 * 563 * Section Address Range Offset EMI 564 * 1 0x00000000 - 0x3FFFFFFF 0x80000000 VC 565 * 2 0x40000000 - 0xBFFFFFFF 0x40000000 SYS 566 * 3 0xC0000000 - 0xFFFFFFFF 0x80000000 VC 567 * 568 * When the start and end addresses have crossed two different sections, we 569 * need to break the L2 operation into two, each within its own section. 570 * For example, if we need to invalidate addresses starts at 0xBFFF0000 and 571 * ends at 0xC0001000, we need do invalidate 1) 0xBFFF0000 - 0xBFFFFFFF and 2) 572 * 0xC0000000 - 0xC0001000 573 * 574 * Note 1: 575 * By breaking a single L2 operation into two, we may potentially suffer some 576 * performance hit, but keep in mind the cross section case is very rare 577 * 578 * Note 2: 579 * We do not need to handle the case when the start address is in 580 * Section 1 and the end address is in Section 3, since it is not a valid use 581 * case 582 * 583 * Note 3: 584 * Section 1 in practical terms can no longer be used on rev A2. Because of 585 * that the code does not need to handle section 1 at all. 586 * 587 */ 588 #define BCM_SYS_EMI_START_ADDR 0x40000000UL 589 #define BCM_VC_EMI_SEC3_START_ADDR 0xC0000000UL 590 591 #define BCM_SYS_EMI_OFFSET 0x40000000UL 592 #define BCM_VC_EMI_OFFSET 0x80000000UL 593 594 static inline int bcm_addr_is_sys_emi(unsigned long addr) 595 { 596 return (addr >= BCM_SYS_EMI_START_ADDR) && 597 (addr < BCM_VC_EMI_SEC3_START_ADDR); 598 } 599 600 static inline unsigned long bcm_l2_phys_addr(unsigned long addr) 601 { 602 if (bcm_addr_is_sys_emi(addr)) 603 return addr + BCM_SYS_EMI_OFFSET; 604 else 605 return addr + BCM_VC_EMI_OFFSET; 606 } 607 608 static void bcm_inv_range(unsigned long start, unsigned long end) 609 { 610 unsigned long new_start, new_end; 611 612 BUG_ON(start < BCM_SYS_EMI_START_ADDR); 613 614 if (unlikely(end <= start)) 615 return; 616 617 new_start = bcm_l2_phys_addr(start); 618 new_end = bcm_l2_phys_addr(end); 619 620 /* normal case, no cross section between start and end */ 621 if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { 622 l2x0_inv_range(new_start, new_end); 623 return; 624 } 625 626 /* They cross sections, so it can only be a cross from section 627 * 2 to section 3 628 */ 629 l2x0_inv_range(new_start, 630 bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); 631 l2x0_inv_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), 632 new_end); 633 } 634 635 static void bcm_clean_range(unsigned long start, unsigned long end) 636 { 637 unsigned long new_start, new_end; 638 639 BUG_ON(start < BCM_SYS_EMI_START_ADDR); 640 641 if (unlikely(end <= start)) 642 return; 643 644 if ((end - start) >= l2x0_size) { 645 l2x0_clean_all(); 646 return; 647 } 648 649 new_start = bcm_l2_phys_addr(start); 650 new_end = bcm_l2_phys_addr(end); 651 652 /* normal case, no cross section between start and end */ 653 if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { 654 l2x0_clean_range(new_start, new_end); 655 return; 656 } 657 658 /* They cross sections, so it can only be a cross from section 659 * 2 to section 3 660 */ 661 l2x0_clean_range(new_start, 662 bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); 663 l2x0_clean_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), 664 new_end); 665 } 666 667 static void bcm_flush_range(unsigned long start, unsigned long end) 668 { 669 unsigned long new_start, new_end; 670 671 BUG_ON(start < BCM_SYS_EMI_START_ADDR); 672 673 if (unlikely(end <= start)) 674 return; 675 676 if ((end - start) >= l2x0_size) { 677 l2x0_flush_all(); 678 return; 679 } 680 681 new_start = bcm_l2_phys_addr(start); 682 new_end = bcm_l2_phys_addr(end); 683 684 /* normal case, no cross section between start and end */ 685 if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { 686 l2x0_flush_range(new_start, new_end); 687 return; 688 } 689 690 /* They cross sections, so it can only be a cross from section 691 * 2 to section 3 692 */ 693 l2x0_flush_range(new_start, 694 bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); 695 l2x0_flush_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), 696 new_end); 697 } 698 699 static void __init l2x0_of_parse(const struct device_node *np, 700 u32 *aux_val, u32 *aux_mask) 701 { 702 u32 data[2] = { 0, 0 }; 703 u32 tag = 0; 704 u32 dirty = 0; 705 u32 val = 0, mask = 0; 706 707 of_property_read_u32(np, "arm,tag-latency", &tag); 708 if (tag) { 709 mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK; 710 val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT; 711 } 712 713 of_property_read_u32_array(np, "arm,data-latency", 714 data, ARRAY_SIZE(data)); 715 if (data[0] && data[1]) { 716 mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK | 717 L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK; 718 val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) | 719 ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT); 720 } 721 722 of_property_read_u32(np, "arm,dirty-latency", &dirty); 723 if (dirty) { 724 mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK; 725 val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT; 726 } 727 728 *aux_val &= ~mask; 729 *aux_val |= val; 730 *aux_mask &= ~mask; 731 } 732 733 static void __init pl310_of_parse(const struct device_node *np, 734 u32 *aux_val, u32 *aux_mask) 735 { 736 u32 data[3] = { 0, 0, 0 }; 737 u32 tag[3] = { 0, 0, 0 }; 738 u32 filter[2] = { 0, 0 }; 739 740 of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag)); 741 if (tag[0] && tag[1] && tag[2]) 742 writel_relaxed( 743 ((tag[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) | 744 ((tag[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) | 745 ((tag[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT), 746 l2x0_base + L2X0_TAG_LATENCY_CTRL); 747 748 of_property_read_u32_array(np, "arm,data-latency", 749 data, ARRAY_SIZE(data)); 750 if (data[0] && data[1] && data[2]) 751 writel_relaxed( 752 ((data[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) | 753 ((data[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) | 754 ((data[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT), 755 l2x0_base + L2X0_DATA_LATENCY_CTRL); 756 757 of_property_read_u32_array(np, "arm,filter-ranges", 758 filter, ARRAY_SIZE(filter)); 759 if (filter[1]) { 760 writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M), 761 l2x0_base + L2X0_ADDR_FILTER_END); 762 writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN, 763 l2x0_base + L2X0_ADDR_FILTER_START); 764 } 765 } 766 767 static void __init pl310_save(void) 768 { 769 u32 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) & 770 L2X0_CACHE_ID_RTL_MASK; 771 772 l2x0_saved_regs.tag_latency = readl_relaxed(l2x0_base + 773 L2X0_TAG_LATENCY_CTRL); 774 l2x0_saved_regs.data_latency = readl_relaxed(l2x0_base + 775 L2X0_DATA_LATENCY_CTRL); 776 l2x0_saved_regs.filter_end = readl_relaxed(l2x0_base + 777 L2X0_ADDR_FILTER_END); 778 l2x0_saved_regs.filter_start = readl_relaxed(l2x0_base + 779 L2X0_ADDR_FILTER_START); 780 781 if (l2x0_revision >= L310_CACHE_ID_RTL_R2P0) { 782 /* 783 * From r2p0, there is Prefetch offset/control register 784 */ 785 l2x0_saved_regs.prefetch_ctrl = readl_relaxed(l2x0_base + 786 L2X0_PREFETCH_CTRL); 787 /* 788 * From r3p0, there is Power control register 789 */ 790 if (l2x0_revision >= L310_CACHE_ID_RTL_R3P0) 791 l2x0_saved_regs.pwr_ctrl = readl_relaxed(l2x0_base + 792 L2X0_POWER_CTRL); 793 } 794 } 795 796 static void aurora_save(void) 797 { 798 l2x0_saved_regs.ctrl = readl_relaxed(l2x0_base + L2X0_CTRL); 799 l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); 800 } 801 802 static void __init tauros3_save(void) 803 { 804 l2x0_saved_regs.aux2_ctrl = 805 readl_relaxed(l2x0_base + TAUROS3_AUX2_CTRL); 806 l2x0_saved_regs.prefetch_ctrl = 807 readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL); 808 } 809 810 static void l2x0_resume(void) 811 { 812 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { 813 /* restore aux ctrl and enable l2 */ 814 l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID)); 815 816 writel_relaxed(l2x0_saved_regs.aux_ctrl, l2x0_base + 817 L2X0_AUX_CTRL); 818 819 l2x0_inv_all(); 820 821 writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL); 822 } 823 } 824 825 static void pl310_resume(void) 826 { 827 u32 l2x0_revision; 828 829 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { 830 /* restore pl310 setup */ 831 writel_relaxed(l2x0_saved_regs.tag_latency, 832 l2x0_base + L2X0_TAG_LATENCY_CTRL); 833 writel_relaxed(l2x0_saved_regs.data_latency, 834 l2x0_base + L2X0_DATA_LATENCY_CTRL); 835 writel_relaxed(l2x0_saved_regs.filter_end, 836 l2x0_base + L2X0_ADDR_FILTER_END); 837 writel_relaxed(l2x0_saved_regs.filter_start, 838 l2x0_base + L2X0_ADDR_FILTER_START); 839 840 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) & 841 L2X0_CACHE_ID_RTL_MASK; 842 843 if (l2x0_revision >= L310_CACHE_ID_RTL_R2P0) { 844 writel_relaxed(l2x0_saved_regs.prefetch_ctrl, 845 l2x0_base + L2X0_PREFETCH_CTRL); 846 if (l2x0_revision >= L310_CACHE_ID_RTL_R3P0) 847 writel_relaxed(l2x0_saved_regs.pwr_ctrl, 848 l2x0_base + L2X0_POWER_CTRL); 849 } 850 } 851 852 l2x0_resume(); 853 } 854 855 static void aurora_resume(void) 856 { 857 if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { 858 writel_relaxed(l2x0_saved_regs.aux_ctrl, 859 l2x0_base + L2X0_AUX_CTRL); 860 writel_relaxed(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL); 861 } 862 } 863 864 static void tauros3_resume(void) 865 { 866 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { 867 writel_relaxed(l2x0_saved_regs.aux2_ctrl, 868 l2x0_base + TAUROS3_AUX2_CTRL); 869 writel_relaxed(l2x0_saved_regs.prefetch_ctrl, 870 l2x0_base + L2X0_PREFETCH_CTRL); 871 } 872 873 l2x0_resume(); 874 } 875 876 static void __init aurora_broadcast_l2_commands(void) 877 { 878 __u32 u; 879 /* Enable Broadcasting of cache commands to L2*/ 880 __asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r"(u)); 881 u |= AURORA_CTRL_FW; /* Set the FW bit */ 882 __asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" : : "r"(u)); 883 isb(); 884 } 885 886 static void __init aurora_of_parse(const struct device_node *np, 887 u32 *aux_val, u32 *aux_mask) 888 { 889 u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU; 890 u32 mask = AURORA_ACR_REPLACEMENT_MASK; 891 892 of_property_read_u32(np, "cache-id-part", 893 &cache_id_part_number_from_dt); 894 895 /* Determine and save the write policy */ 896 l2_wt_override = of_property_read_bool(np, "wt-override"); 897 898 if (l2_wt_override) { 899 val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY; 900 mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK; 901 } 902 903 *aux_val &= ~mask; 904 *aux_val |= val; 905 *aux_mask &= ~mask; 906 } 907 908 static const struct l2c_init_data of_pl310_data __initconst = { 909 .of_parse = pl310_of_parse, 910 .save = pl310_save, 911 .outer_cache = { 912 .inv_range = l2x0_inv_range, 913 .clean_range = l2x0_clean_range, 914 .flush_range = l2x0_flush_range, 915 .flush_all = l2x0_flush_all, 916 .disable = l2x0_disable, 917 .sync = l2x0_cache_sync, 918 .resume = pl310_resume, 919 }, 920 }; 921 922 static const struct l2c_init_data of_l2x0_data __initconst = { 923 .of_parse = l2x0_of_parse, 924 .outer_cache = { 925 .inv_range = l2x0_inv_range, 926 .clean_range = l2x0_clean_range, 927 .flush_range = l2x0_flush_range, 928 .flush_all = l2x0_flush_all, 929 .disable = l2x0_disable, 930 .sync = l2x0_cache_sync, 931 .resume = l2x0_resume, 932 }, 933 }; 934 935 static const struct l2c_init_data of_aurora_with_outer_data __initconst = { 936 .of_parse = aurora_of_parse, 937 .save = aurora_save, 938 .outer_cache = { 939 .inv_range = aurora_inv_range, 940 .clean_range = aurora_clean_range, 941 .flush_range = aurora_flush_range, 942 .flush_all = l2x0_flush_all, 943 .disable = l2x0_disable, 944 .sync = l2x0_cache_sync, 945 .resume = aurora_resume, 946 }, 947 }; 948 949 static const struct l2c_init_data of_aurora_no_outer_data __initconst = { 950 .of_parse = aurora_of_parse, 951 .save = aurora_save, 952 .outer_cache = { 953 .resume = aurora_resume, 954 }, 955 }; 956 957 static const struct l2c_init_data of_tauros3_data __initconst = { 958 .save = tauros3_save, 959 /* Tauros3 broadcasts L1 cache operations to L2 */ 960 .outer_cache = { 961 .resume = tauros3_resume, 962 }, 963 }; 964 965 static const struct l2c_init_data of_bcm_l2x0_data __initconst = { 966 .of_parse = pl310_of_parse, 967 .save = pl310_save, 968 .outer_cache = { 969 .inv_range = bcm_inv_range, 970 .clean_range = bcm_clean_range, 971 .flush_range = bcm_flush_range, 972 .flush_all = l2x0_flush_all, 973 .disable = l2x0_disable, 974 .sync = l2x0_cache_sync, 975 .resume = pl310_resume, 976 }, 977 }; 978 979 #define L2C_ID(name, fns) { .compatible = name, .data = (void *)&fns } 980 static const struct of_device_id l2x0_ids[] __initconst = { 981 L2C_ID("arm,l210-cache", of_l2x0_data), 982 L2C_ID("arm,l220-cache", of_l2x0_data), 983 L2C_ID("arm,pl310-cache", of_pl310_data), 984 L2C_ID("brcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data), 985 L2C_ID("marvell,aurora-outer-cache", of_aurora_with_outer_data), 986 L2C_ID("marvell,aurora-system-cache", of_aurora_no_outer_data), 987 L2C_ID("marvell,tauros3-cache", of_tauros3_data), 988 /* Deprecated IDs */ 989 L2C_ID("bcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data), 990 {} 991 }; 992 993 int __init l2x0_of_init(u32 aux_val, u32 aux_mask) 994 { 995 const struct l2c_init_data *data; 996 struct device_node *np; 997 struct resource res; 998 u32 cache_id; 999 1000 np = of_find_matching_node(NULL, l2x0_ids); 1001 if (!np) 1002 return -ENODEV; 1003 1004 if (of_address_to_resource(np, 0, &res)) 1005 return -ENODEV; 1006 1007 l2x0_base = ioremap(res.start, resource_size(&res)); 1008 if (!l2x0_base) 1009 return -ENOMEM; 1010 1011 l2x0_saved_regs.phy_base = res.start; 1012 1013 data = of_match_node(l2x0_ids, np)->data; 1014 1015 /* L2 configuration can only be changed if the cache is disabled */ 1016 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { 1017 if (data->of_parse) 1018 data->of_parse(np, &aux_val, &aux_mask); 1019 1020 /* For aurora cache in no outer mode select the 1021 * correct mode using the coprocessor*/ 1022 if (data == &of_aurora_no_outer_data) 1023 aurora_broadcast_l2_commands(); 1024 } 1025 1026 if (data->save) 1027 data->save(); 1028 1029 if (cache_id_part_number_from_dt) 1030 cache_id = cache_id_part_number_from_dt; 1031 else 1032 cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); 1033 1034 __l2c_init(data, aux_val, aux_mask, cache_id); 1035 1036 return 0; 1037 } 1038 #endif 1039