1 /* 2 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support 3 * 4 * Copyright (C) 2007 ARM Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 #include <linux/init.h> 20 #include <linux/spinlock.h> 21 #include <linux/io.h> 22 23 #include <asm/cacheflush.h> 24 #include <asm/hardware/cache-l2x0.h> 25 26 #define CACHE_LINE_SIZE 32 27 28 static void __iomem *l2x0_base; 29 static DEFINE_SPINLOCK(l2x0_lock); 30 static uint32_t l2x0_way_mask; /* Bitmask of active ways */ 31 32 static inline void cache_wait(void __iomem *reg, unsigned long mask) 33 { 34 /* wait for the operation to complete */ 35 while (readl(reg) & mask) 36 ; 37 } 38 39 static inline void cache_sync(void) 40 { 41 void __iomem *base = l2x0_base; 42 writel(0, base + L2X0_CACHE_SYNC); 43 cache_wait(base + L2X0_CACHE_SYNC, 1); 44 } 45 46 static inline void l2x0_clean_line(unsigned long addr) 47 { 48 void __iomem *base = l2x0_base; 49 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 50 writel(addr, base + L2X0_CLEAN_LINE_PA); 51 } 52 53 static inline void l2x0_inv_line(unsigned long addr) 54 { 55 void __iomem *base = l2x0_base; 56 cache_wait(base + L2X0_INV_LINE_PA, 1); 57 writel(addr, base + L2X0_INV_LINE_PA); 58 } 59 60 #ifdef CONFIG_PL310_ERRATA_588369 61 static void debug_writel(unsigned long val) 62 { 63 extern void omap_smc1(u32 fn, u32 arg); 64 65 /* 66 * Texas Instrument secure monitor api to modify the 67 * PL310 Debug Control Register. 68 */ 69 omap_smc1(0x100, val); 70 } 71 72 static inline void l2x0_flush_line(unsigned long addr) 73 { 74 void __iomem *base = l2x0_base; 75 76 /* Clean by PA followed by Invalidate by PA */ 77 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 78 writel(addr, base + L2X0_CLEAN_LINE_PA); 79 cache_wait(base + L2X0_INV_LINE_PA, 1); 80 writel(addr, base + L2X0_INV_LINE_PA); 81 } 82 #else 83 84 /* Optimised out for non-errata case */ 85 static inline void debug_writel(unsigned long val) 86 { 87 } 88 89 static inline void l2x0_flush_line(unsigned long addr) 90 { 91 void __iomem *base = l2x0_base; 92 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 93 writel(addr, base + L2X0_CLEAN_INV_LINE_PA); 94 } 95 #endif 96 97 static inline void l2x0_inv_all(void) 98 { 99 unsigned long flags; 100 101 /* invalidate all ways */ 102 spin_lock_irqsave(&l2x0_lock, flags); 103 writel(l2x0_way_mask, l2x0_base + L2X0_INV_WAY); 104 cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask); 105 cache_sync(); 106 spin_unlock_irqrestore(&l2x0_lock, flags); 107 } 108 109 static void l2x0_inv_range(unsigned long start, unsigned long end) 110 { 111 void __iomem *base = l2x0_base; 112 unsigned long flags; 113 114 spin_lock_irqsave(&l2x0_lock, flags); 115 if (start & (CACHE_LINE_SIZE - 1)) { 116 start &= ~(CACHE_LINE_SIZE - 1); 117 debug_writel(0x03); 118 l2x0_flush_line(start); 119 debug_writel(0x00); 120 start += CACHE_LINE_SIZE; 121 } 122 123 if (end & (CACHE_LINE_SIZE - 1)) { 124 end &= ~(CACHE_LINE_SIZE - 1); 125 debug_writel(0x03); 126 l2x0_flush_line(end); 127 debug_writel(0x00); 128 } 129 130 while (start < end) { 131 unsigned long blk_end = start + min(end - start, 4096UL); 132 133 while (start < blk_end) { 134 l2x0_inv_line(start); 135 start += CACHE_LINE_SIZE; 136 } 137 138 if (blk_end < end) { 139 spin_unlock_irqrestore(&l2x0_lock, flags); 140 spin_lock_irqsave(&l2x0_lock, flags); 141 } 142 } 143 cache_wait(base + L2X0_INV_LINE_PA, 1); 144 cache_sync(); 145 spin_unlock_irqrestore(&l2x0_lock, flags); 146 } 147 148 static void l2x0_clean_range(unsigned long start, unsigned long end) 149 { 150 void __iomem *base = l2x0_base; 151 unsigned long flags; 152 153 spin_lock_irqsave(&l2x0_lock, flags); 154 start &= ~(CACHE_LINE_SIZE - 1); 155 while (start < end) { 156 unsigned long blk_end = start + min(end - start, 4096UL); 157 158 while (start < blk_end) { 159 l2x0_clean_line(start); 160 start += CACHE_LINE_SIZE; 161 } 162 163 if (blk_end < end) { 164 spin_unlock_irqrestore(&l2x0_lock, flags); 165 spin_lock_irqsave(&l2x0_lock, flags); 166 } 167 } 168 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 169 cache_sync(); 170 spin_unlock_irqrestore(&l2x0_lock, flags); 171 } 172 173 static void l2x0_flush_range(unsigned long start, unsigned long end) 174 { 175 void __iomem *base = l2x0_base; 176 unsigned long flags; 177 178 spin_lock_irqsave(&l2x0_lock, flags); 179 start &= ~(CACHE_LINE_SIZE - 1); 180 while (start < end) { 181 unsigned long blk_end = start + min(end - start, 4096UL); 182 183 debug_writel(0x03); 184 while (start < blk_end) { 185 l2x0_flush_line(start); 186 start += CACHE_LINE_SIZE; 187 } 188 debug_writel(0x00); 189 190 if (blk_end < end) { 191 spin_unlock_irqrestore(&l2x0_lock, flags); 192 spin_lock_irqsave(&l2x0_lock, flags); 193 } 194 } 195 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 196 cache_sync(); 197 spin_unlock_irqrestore(&l2x0_lock, flags); 198 } 199 200 void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) 201 { 202 __u32 aux; 203 __u32 cache_id; 204 int ways; 205 const char *type; 206 207 l2x0_base = base; 208 209 cache_id = readl(l2x0_base + L2X0_CACHE_ID); 210 aux = readl(l2x0_base + L2X0_AUX_CTRL); 211 212 /* Determine the number of ways */ 213 switch (cache_id & L2X0_CACHE_ID_PART_MASK) { 214 case L2X0_CACHE_ID_PART_L310: 215 if (aux & (1 << 16)) 216 ways = 16; 217 else 218 ways = 8; 219 type = "L310"; 220 break; 221 case L2X0_CACHE_ID_PART_L210: 222 ways = (aux >> 13) & 0xf; 223 type = "L210"; 224 break; 225 default: 226 /* Assume unknown chips have 8 ways */ 227 ways = 8; 228 type = "L2x0 series"; 229 break; 230 } 231 232 l2x0_way_mask = (1 << ways) - 1; 233 234 /* 235 * Check if l2x0 controller is already enabled. 236 * If you are booting from non-secure mode 237 * accessing the below registers will fault. 238 */ 239 if (!(readl(l2x0_base + L2X0_CTRL) & 1)) { 240 241 /* l2x0 controller is disabled */ 242 aux &= aux_mask; 243 aux |= aux_val; 244 writel(aux, l2x0_base + L2X0_AUX_CTRL); 245 246 l2x0_inv_all(); 247 248 /* enable L2X0 */ 249 writel(1, l2x0_base + L2X0_CTRL); 250 } 251 252 outer_cache.inv_range = l2x0_inv_range; 253 outer_cache.clean_range = l2x0_clean_range; 254 outer_cache.flush_range = l2x0_flush_range; 255 256 printk(KERN_INFO "%s cache controller enabled\n", type); 257 printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n", 258 ways, cache_id, aux); 259 } 260