1 /* 2 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support 3 * 4 * Copyright (C) 2007 ARM Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 #include <linux/init.h> 20 #include <linux/spinlock.h> 21 #include <linux/io.h> 22 23 #include <asm/cacheflush.h> 24 #include <asm/hardware/cache-l2x0.h> 25 26 #define CACHE_LINE_SIZE 32 27 28 static void __iomem *l2x0_base; 29 static DEFINE_SPINLOCK(l2x0_lock); 30 static uint32_t l2x0_way_mask; /* Bitmask of active ways */ 31 static uint32_t l2x0_size; 32 33 static inline void cache_wait_way(void __iomem *reg, unsigned long mask) 34 { 35 /* wait for cache operation by line or way to complete */ 36 while (readl_relaxed(reg) & mask) 37 ; 38 } 39 40 #ifdef CONFIG_CACHE_PL310 41 static inline void cache_wait(void __iomem *reg, unsigned long mask) 42 { 43 /* cache operations by line are atomic on PL310 */ 44 } 45 #else 46 #define cache_wait cache_wait_way 47 #endif 48 49 static inline void cache_sync(void) 50 { 51 void __iomem *base = l2x0_base; 52 writel_relaxed(0, base + L2X0_CACHE_SYNC); 53 cache_wait(base + L2X0_CACHE_SYNC, 1); 54 } 55 56 static inline void l2x0_clean_line(unsigned long addr) 57 { 58 void __iomem *base = l2x0_base; 59 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 60 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA); 61 } 62 63 static inline void l2x0_inv_line(unsigned long addr) 64 { 65 void __iomem *base = l2x0_base; 66 cache_wait(base + L2X0_INV_LINE_PA, 1); 67 writel_relaxed(addr, base + L2X0_INV_LINE_PA); 68 } 69 70 #ifdef CONFIG_PL310_ERRATA_588369 71 static void debug_writel(unsigned long val) 72 { 73 extern void omap_smc1(u32 fn, u32 arg); 74 75 /* 76 * Texas Instrument secure monitor api to modify the 77 * PL310 Debug Control Register. 78 */ 79 omap_smc1(0x100, val); 80 } 81 82 static inline void l2x0_flush_line(unsigned long addr) 83 { 84 void __iomem *base = l2x0_base; 85 86 /* Clean by PA followed by Invalidate by PA */ 87 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 88 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA); 89 cache_wait(base + L2X0_INV_LINE_PA, 1); 90 writel_relaxed(addr, base + L2X0_INV_LINE_PA); 91 } 92 #else 93 94 /* Optimised out for non-errata case */ 95 static inline void debug_writel(unsigned long val) 96 { 97 } 98 99 static inline void l2x0_flush_line(unsigned long addr) 100 { 101 void __iomem *base = l2x0_base; 102 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 103 writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA); 104 } 105 #endif 106 107 static void l2x0_cache_sync(void) 108 { 109 unsigned long flags; 110 111 spin_lock_irqsave(&l2x0_lock, flags); 112 cache_sync(); 113 spin_unlock_irqrestore(&l2x0_lock, flags); 114 } 115 116 static void l2x0_flush_all(void) 117 { 118 unsigned long flags; 119 120 /* clean all ways */ 121 spin_lock_irqsave(&l2x0_lock, flags); 122 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY); 123 cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask); 124 cache_sync(); 125 spin_unlock_irqrestore(&l2x0_lock, flags); 126 } 127 128 static void l2x0_inv_all(void) 129 { 130 unsigned long flags; 131 132 /* invalidate all ways */ 133 spin_lock_irqsave(&l2x0_lock, flags); 134 /* Invalidating when L2 is enabled is a nono */ 135 BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1); 136 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY); 137 cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask); 138 cache_sync(); 139 spin_unlock_irqrestore(&l2x0_lock, flags); 140 } 141 142 static void l2x0_inv_range(unsigned long start, unsigned long end) 143 { 144 void __iomem *base = l2x0_base; 145 unsigned long flags; 146 147 spin_lock_irqsave(&l2x0_lock, flags); 148 if (start & (CACHE_LINE_SIZE - 1)) { 149 start &= ~(CACHE_LINE_SIZE - 1); 150 debug_writel(0x03); 151 l2x0_flush_line(start); 152 debug_writel(0x00); 153 start += CACHE_LINE_SIZE; 154 } 155 156 if (end & (CACHE_LINE_SIZE - 1)) { 157 end &= ~(CACHE_LINE_SIZE - 1); 158 debug_writel(0x03); 159 l2x0_flush_line(end); 160 debug_writel(0x00); 161 } 162 163 while (start < end) { 164 unsigned long blk_end = start + min(end - start, 4096UL); 165 166 while (start < blk_end) { 167 l2x0_inv_line(start); 168 start += CACHE_LINE_SIZE; 169 } 170 171 if (blk_end < end) { 172 spin_unlock_irqrestore(&l2x0_lock, flags); 173 spin_lock_irqsave(&l2x0_lock, flags); 174 } 175 } 176 cache_wait(base + L2X0_INV_LINE_PA, 1); 177 cache_sync(); 178 spin_unlock_irqrestore(&l2x0_lock, flags); 179 } 180 181 static void l2x0_clean_range(unsigned long start, unsigned long end) 182 { 183 void __iomem *base = l2x0_base; 184 unsigned long flags; 185 186 spin_lock_irqsave(&l2x0_lock, flags); 187 start &= ~(CACHE_LINE_SIZE - 1); 188 while (start < end) { 189 unsigned long blk_end = start + min(end - start, 4096UL); 190 191 while (start < blk_end) { 192 l2x0_clean_line(start); 193 start += CACHE_LINE_SIZE; 194 } 195 196 if (blk_end < end) { 197 spin_unlock_irqrestore(&l2x0_lock, flags); 198 spin_lock_irqsave(&l2x0_lock, flags); 199 } 200 } 201 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 202 cache_sync(); 203 spin_unlock_irqrestore(&l2x0_lock, flags); 204 } 205 206 static void l2x0_flush_range(unsigned long start, unsigned long end) 207 { 208 void __iomem *base = l2x0_base; 209 unsigned long flags; 210 211 spin_lock_irqsave(&l2x0_lock, flags); 212 start &= ~(CACHE_LINE_SIZE - 1); 213 while (start < end) { 214 unsigned long blk_end = start + min(end - start, 4096UL); 215 216 debug_writel(0x03); 217 while (start < blk_end) { 218 l2x0_flush_line(start); 219 start += CACHE_LINE_SIZE; 220 } 221 debug_writel(0x00); 222 223 if (blk_end < end) { 224 spin_unlock_irqrestore(&l2x0_lock, flags); 225 spin_lock_irqsave(&l2x0_lock, flags); 226 } 227 } 228 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 229 cache_sync(); 230 spin_unlock_irqrestore(&l2x0_lock, flags); 231 } 232 233 static void l2x0_disable(void) 234 { 235 unsigned long flags; 236 237 spin_lock_irqsave(&l2x0_lock, flags); 238 writel(0, l2x0_base + L2X0_CTRL); 239 spin_unlock_irqrestore(&l2x0_lock, flags); 240 } 241 242 void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) 243 { 244 __u32 aux; 245 __u32 cache_id; 246 __u32 way_size = 0; 247 int ways; 248 const char *type; 249 250 l2x0_base = base; 251 252 cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); 253 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); 254 255 aux &= aux_mask; 256 aux |= aux_val; 257 258 /* Determine the number of ways */ 259 switch (cache_id & L2X0_CACHE_ID_PART_MASK) { 260 case L2X0_CACHE_ID_PART_L310: 261 if (aux & (1 << 16)) 262 ways = 16; 263 else 264 ways = 8; 265 type = "L310"; 266 break; 267 case L2X0_CACHE_ID_PART_L210: 268 ways = (aux >> 13) & 0xf; 269 type = "L210"; 270 break; 271 default: 272 /* Assume unknown chips have 8 ways */ 273 ways = 8; 274 type = "L2x0 series"; 275 break; 276 } 277 278 l2x0_way_mask = (1 << ways) - 1; 279 280 /* 281 * L2 cache Size = Way size * Number of ways 282 */ 283 way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17; 284 way_size = 1 << (way_size + 3); 285 l2x0_size = ways * way_size * SZ_1K; 286 287 /* 288 * Check if l2x0 controller is already enabled. 289 * If you are booting from non-secure mode 290 * accessing the below registers will fault. 291 */ 292 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) { 293 294 /* l2x0 controller is disabled */ 295 writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL); 296 297 l2x0_inv_all(); 298 299 /* enable L2X0 */ 300 writel_relaxed(1, l2x0_base + L2X0_CTRL); 301 } 302 303 outer_cache.inv_range = l2x0_inv_range; 304 outer_cache.clean_range = l2x0_clean_range; 305 outer_cache.flush_range = l2x0_flush_range; 306 outer_cache.sync = l2x0_cache_sync; 307 outer_cache.flush_all = l2x0_flush_all; 308 outer_cache.inv_all = l2x0_inv_all; 309 outer_cache.disable = l2x0_disable; 310 311 printk(KERN_INFO "%s cache controller enabled\n", type); 312 printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", 313 ways, cache_id, aux, l2x0_size); 314 } 315