1 /* 2 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support 3 * 4 * Copyright (C) 2007 ARM Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 #include <linux/init.h> 20 #include <linux/spinlock.h> 21 #include <linux/io.h> 22 23 #include <asm/cacheflush.h> 24 #include <asm/hardware/cache-l2x0.h> 25 26 #define CACHE_LINE_SIZE 32 27 28 static void __iomem *l2x0_base; 29 static DEFINE_SPINLOCK(l2x0_lock); 30 31 static inline void cache_wait(void __iomem *reg, unsigned long mask) 32 { 33 /* wait for the operation to complete */ 34 while (readl(reg) & mask) 35 ; 36 } 37 38 static inline void cache_sync(void) 39 { 40 void __iomem *base = l2x0_base; 41 writel(0, base + L2X0_CACHE_SYNC); 42 cache_wait(base + L2X0_CACHE_SYNC, 1); 43 } 44 45 static inline void l2x0_clean_line(unsigned long addr) 46 { 47 void __iomem *base = l2x0_base; 48 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 49 writel(addr, base + L2X0_CLEAN_LINE_PA); 50 } 51 52 static inline void l2x0_inv_line(unsigned long addr) 53 { 54 void __iomem *base = l2x0_base; 55 cache_wait(base + L2X0_INV_LINE_PA, 1); 56 writel(addr, base + L2X0_INV_LINE_PA); 57 } 58 59 static inline void l2x0_flush_line(unsigned long addr) 60 { 61 void __iomem *base = l2x0_base; 62 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 63 writel(addr, base + L2X0_CLEAN_INV_LINE_PA); 64 } 65 66 static inline void l2x0_inv_all(void) 67 { 68 unsigned long flags; 69 70 /* invalidate all ways */ 71 spin_lock_irqsave(&l2x0_lock, flags); 72 writel(0xff, l2x0_base + L2X0_INV_WAY); 73 cache_wait(l2x0_base + L2X0_INV_WAY, 0xff); 74 cache_sync(); 75 spin_unlock_irqrestore(&l2x0_lock, flags); 76 } 77 78 static void l2x0_inv_range(unsigned long start, unsigned long end) 79 { 80 void __iomem *base = l2x0_base; 81 unsigned long flags; 82 83 spin_lock_irqsave(&l2x0_lock, flags); 84 if (start & (CACHE_LINE_SIZE - 1)) { 85 start &= ~(CACHE_LINE_SIZE - 1); 86 l2x0_flush_line(start); 87 start += CACHE_LINE_SIZE; 88 } 89 90 if (end & (CACHE_LINE_SIZE - 1)) { 91 end &= ~(CACHE_LINE_SIZE - 1); 92 l2x0_flush_line(end); 93 } 94 95 while (start < end) { 96 unsigned long blk_end = start + min(end - start, 4096UL); 97 98 while (start < blk_end) { 99 l2x0_inv_line(start); 100 start += CACHE_LINE_SIZE; 101 } 102 103 if (blk_end < end) { 104 spin_unlock_irqrestore(&l2x0_lock, flags); 105 spin_lock_irqsave(&l2x0_lock, flags); 106 } 107 } 108 cache_wait(base + L2X0_INV_LINE_PA, 1); 109 cache_sync(); 110 spin_unlock_irqrestore(&l2x0_lock, flags); 111 } 112 113 static void l2x0_clean_range(unsigned long start, unsigned long end) 114 { 115 void __iomem *base = l2x0_base; 116 unsigned long flags; 117 118 spin_lock_irqsave(&l2x0_lock, flags); 119 start &= ~(CACHE_LINE_SIZE - 1); 120 while (start < end) { 121 unsigned long blk_end = start + min(end - start, 4096UL); 122 123 while (start < blk_end) { 124 l2x0_clean_line(start); 125 start += CACHE_LINE_SIZE; 126 } 127 128 if (blk_end < end) { 129 spin_unlock_irqrestore(&l2x0_lock, flags); 130 spin_lock_irqsave(&l2x0_lock, flags); 131 } 132 } 133 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 134 cache_sync(); 135 spin_unlock_irqrestore(&l2x0_lock, flags); 136 } 137 138 static void l2x0_flush_range(unsigned long start, unsigned long end) 139 { 140 void __iomem *base = l2x0_base; 141 unsigned long flags; 142 143 spin_lock_irqsave(&l2x0_lock, flags); 144 start &= ~(CACHE_LINE_SIZE - 1); 145 while (start < end) { 146 unsigned long blk_end = start + min(end - start, 4096UL); 147 148 while (start < blk_end) { 149 l2x0_flush_line(start); 150 start += CACHE_LINE_SIZE; 151 } 152 153 if (blk_end < end) { 154 spin_unlock_irqrestore(&l2x0_lock, flags); 155 spin_lock_irqsave(&l2x0_lock, flags); 156 } 157 } 158 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 159 cache_sync(); 160 spin_unlock_irqrestore(&l2x0_lock, flags); 161 } 162 163 void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) 164 { 165 __u32 aux; 166 167 l2x0_base = base; 168 169 /* 170 * Check if l2x0 controller is already enabled. 171 * If you are booting from non-secure mode 172 * accessing the below registers will fault. 173 */ 174 if (!(readl(l2x0_base + L2X0_CTRL) & 1)) { 175 176 /* l2x0 controller is disabled */ 177 178 aux = readl(l2x0_base + L2X0_AUX_CTRL); 179 aux &= aux_mask; 180 aux |= aux_val; 181 writel(aux, l2x0_base + L2X0_AUX_CTRL); 182 183 l2x0_inv_all(); 184 185 /* enable L2X0 */ 186 writel(1, l2x0_base + L2X0_CTRL); 187 } 188 189 outer_cache.inv_range = l2x0_inv_range; 190 outer_cache.clean_range = l2x0_clean_range; 191 outer_cache.flush_range = l2x0_flush_range; 192 193 printk(KERN_INFO "L2X0 cache controller enabled\n"); 194 } 195