1 /* 2 * arch/arm/mm/cache-l2x0.c - L210/L220/L310 cache controller support 3 * 4 * Copyright (C) 2007 ARM Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 #include <linux/cpu.h> 20 #include <linux/err.h> 21 #include <linux/init.h> 22 #include <linux/smp.h> 23 #include <linux/spinlock.h> 24 #include <linux/log2.h> 25 #include <linux/io.h> 26 #include <linux/of.h> 27 #include <linux/of_address.h> 28 29 #include <asm/cacheflush.h> 30 #include <asm/cp15.h> 31 #include <asm/cputype.h> 32 #include <asm/hardware/cache-l2x0.h> 33 #include "cache-tauros3.h" 34 #include "cache-aurora-l2.h" 35 36 struct l2c_init_data { 37 const char *type; 38 unsigned way_size_0; 39 unsigned num_lock; 40 void (*of_parse)(const struct device_node *, u32 *, u32 *); 41 void (*enable)(void __iomem *, unsigned); 42 void (*fixup)(void __iomem *, u32, struct outer_cache_fns *); 43 void (*save)(void __iomem *); 44 void (*configure)(void __iomem *); 45 void (*unlock)(void __iomem *, unsigned); 46 struct outer_cache_fns outer_cache; 47 }; 48 49 #define CACHE_LINE_SIZE 32 50 51 static void __iomem *l2x0_base; 52 static const struct l2c_init_data *l2x0_data; 53 static DEFINE_RAW_SPINLOCK(l2x0_lock); 54 static u32 l2x0_way_mask; /* Bitmask of active ways */ 55 static u32 l2x0_size; 56 static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; 57 58 struct l2x0_regs l2x0_saved_regs; 59 60 /* 61 * Common code for all cache controllers. 62 */ 63 static inline void l2c_wait_mask(void __iomem *reg, unsigned long mask) 64 { 65 /* wait for cache operation by line or way to complete */ 66 while (readl_relaxed(reg) & mask) 67 cpu_relax(); 68 } 69 70 /* 71 * By default, we write directly to secure registers. Platforms must 72 * override this if they are running non-secure. 73 */ 74 static void l2c_write_sec(unsigned long val, void __iomem *base, unsigned reg) 75 { 76 if (val == readl_relaxed(base + reg)) 77 return; 78 if (outer_cache.write_sec) 79 outer_cache.write_sec(val, reg); 80 else 81 writel_relaxed(val, base + reg); 82 } 83 84 /* 85 * This should only be called when we have a requirement that the 86 * register be written due to a work-around, as platforms running 87 * in non-secure mode may not be able to access this register. 88 */ 89 static inline void l2c_set_debug(void __iomem *base, unsigned long val) 90 { 91 l2c_write_sec(val, base, L2X0_DEBUG_CTRL); 92 } 93 94 static void __l2c_op_way(void __iomem *reg) 95 { 96 writel_relaxed(l2x0_way_mask, reg); 97 l2c_wait_mask(reg, l2x0_way_mask); 98 } 99 100 static inline void l2c_unlock(void __iomem *base, unsigned num) 101 { 102 unsigned i; 103 104 for (i = 0; i < num; i++) { 105 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE + 106 i * L2X0_LOCKDOWN_STRIDE); 107 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE + 108 i * L2X0_LOCKDOWN_STRIDE); 109 } 110 } 111 112 static void l2c_configure(void __iomem *base) 113 { 114 l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL); 115 } 116 117 /* 118 * Enable the L2 cache controller. This function must only be 119 * called when the cache controller is known to be disabled. 120 */ 121 static void l2c_enable(void __iomem *base, unsigned num_lock) 122 { 123 unsigned long flags; 124 125 if (outer_cache.configure) 126 outer_cache.configure(&l2x0_saved_regs); 127 else 128 l2x0_data->configure(base); 129 130 l2x0_data->unlock(base, num_lock); 131 132 local_irq_save(flags); 133 __l2c_op_way(base + L2X0_INV_WAY); 134 writel_relaxed(0, base + sync_reg_offset); 135 l2c_wait_mask(base + sync_reg_offset, 1); 136 local_irq_restore(flags); 137 138 l2c_write_sec(L2X0_CTRL_EN, base, L2X0_CTRL); 139 } 140 141 static void l2c_disable(void) 142 { 143 void __iomem *base = l2x0_base; 144 145 outer_cache.flush_all(); 146 l2c_write_sec(0, base, L2X0_CTRL); 147 dsb(st); 148 } 149 150 static void l2c_save(void __iomem *base) 151 { 152 l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); 153 } 154 155 static void l2c_resume(void) 156 { 157 void __iomem *base = l2x0_base; 158 159 /* Do not touch the controller if already enabled. */ 160 if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) 161 l2c_enable(base, l2x0_data->num_lock); 162 } 163 164 /* 165 * L2C-210 specific code. 166 * 167 * The L2C-2x0 PA, set/way and sync operations are atomic, but we must 168 * ensure that no background operation is running. The way operations 169 * are all background tasks. 170 * 171 * While a background operation is in progress, any new operation is 172 * ignored (unspecified whether this causes an error.) Thankfully, not 173 * used on SMP. 174 * 175 * Never has a different sync register other than L2X0_CACHE_SYNC, but 176 * we use sync_reg_offset here so we can share some of this with L2C-310. 177 */ 178 static void __l2c210_cache_sync(void __iomem *base) 179 { 180 writel_relaxed(0, base + sync_reg_offset); 181 } 182 183 static void __l2c210_op_pa_range(void __iomem *reg, unsigned long start, 184 unsigned long end) 185 { 186 while (start < end) { 187 writel_relaxed(start, reg); 188 start += CACHE_LINE_SIZE; 189 } 190 } 191 192 static void l2c210_inv_range(unsigned long start, unsigned long end) 193 { 194 void __iomem *base = l2x0_base; 195 196 if (start & (CACHE_LINE_SIZE - 1)) { 197 start &= ~(CACHE_LINE_SIZE - 1); 198 writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA); 199 start += CACHE_LINE_SIZE; 200 } 201 202 if (end & (CACHE_LINE_SIZE - 1)) { 203 end &= ~(CACHE_LINE_SIZE - 1); 204 writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA); 205 } 206 207 __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end); 208 __l2c210_cache_sync(base); 209 } 210 211 static void l2c210_clean_range(unsigned long start, unsigned long end) 212 { 213 void __iomem *base = l2x0_base; 214 215 start &= ~(CACHE_LINE_SIZE - 1); 216 __l2c210_op_pa_range(base + L2X0_CLEAN_LINE_PA, start, end); 217 __l2c210_cache_sync(base); 218 } 219 220 static void l2c210_flush_range(unsigned long start, unsigned long end) 221 { 222 void __iomem *base = l2x0_base; 223 224 start &= ~(CACHE_LINE_SIZE - 1); 225 __l2c210_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA, start, end); 226 __l2c210_cache_sync(base); 227 } 228 229 static void l2c210_flush_all(void) 230 { 231 void __iomem *base = l2x0_base; 232 233 BUG_ON(!irqs_disabled()); 234 235 __l2c_op_way(base + L2X0_CLEAN_INV_WAY); 236 __l2c210_cache_sync(base); 237 } 238 239 static void l2c210_sync(void) 240 { 241 __l2c210_cache_sync(l2x0_base); 242 } 243 244 static const struct l2c_init_data l2c210_data __initconst = { 245 .type = "L2C-210", 246 .way_size_0 = SZ_8K, 247 .num_lock = 1, 248 .enable = l2c_enable, 249 .save = l2c_save, 250 .configure = l2c_configure, 251 .unlock = l2c_unlock, 252 .outer_cache = { 253 .inv_range = l2c210_inv_range, 254 .clean_range = l2c210_clean_range, 255 .flush_range = l2c210_flush_range, 256 .flush_all = l2c210_flush_all, 257 .disable = l2c_disable, 258 .sync = l2c210_sync, 259 .resume = l2c_resume, 260 }, 261 }; 262 263 /* 264 * L2C-220 specific code. 265 * 266 * All operations are background operations: they have to be waited for. 267 * Conflicting requests generate a slave error (which will cause an 268 * imprecise abort.) Never uses sync_reg_offset, so we hard-code the 269 * sync register here. 270 * 271 * However, we can re-use the l2c210_resume call. 272 */ 273 static inline void __l2c220_cache_sync(void __iomem *base) 274 { 275 writel_relaxed(0, base + L2X0_CACHE_SYNC); 276 l2c_wait_mask(base + L2X0_CACHE_SYNC, 1); 277 } 278 279 static void l2c220_op_way(void __iomem *base, unsigned reg) 280 { 281 unsigned long flags; 282 283 raw_spin_lock_irqsave(&l2x0_lock, flags); 284 __l2c_op_way(base + reg); 285 __l2c220_cache_sync(base); 286 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 287 } 288 289 static unsigned long l2c220_op_pa_range(void __iomem *reg, unsigned long start, 290 unsigned long end, unsigned long flags) 291 { 292 raw_spinlock_t *lock = &l2x0_lock; 293 294 while (start < end) { 295 unsigned long blk_end = start + min(end - start, 4096UL); 296 297 while (start < blk_end) { 298 l2c_wait_mask(reg, 1); 299 writel_relaxed(start, reg); 300 start += CACHE_LINE_SIZE; 301 } 302 303 if (blk_end < end) { 304 raw_spin_unlock_irqrestore(lock, flags); 305 raw_spin_lock_irqsave(lock, flags); 306 } 307 } 308 309 return flags; 310 } 311 312 static void l2c220_inv_range(unsigned long start, unsigned long end) 313 { 314 void __iomem *base = l2x0_base; 315 unsigned long flags; 316 317 raw_spin_lock_irqsave(&l2x0_lock, flags); 318 if ((start | end) & (CACHE_LINE_SIZE - 1)) { 319 if (start & (CACHE_LINE_SIZE - 1)) { 320 start &= ~(CACHE_LINE_SIZE - 1); 321 writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA); 322 start += CACHE_LINE_SIZE; 323 } 324 325 if (end & (CACHE_LINE_SIZE - 1)) { 326 end &= ~(CACHE_LINE_SIZE - 1); 327 l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1); 328 writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA); 329 } 330 } 331 332 flags = l2c220_op_pa_range(base + L2X0_INV_LINE_PA, 333 start, end, flags); 334 l2c_wait_mask(base + L2X0_INV_LINE_PA, 1); 335 __l2c220_cache_sync(base); 336 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 337 } 338 339 static void l2c220_clean_range(unsigned long start, unsigned long end) 340 { 341 void __iomem *base = l2x0_base; 342 unsigned long flags; 343 344 start &= ~(CACHE_LINE_SIZE - 1); 345 if ((end - start) >= l2x0_size) { 346 l2c220_op_way(base, L2X0_CLEAN_WAY); 347 return; 348 } 349 350 raw_spin_lock_irqsave(&l2x0_lock, flags); 351 flags = l2c220_op_pa_range(base + L2X0_CLEAN_LINE_PA, 352 start, end, flags); 353 l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1); 354 __l2c220_cache_sync(base); 355 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 356 } 357 358 static void l2c220_flush_range(unsigned long start, unsigned long end) 359 { 360 void __iomem *base = l2x0_base; 361 unsigned long flags; 362 363 start &= ~(CACHE_LINE_SIZE - 1); 364 if ((end - start) >= l2x0_size) { 365 l2c220_op_way(base, L2X0_CLEAN_INV_WAY); 366 return; 367 } 368 369 raw_spin_lock_irqsave(&l2x0_lock, flags); 370 flags = l2c220_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA, 371 start, end, flags); 372 l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1); 373 __l2c220_cache_sync(base); 374 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 375 } 376 377 static void l2c220_flush_all(void) 378 { 379 l2c220_op_way(l2x0_base, L2X0_CLEAN_INV_WAY); 380 } 381 382 static void l2c220_sync(void) 383 { 384 unsigned long flags; 385 386 raw_spin_lock_irqsave(&l2x0_lock, flags); 387 __l2c220_cache_sync(l2x0_base); 388 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 389 } 390 391 static void l2c220_enable(void __iomem *base, unsigned num_lock) 392 { 393 /* 394 * Always enable non-secure access to the lockdown registers - 395 * we write to them as part of the L2C enable sequence so they 396 * need to be accessible. 397 */ 398 l2x0_saved_regs.aux_ctrl |= L220_AUX_CTRL_NS_LOCKDOWN; 399 400 l2c_enable(base, num_lock); 401 } 402 403 static void l2c220_unlock(void __iomem *base, unsigned num_lock) 404 { 405 if (readl_relaxed(base + L2X0_AUX_CTRL) & L220_AUX_CTRL_NS_LOCKDOWN) 406 l2c_unlock(base, num_lock); 407 } 408 409 static const struct l2c_init_data l2c220_data = { 410 .type = "L2C-220", 411 .way_size_0 = SZ_8K, 412 .num_lock = 1, 413 .enable = l2c220_enable, 414 .save = l2c_save, 415 .configure = l2c_configure, 416 .unlock = l2c220_unlock, 417 .outer_cache = { 418 .inv_range = l2c220_inv_range, 419 .clean_range = l2c220_clean_range, 420 .flush_range = l2c220_flush_range, 421 .flush_all = l2c220_flush_all, 422 .disable = l2c_disable, 423 .sync = l2c220_sync, 424 .resume = l2c_resume, 425 }, 426 }; 427 428 /* 429 * L2C-310 specific code. 430 * 431 * Very similar to L2C-210, the PA, set/way and sync operations are atomic, 432 * and the way operations are all background tasks. However, issuing an 433 * operation while a background operation is in progress results in a 434 * SLVERR response. We can reuse: 435 * 436 * __l2c210_cache_sync (using sync_reg_offset) 437 * l2c210_sync 438 * l2c210_inv_range (if 588369 is not applicable) 439 * l2c210_clean_range 440 * l2c210_flush_range (if 588369 is not applicable) 441 * l2c210_flush_all (if 727915 is not applicable) 442 * 443 * Errata: 444 * 588369: PL310 R0P0->R1P0, fixed R2P0. 445 * Affects: all clean+invalidate operations 446 * clean and invalidate skips the invalidate step, so we need to issue 447 * separate operations. We also require the above debug workaround 448 * enclosing this code fragment on affected parts. On unaffected parts, 449 * we must not use this workaround without the debug register writes 450 * to avoid exposing a problem similar to 727915. 451 * 452 * 727915: PL310 R2P0->R3P0, fixed R3P1. 453 * Affects: clean+invalidate by way 454 * clean and invalidate by way runs in the background, and a store can 455 * hit the line between the clean operation and invalidate operation, 456 * resulting in the store being lost. 457 * 458 * 752271: PL310 R3P0->R3P1-50REL0, fixed R3P2. 459 * Affects: 8x64-bit (double fill) line fetches 460 * double fill line fetches can fail to cause dirty data to be evicted 461 * from the cache before the new data overwrites the second line. 462 * 463 * 753970: PL310 R3P0, fixed R3P1. 464 * Affects: sync 465 * prevents merging writes after the sync operation, until another L2C 466 * operation is performed (or a number of other conditions.) 467 * 468 * 769419: PL310 R0P0->R3P1, fixed R3P2. 469 * Affects: store buffer 470 * store buffer is not automatically drained. 471 */ 472 static void l2c310_inv_range_erratum(unsigned long start, unsigned long end) 473 { 474 void __iomem *base = l2x0_base; 475 476 if ((start | end) & (CACHE_LINE_SIZE - 1)) { 477 unsigned long flags; 478 479 /* Erratum 588369 for both clean+invalidate operations */ 480 raw_spin_lock_irqsave(&l2x0_lock, flags); 481 l2c_set_debug(base, 0x03); 482 483 if (start & (CACHE_LINE_SIZE - 1)) { 484 start &= ~(CACHE_LINE_SIZE - 1); 485 writel_relaxed(start, base + L2X0_CLEAN_LINE_PA); 486 writel_relaxed(start, base + L2X0_INV_LINE_PA); 487 start += CACHE_LINE_SIZE; 488 } 489 490 if (end & (CACHE_LINE_SIZE - 1)) { 491 end &= ~(CACHE_LINE_SIZE - 1); 492 writel_relaxed(end, base + L2X0_CLEAN_LINE_PA); 493 writel_relaxed(end, base + L2X0_INV_LINE_PA); 494 } 495 496 l2c_set_debug(base, 0x00); 497 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 498 } 499 500 __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end); 501 __l2c210_cache_sync(base); 502 } 503 504 static void l2c310_flush_range_erratum(unsigned long start, unsigned long end) 505 { 506 raw_spinlock_t *lock = &l2x0_lock; 507 unsigned long flags; 508 void __iomem *base = l2x0_base; 509 510 raw_spin_lock_irqsave(lock, flags); 511 while (start < end) { 512 unsigned long blk_end = start + min(end - start, 4096UL); 513 514 l2c_set_debug(base, 0x03); 515 while (start < blk_end) { 516 writel_relaxed(start, base + L2X0_CLEAN_LINE_PA); 517 writel_relaxed(start, base + L2X0_INV_LINE_PA); 518 start += CACHE_LINE_SIZE; 519 } 520 l2c_set_debug(base, 0x00); 521 522 if (blk_end < end) { 523 raw_spin_unlock_irqrestore(lock, flags); 524 raw_spin_lock_irqsave(lock, flags); 525 } 526 } 527 raw_spin_unlock_irqrestore(lock, flags); 528 __l2c210_cache_sync(base); 529 } 530 531 static void l2c310_flush_all_erratum(void) 532 { 533 void __iomem *base = l2x0_base; 534 unsigned long flags; 535 536 raw_spin_lock_irqsave(&l2x0_lock, flags); 537 l2c_set_debug(base, 0x03); 538 __l2c_op_way(base + L2X0_CLEAN_INV_WAY); 539 l2c_set_debug(base, 0x00); 540 __l2c210_cache_sync(base); 541 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 542 } 543 544 static void __init l2c310_save(void __iomem *base) 545 { 546 unsigned revision; 547 548 l2c_save(base); 549 550 l2x0_saved_regs.tag_latency = readl_relaxed(base + 551 L310_TAG_LATENCY_CTRL); 552 l2x0_saved_regs.data_latency = readl_relaxed(base + 553 L310_DATA_LATENCY_CTRL); 554 l2x0_saved_regs.filter_end = readl_relaxed(base + 555 L310_ADDR_FILTER_END); 556 l2x0_saved_regs.filter_start = readl_relaxed(base + 557 L310_ADDR_FILTER_START); 558 559 revision = readl_relaxed(base + L2X0_CACHE_ID) & 560 L2X0_CACHE_ID_RTL_MASK; 561 562 /* From r2p0, there is Prefetch offset/control register */ 563 if (revision >= L310_CACHE_ID_RTL_R2P0) 564 l2x0_saved_regs.prefetch_ctrl = readl_relaxed(base + 565 L310_PREFETCH_CTRL); 566 567 /* From r3p0, there is Power control register */ 568 if (revision >= L310_CACHE_ID_RTL_R3P0) 569 l2x0_saved_regs.pwr_ctrl = readl_relaxed(base + 570 L310_POWER_CTRL); 571 } 572 573 static void l2c310_configure(void __iomem *base) 574 { 575 unsigned revision; 576 577 l2c_configure(base); 578 579 /* restore pl310 setup */ 580 l2c_write_sec(l2x0_saved_regs.tag_latency, base, 581 L310_TAG_LATENCY_CTRL); 582 l2c_write_sec(l2x0_saved_regs.data_latency, base, 583 L310_DATA_LATENCY_CTRL); 584 l2c_write_sec(l2x0_saved_regs.filter_end, base, 585 L310_ADDR_FILTER_END); 586 l2c_write_sec(l2x0_saved_regs.filter_start, base, 587 L310_ADDR_FILTER_START); 588 589 revision = readl_relaxed(base + L2X0_CACHE_ID) & 590 L2X0_CACHE_ID_RTL_MASK; 591 592 if (revision >= L310_CACHE_ID_RTL_R2P0) 593 l2c_write_sec(l2x0_saved_regs.prefetch_ctrl, base, 594 L310_PREFETCH_CTRL); 595 if (revision >= L310_CACHE_ID_RTL_R3P0) 596 l2c_write_sec(l2x0_saved_regs.pwr_ctrl, base, 597 L310_POWER_CTRL); 598 } 599 600 static int l2c310_cpu_enable_flz(struct notifier_block *nb, unsigned long act, void *data) 601 { 602 switch (act & ~CPU_TASKS_FROZEN) { 603 case CPU_STARTING: 604 set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1)); 605 break; 606 case CPU_DYING: 607 set_auxcr(get_auxcr() & ~(BIT(3) | BIT(2) | BIT(1))); 608 break; 609 } 610 return NOTIFY_OK; 611 } 612 613 static void __init l2c310_enable(void __iomem *base, unsigned num_lock) 614 { 615 unsigned rev = readl_relaxed(base + L2X0_CACHE_ID) & L2X0_CACHE_ID_RTL_MASK; 616 bool cortex_a9 = read_cpuid_part() == ARM_CPU_PART_CORTEX_A9; 617 u32 aux = l2x0_saved_regs.aux_ctrl; 618 619 if (rev >= L310_CACHE_ID_RTL_R2P0) { 620 if (cortex_a9) { 621 aux |= L310_AUX_CTRL_EARLY_BRESP; 622 pr_info("L2C-310 enabling early BRESP for Cortex-A9\n"); 623 } else if (aux & L310_AUX_CTRL_EARLY_BRESP) { 624 pr_warn("L2C-310 early BRESP only supported with Cortex-A9\n"); 625 aux &= ~L310_AUX_CTRL_EARLY_BRESP; 626 } 627 } 628 629 if (cortex_a9) { 630 u32 aux_cur = readl_relaxed(base + L2X0_AUX_CTRL); 631 u32 acr = get_auxcr(); 632 633 pr_debug("Cortex-A9 ACR=0x%08x\n", acr); 634 635 if (acr & BIT(3) && !(aux_cur & L310_AUX_CTRL_FULL_LINE_ZERO)) 636 pr_err("L2C-310: full line of zeros enabled in Cortex-A9 but not L2C-310 - invalid\n"); 637 638 if (aux & L310_AUX_CTRL_FULL_LINE_ZERO && !(acr & BIT(3))) 639 pr_err("L2C-310: enabling full line of zeros but not enabled in Cortex-A9\n"); 640 641 if (!(aux & L310_AUX_CTRL_FULL_LINE_ZERO) && !outer_cache.write_sec) { 642 aux |= L310_AUX_CTRL_FULL_LINE_ZERO; 643 pr_info("L2C-310 full line of zeros enabled for Cortex-A9\n"); 644 } 645 } else if (aux & (L310_AUX_CTRL_FULL_LINE_ZERO | L310_AUX_CTRL_EARLY_BRESP)) { 646 pr_err("L2C-310: disabling Cortex-A9 specific feature bits\n"); 647 aux &= ~(L310_AUX_CTRL_FULL_LINE_ZERO | L310_AUX_CTRL_EARLY_BRESP); 648 } 649 650 /* r3p0 or later has power control register */ 651 if (rev >= L310_CACHE_ID_RTL_R3P0) 652 l2x0_saved_regs.pwr_ctrl = L310_DYNAMIC_CLK_GATING_EN | 653 L310_STNDBY_MODE_EN; 654 655 /* 656 * Always enable non-secure access to the lockdown registers - 657 * we write to them as part of the L2C enable sequence so they 658 * need to be accessible. 659 */ 660 l2x0_saved_regs.aux_ctrl = aux | L310_AUX_CTRL_NS_LOCKDOWN; 661 662 l2c_enable(base, num_lock); 663 664 /* Read back resulting AUX_CTRL value as it could have been altered. */ 665 aux = readl_relaxed(base + L2X0_AUX_CTRL); 666 667 if (aux & (L310_AUX_CTRL_DATA_PREFETCH | L310_AUX_CTRL_INSTR_PREFETCH)) { 668 u32 prefetch = readl_relaxed(base + L310_PREFETCH_CTRL); 669 670 pr_info("L2C-310 %s%s prefetch enabled, offset %u lines\n", 671 aux & L310_AUX_CTRL_INSTR_PREFETCH ? "I" : "", 672 aux & L310_AUX_CTRL_DATA_PREFETCH ? "D" : "", 673 1 + (prefetch & L310_PREFETCH_CTRL_OFFSET_MASK)); 674 } 675 676 /* r3p0 or later has power control register */ 677 if (rev >= L310_CACHE_ID_RTL_R3P0) { 678 u32 power_ctrl; 679 680 power_ctrl = readl_relaxed(base + L310_POWER_CTRL); 681 pr_info("L2C-310 dynamic clock gating %sabled, standby mode %sabled\n", 682 power_ctrl & L310_DYNAMIC_CLK_GATING_EN ? "en" : "dis", 683 power_ctrl & L310_STNDBY_MODE_EN ? "en" : "dis"); 684 } 685 686 if (aux & L310_AUX_CTRL_FULL_LINE_ZERO) { 687 set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1)); 688 cpu_notifier(l2c310_cpu_enable_flz, 0); 689 } 690 } 691 692 static void __init l2c310_fixup(void __iomem *base, u32 cache_id, 693 struct outer_cache_fns *fns) 694 { 695 unsigned revision = cache_id & L2X0_CACHE_ID_RTL_MASK; 696 const char *errata[8]; 697 unsigned n = 0; 698 699 if (IS_ENABLED(CONFIG_PL310_ERRATA_588369) && 700 revision < L310_CACHE_ID_RTL_R2P0 && 701 /* For bcm compatibility */ 702 fns->inv_range == l2c210_inv_range) { 703 fns->inv_range = l2c310_inv_range_erratum; 704 fns->flush_range = l2c310_flush_range_erratum; 705 errata[n++] = "588369"; 706 } 707 708 if (IS_ENABLED(CONFIG_PL310_ERRATA_727915) && 709 revision >= L310_CACHE_ID_RTL_R2P0 && 710 revision < L310_CACHE_ID_RTL_R3P1) { 711 fns->flush_all = l2c310_flush_all_erratum; 712 errata[n++] = "727915"; 713 } 714 715 if (revision >= L310_CACHE_ID_RTL_R3P0 && 716 revision < L310_CACHE_ID_RTL_R3P2) { 717 u32 val = l2x0_saved_regs.prefetch_ctrl; 718 /* I don't think bit23 is required here... but iMX6 does so */ 719 if (val & (BIT(30) | BIT(23))) { 720 val &= ~(BIT(30) | BIT(23)); 721 l2x0_saved_regs.prefetch_ctrl = val; 722 errata[n++] = "752271"; 723 } 724 } 725 726 if (IS_ENABLED(CONFIG_PL310_ERRATA_753970) && 727 revision == L310_CACHE_ID_RTL_R3P0) { 728 sync_reg_offset = L2X0_DUMMY_REG; 729 errata[n++] = "753970"; 730 } 731 732 if (IS_ENABLED(CONFIG_PL310_ERRATA_769419)) 733 errata[n++] = "769419"; 734 735 if (n) { 736 unsigned i; 737 738 pr_info("L2C-310 errat%s", n > 1 ? "a" : "um"); 739 for (i = 0; i < n; i++) 740 pr_cont(" %s", errata[i]); 741 pr_cont(" enabled\n"); 742 } 743 } 744 745 static void l2c310_disable(void) 746 { 747 /* 748 * If full-line-of-zeros is enabled, we must first disable it in the 749 * Cortex-A9 auxiliary control register before disabling the L2 cache. 750 */ 751 if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_FULL_LINE_ZERO) 752 set_auxcr(get_auxcr() & ~(BIT(3) | BIT(2) | BIT(1))); 753 754 l2c_disable(); 755 } 756 757 static void l2c310_resume(void) 758 { 759 l2c_resume(); 760 761 /* Re-enable full-line-of-zeros for Cortex-A9 */ 762 if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_FULL_LINE_ZERO) 763 set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1)); 764 } 765 766 static void l2c310_unlock(void __iomem *base, unsigned num_lock) 767 { 768 if (readl_relaxed(base + L2X0_AUX_CTRL) & L310_AUX_CTRL_NS_LOCKDOWN) 769 l2c_unlock(base, num_lock); 770 } 771 772 static const struct l2c_init_data l2c310_init_fns __initconst = { 773 .type = "L2C-310", 774 .way_size_0 = SZ_8K, 775 .num_lock = 8, 776 .enable = l2c310_enable, 777 .fixup = l2c310_fixup, 778 .save = l2c310_save, 779 .configure = l2c310_configure, 780 .unlock = l2c310_unlock, 781 .outer_cache = { 782 .inv_range = l2c210_inv_range, 783 .clean_range = l2c210_clean_range, 784 .flush_range = l2c210_flush_range, 785 .flush_all = l2c210_flush_all, 786 .disable = l2c310_disable, 787 .sync = l2c210_sync, 788 .resume = l2c310_resume, 789 }, 790 }; 791 792 static int __init __l2c_init(const struct l2c_init_data *data, 793 u32 aux_val, u32 aux_mask, u32 cache_id, bool nosync) 794 { 795 struct outer_cache_fns fns; 796 unsigned way_size_bits, ways; 797 u32 aux, old_aux; 798 799 /* 800 * Save the pointer globally so that callbacks which do not receive 801 * context from callers can access the structure. 802 */ 803 l2x0_data = kmemdup(data, sizeof(*data), GFP_KERNEL); 804 if (!l2x0_data) 805 return -ENOMEM; 806 807 /* 808 * Sanity check the aux values. aux_mask is the bits we preserve 809 * from reading the hardware register, and aux_val is the bits we 810 * set. 811 */ 812 if (aux_val & aux_mask) 813 pr_alert("L2C: platform provided aux values permit register corruption.\n"); 814 815 old_aux = aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); 816 aux &= aux_mask; 817 aux |= aux_val; 818 819 if (old_aux != aux) 820 pr_warn("L2C: DT/platform modifies aux control register: 0x%08x -> 0x%08x\n", 821 old_aux, aux); 822 823 /* Determine the number of ways */ 824 switch (cache_id & L2X0_CACHE_ID_PART_MASK) { 825 case L2X0_CACHE_ID_PART_L310: 826 if ((aux_val | ~aux_mask) & (L2C_AUX_CTRL_WAY_SIZE_MASK | L310_AUX_CTRL_ASSOCIATIVITY_16)) 827 pr_warn("L2C: DT/platform tries to modify or specify cache size\n"); 828 if (aux & (1 << 16)) 829 ways = 16; 830 else 831 ways = 8; 832 break; 833 834 case L2X0_CACHE_ID_PART_L210: 835 case L2X0_CACHE_ID_PART_L220: 836 ways = (aux >> 13) & 0xf; 837 break; 838 839 case AURORA_CACHE_ID: 840 ways = (aux >> 13) & 0xf; 841 ways = 2 << ((ways + 1) >> 2); 842 break; 843 844 default: 845 /* Assume unknown chips have 8 ways */ 846 ways = 8; 847 break; 848 } 849 850 l2x0_way_mask = (1 << ways) - 1; 851 852 /* 853 * way_size_0 is the size that a way_size value of zero would be 854 * given the calculation: way_size = way_size_0 << way_size_bits. 855 * So, if way_size_bits=0 is reserved, but way_size_bits=1 is 16k, 856 * then way_size_0 would be 8k. 857 * 858 * L2 cache size = number of ways * way size. 859 */ 860 way_size_bits = (aux & L2C_AUX_CTRL_WAY_SIZE_MASK) >> 861 L2C_AUX_CTRL_WAY_SIZE_SHIFT; 862 l2x0_size = ways * (data->way_size_0 << way_size_bits); 863 864 fns = data->outer_cache; 865 fns.write_sec = outer_cache.write_sec; 866 fns.configure = outer_cache.configure; 867 if (data->fixup) 868 data->fixup(l2x0_base, cache_id, &fns); 869 if (nosync) { 870 pr_info("L2C: disabling outer sync\n"); 871 fns.sync = NULL; 872 } 873 874 /* 875 * Check if l2x0 controller is already enabled. If we are booting 876 * in non-secure mode accessing the below registers will fault. 877 */ 878 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { 879 l2x0_saved_regs.aux_ctrl = aux; 880 881 data->enable(l2x0_base, data->num_lock); 882 } 883 884 outer_cache = fns; 885 886 /* 887 * It is strange to save the register state before initialisation, 888 * but hey, this is what the DT implementations decided to do. 889 */ 890 if (data->save) 891 data->save(l2x0_base); 892 893 /* Re-read it in case some bits are reserved. */ 894 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); 895 896 pr_info("%s cache controller enabled, %d ways, %d kB\n", 897 data->type, ways, l2x0_size >> 10); 898 pr_info("%s: CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n", 899 data->type, cache_id, aux); 900 901 return 0; 902 } 903 904 void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) 905 { 906 const struct l2c_init_data *data; 907 u32 cache_id; 908 909 l2x0_base = base; 910 911 cache_id = readl_relaxed(base + L2X0_CACHE_ID); 912 913 switch (cache_id & L2X0_CACHE_ID_PART_MASK) { 914 default: 915 case L2X0_CACHE_ID_PART_L210: 916 data = &l2c210_data; 917 break; 918 919 case L2X0_CACHE_ID_PART_L220: 920 data = &l2c220_data; 921 break; 922 923 case L2X0_CACHE_ID_PART_L310: 924 data = &l2c310_init_fns; 925 break; 926 } 927 928 /* Read back current (default) hardware configuration */ 929 if (data->save) 930 data->save(l2x0_base); 931 932 __l2c_init(data, aux_val, aux_mask, cache_id, false); 933 } 934 935 #ifdef CONFIG_OF 936 static int l2_wt_override; 937 938 /* Aurora don't have the cache ID register available, so we have to 939 * pass it though the device tree */ 940 static u32 cache_id_part_number_from_dt; 941 942 /** 943 * l2x0_cache_size_of_parse() - read cache size parameters from DT 944 * @np: the device tree node for the l2 cache 945 * @aux_val: pointer to machine-supplied auxilary register value, to 946 * be augmented by the call (bits to be set to 1) 947 * @aux_mask: pointer to machine-supplied auxilary register mask, to 948 * be augmented by the call (bits to be set to 0) 949 * @associativity: variable to return the calculated associativity in 950 * @max_way_size: the maximum size in bytes for the cache ways 951 */ 952 static int __init l2x0_cache_size_of_parse(const struct device_node *np, 953 u32 *aux_val, u32 *aux_mask, 954 u32 *associativity, 955 u32 max_way_size) 956 { 957 u32 mask = 0, val = 0; 958 u32 cache_size = 0, sets = 0; 959 u32 way_size_bits = 1; 960 u32 way_size = 0; 961 u32 block_size = 0; 962 u32 line_size = 0; 963 964 of_property_read_u32(np, "cache-size", &cache_size); 965 of_property_read_u32(np, "cache-sets", &sets); 966 of_property_read_u32(np, "cache-block-size", &block_size); 967 of_property_read_u32(np, "cache-line-size", &line_size); 968 969 if (!cache_size || !sets) 970 return -ENODEV; 971 972 /* All these l2 caches have the same line = block size actually */ 973 if (!line_size) { 974 if (block_size) { 975 /* If linesize is not given, it is equal to blocksize */ 976 line_size = block_size; 977 } else { 978 /* Fall back to known size */ 979 pr_warn("L2C OF: no cache block/line size given: " 980 "falling back to default size %d bytes\n", 981 CACHE_LINE_SIZE); 982 line_size = CACHE_LINE_SIZE; 983 } 984 } 985 986 if (line_size != CACHE_LINE_SIZE) 987 pr_warn("L2C OF: DT supplied line size %d bytes does " 988 "not match hardware line size of %d bytes\n", 989 line_size, 990 CACHE_LINE_SIZE); 991 992 /* 993 * Since: 994 * set size = cache size / sets 995 * ways = cache size / (sets * line size) 996 * way size = cache size / (cache size / (sets * line size)) 997 * way size = sets * line size 998 * associativity = ways = cache size / way size 999 */ 1000 way_size = sets * line_size; 1001 *associativity = cache_size / way_size; 1002 1003 if (way_size > max_way_size) { 1004 pr_err("L2C OF: set size %dKB is too large\n", way_size); 1005 return -EINVAL; 1006 } 1007 1008 pr_info("L2C OF: override cache size: %d bytes (%dKB)\n", 1009 cache_size, cache_size >> 10); 1010 pr_info("L2C OF: override line size: %d bytes\n", line_size); 1011 pr_info("L2C OF: override way size: %d bytes (%dKB)\n", 1012 way_size, way_size >> 10); 1013 pr_info("L2C OF: override associativity: %d\n", *associativity); 1014 1015 /* 1016 * Calculates the bits 17:19 to set for way size: 1017 * 512KB -> 6, 256KB -> 5, ... 16KB -> 1 1018 */ 1019 way_size_bits = ilog2(way_size >> 10) - 3; 1020 if (way_size_bits < 1 || way_size_bits > 6) { 1021 pr_err("L2C OF: cache way size illegal: %dKB is not mapped\n", 1022 way_size); 1023 return -EINVAL; 1024 } 1025 1026 mask |= L2C_AUX_CTRL_WAY_SIZE_MASK; 1027 val |= (way_size_bits << L2C_AUX_CTRL_WAY_SIZE_SHIFT); 1028 1029 *aux_val &= ~mask; 1030 *aux_val |= val; 1031 *aux_mask &= ~mask; 1032 1033 return 0; 1034 } 1035 1036 static void __init l2x0_of_parse(const struct device_node *np, 1037 u32 *aux_val, u32 *aux_mask) 1038 { 1039 u32 data[2] = { 0, 0 }; 1040 u32 tag = 0; 1041 u32 dirty = 0; 1042 u32 val = 0, mask = 0; 1043 u32 assoc; 1044 int ret; 1045 1046 of_property_read_u32(np, "arm,tag-latency", &tag); 1047 if (tag) { 1048 mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK; 1049 val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT; 1050 } 1051 1052 of_property_read_u32_array(np, "arm,data-latency", 1053 data, ARRAY_SIZE(data)); 1054 if (data[0] && data[1]) { 1055 mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK | 1056 L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK; 1057 val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) | 1058 ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT); 1059 } 1060 1061 of_property_read_u32(np, "arm,dirty-latency", &dirty); 1062 if (dirty) { 1063 mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK; 1064 val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT; 1065 } 1066 1067 if (of_property_read_bool(np, "arm,parity-enable")) { 1068 mask &= ~L2C_AUX_CTRL_PARITY_ENABLE; 1069 val |= L2C_AUX_CTRL_PARITY_ENABLE; 1070 } else if (of_property_read_bool(np, "arm,parity-disable")) { 1071 mask &= ~L2C_AUX_CTRL_PARITY_ENABLE; 1072 } 1073 1074 if (of_property_read_bool(np, "arm,shared-override")) { 1075 mask &= ~L2C_AUX_CTRL_SHARED_OVERRIDE; 1076 val |= L2C_AUX_CTRL_SHARED_OVERRIDE; 1077 } 1078 1079 ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_256K); 1080 if (ret) 1081 return; 1082 1083 if (assoc > 8) { 1084 pr_err("l2x0 of: cache setting yield too high associativity\n"); 1085 pr_err("l2x0 of: %d calculated, max 8\n", assoc); 1086 } else { 1087 mask |= L2X0_AUX_CTRL_ASSOC_MASK; 1088 val |= (assoc << L2X0_AUX_CTRL_ASSOC_SHIFT); 1089 } 1090 1091 *aux_val &= ~mask; 1092 *aux_val |= val; 1093 *aux_mask &= ~mask; 1094 } 1095 1096 static const struct l2c_init_data of_l2c210_data __initconst = { 1097 .type = "L2C-210", 1098 .way_size_0 = SZ_8K, 1099 .num_lock = 1, 1100 .of_parse = l2x0_of_parse, 1101 .enable = l2c_enable, 1102 .save = l2c_save, 1103 .configure = l2c_configure, 1104 .unlock = l2c_unlock, 1105 .outer_cache = { 1106 .inv_range = l2c210_inv_range, 1107 .clean_range = l2c210_clean_range, 1108 .flush_range = l2c210_flush_range, 1109 .flush_all = l2c210_flush_all, 1110 .disable = l2c_disable, 1111 .sync = l2c210_sync, 1112 .resume = l2c_resume, 1113 }, 1114 }; 1115 1116 static const struct l2c_init_data of_l2c220_data __initconst = { 1117 .type = "L2C-220", 1118 .way_size_0 = SZ_8K, 1119 .num_lock = 1, 1120 .of_parse = l2x0_of_parse, 1121 .enable = l2c220_enable, 1122 .save = l2c_save, 1123 .configure = l2c_configure, 1124 .unlock = l2c220_unlock, 1125 .outer_cache = { 1126 .inv_range = l2c220_inv_range, 1127 .clean_range = l2c220_clean_range, 1128 .flush_range = l2c220_flush_range, 1129 .flush_all = l2c220_flush_all, 1130 .disable = l2c_disable, 1131 .sync = l2c220_sync, 1132 .resume = l2c_resume, 1133 }, 1134 }; 1135 1136 static void __init l2c310_of_parse(const struct device_node *np, 1137 u32 *aux_val, u32 *aux_mask) 1138 { 1139 u32 data[3] = { 0, 0, 0 }; 1140 u32 tag[3] = { 0, 0, 0 }; 1141 u32 filter[2] = { 0, 0 }; 1142 u32 assoc; 1143 u32 prefetch; 1144 u32 val; 1145 int ret; 1146 1147 of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag)); 1148 if (tag[0] && tag[1] && tag[2]) 1149 l2x0_saved_regs.tag_latency = 1150 L310_LATENCY_CTRL_RD(tag[0] - 1) | 1151 L310_LATENCY_CTRL_WR(tag[1] - 1) | 1152 L310_LATENCY_CTRL_SETUP(tag[2] - 1); 1153 1154 of_property_read_u32_array(np, "arm,data-latency", 1155 data, ARRAY_SIZE(data)); 1156 if (data[0] && data[1] && data[2]) 1157 l2x0_saved_regs.data_latency = 1158 L310_LATENCY_CTRL_RD(data[0] - 1) | 1159 L310_LATENCY_CTRL_WR(data[1] - 1) | 1160 L310_LATENCY_CTRL_SETUP(data[2] - 1); 1161 1162 of_property_read_u32_array(np, "arm,filter-ranges", 1163 filter, ARRAY_SIZE(filter)); 1164 if (filter[1]) { 1165 l2x0_saved_regs.filter_end = 1166 ALIGN(filter[0] + filter[1], SZ_1M); 1167 l2x0_saved_regs.filter_start = (filter[0] & ~(SZ_1M - 1)) 1168 | L310_ADDR_FILTER_EN; 1169 } 1170 1171 ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_512K); 1172 if (!ret) { 1173 switch (assoc) { 1174 case 16: 1175 *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK; 1176 *aux_val |= L310_AUX_CTRL_ASSOCIATIVITY_16; 1177 *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK; 1178 break; 1179 case 8: 1180 *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK; 1181 *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK; 1182 break; 1183 default: 1184 pr_err("L2C-310 OF cache associativity %d invalid, only 8 or 16 permitted\n", 1185 assoc); 1186 break; 1187 } 1188 } 1189 1190 if (of_property_read_bool(np, "arm,shared-override")) { 1191 *aux_val |= L2C_AUX_CTRL_SHARED_OVERRIDE; 1192 *aux_mask &= ~L2C_AUX_CTRL_SHARED_OVERRIDE; 1193 } 1194 1195 if (of_property_read_bool(np, "arm,parity-enable")) { 1196 *aux_val |= L2C_AUX_CTRL_PARITY_ENABLE; 1197 *aux_mask &= ~L2C_AUX_CTRL_PARITY_ENABLE; 1198 } else if (of_property_read_bool(np, "arm,parity-disable")) { 1199 *aux_val &= ~L2C_AUX_CTRL_PARITY_ENABLE; 1200 *aux_mask &= ~L2C_AUX_CTRL_PARITY_ENABLE; 1201 } 1202 1203 prefetch = l2x0_saved_regs.prefetch_ctrl; 1204 1205 ret = of_property_read_u32(np, "arm,double-linefill", &val); 1206 if (ret == 0) { 1207 if (val) 1208 prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL; 1209 else 1210 prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL; 1211 } else if (ret != -EINVAL) { 1212 pr_err("L2C-310 OF arm,double-linefill property value is missing\n"); 1213 } 1214 1215 ret = of_property_read_u32(np, "arm,double-linefill-incr", &val); 1216 if (ret == 0) { 1217 if (val) 1218 prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_INCR; 1219 else 1220 prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL_INCR; 1221 } else if (ret != -EINVAL) { 1222 pr_err("L2C-310 OF arm,double-linefill-incr property value is missing\n"); 1223 } 1224 1225 ret = of_property_read_u32(np, "arm,double-linefill-wrap", &val); 1226 if (ret == 0) { 1227 if (!val) 1228 prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP; 1229 else 1230 prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP; 1231 } else if (ret != -EINVAL) { 1232 pr_err("L2C-310 OF arm,double-linefill-wrap property value is missing\n"); 1233 } 1234 1235 ret = of_property_read_u32(np, "arm,prefetch-drop", &val); 1236 if (ret == 0) { 1237 if (val) 1238 prefetch |= L310_PREFETCH_CTRL_PREFETCH_DROP; 1239 else 1240 prefetch &= ~L310_PREFETCH_CTRL_PREFETCH_DROP; 1241 } else if (ret != -EINVAL) { 1242 pr_err("L2C-310 OF arm,prefetch-drop property value is missing\n"); 1243 } 1244 1245 ret = of_property_read_u32(np, "arm,prefetch-offset", &val); 1246 if (ret == 0) { 1247 prefetch &= ~L310_PREFETCH_CTRL_OFFSET_MASK; 1248 prefetch |= val & L310_PREFETCH_CTRL_OFFSET_MASK; 1249 } else if (ret != -EINVAL) { 1250 pr_err("L2C-310 OF arm,prefetch-offset property value is missing\n"); 1251 } 1252 1253 ret = of_property_read_u32(np, "prefetch-data", &val); 1254 if (ret == 0) { 1255 if (val) 1256 prefetch |= L310_PREFETCH_CTRL_DATA_PREFETCH; 1257 else 1258 prefetch &= ~L310_PREFETCH_CTRL_DATA_PREFETCH; 1259 } else if (ret != -EINVAL) { 1260 pr_err("L2C-310 OF prefetch-data property value is missing\n"); 1261 } 1262 1263 ret = of_property_read_u32(np, "prefetch-instr", &val); 1264 if (ret == 0) { 1265 if (val) 1266 prefetch |= L310_PREFETCH_CTRL_INSTR_PREFETCH; 1267 else 1268 prefetch &= ~L310_PREFETCH_CTRL_INSTR_PREFETCH; 1269 } else if (ret != -EINVAL) { 1270 pr_err("L2C-310 OF prefetch-instr property value is missing\n"); 1271 } 1272 1273 l2x0_saved_regs.prefetch_ctrl = prefetch; 1274 } 1275 1276 static const struct l2c_init_data of_l2c310_data __initconst = { 1277 .type = "L2C-310", 1278 .way_size_0 = SZ_8K, 1279 .num_lock = 8, 1280 .of_parse = l2c310_of_parse, 1281 .enable = l2c310_enable, 1282 .fixup = l2c310_fixup, 1283 .save = l2c310_save, 1284 .configure = l2c310_configure, 1285 .unlock = l2c310_unlock, 1286 .outer_cache = { 1287 .inv_range = l2c210_inv_range, 1288 .clean_range = l2c210_clean_range, 1289 .flush_range = l2c210_flush_range, 1290 .flush_all = l2c210_flush_all, 1291 .disable = l2c310_disable, 1292 .sync = l2c210_sync, 1293 .resume = l2c310_resume, 1294 }, 1295 }; 1296 1297 /* 1298 * This is a variant of the of_l2c310_data with .sync set to 1299 * NULL. Outer sync operations are not needed when the system is I/O 1300 * coherent, and potentially harmful in certain situations (PCIe/PL310 1301 * deadlock on Armada 375/38x due to hardware I/O coherency). The 1302 * other operations are kept because they are infrequent (therefore do 1303 * not cause the deadlock in practice) and needed for secondary CPU 1304 * boot and other power management activities. 1305 */ 1306 static const struct l2c_init_data of_l2c310_coherent_data __initconst = { 1307 .type = "L2C-310 Coherent", 1308 .way_size_0 = SZ_8K, 1309 .num_lock = 8, 1310 .of_parse = l2c310_of_parse, 1311 .enable = l2c310_enable, 1312 .fixup = l2c310_fixup, 1313 .save = l2c310_save, 1314 .configure = l2c310_configure, 1315 .unlock = l2c310_unlock, 1316 .outer_cache = { 1317 .inv_range = l2c210_inv_range, 1318 .clean_range = l2c210_clean_range, 1319 .flush_range = l2c210_flush_range, 1320 .flush_all = l2c210_flush_all, 1321 .disable = l2c310_disable, 1322 .resume = l2c310_resume, 1323 }, 1324 }; 1325 1326 /* 1327 * Note that the end addresses passed to Linux primitives are 1328 * noninclusive, while the hardware cache range operations use 1329 * inclusive start and end addresses. 1330 */ 1331 static unsigned long aurora_range_end(unsigned long start, unsigned long end) 1332 { 1333 /* 1334 * Limit the number of cache lines processed at once, 1335 * since cache range operations stall the CPU pipeline 1336 * until completion. 1337 */ 1338 if (end > start + MAX_RANGE_SIZE) 1339 end = start + MAX_RANGE_SIZE; 1340 1341 /* 1342 * Cache range operations can't straddle a page boundary. 1343 */ 1344 if (end > PAGE_ALIGN(start+1)) 1345 end = PAGE_ALIGN(start+1); 1346 1347 return end; 1348 } 1349 1350 static void aurora_pa_range(unsigned long start, unsigned long end, 1351 unsigned long offset) 1352 { 1353 void __iomem *base = l2x0_base; 1354 unsigned long range_end; 1355 unsigned long flags; 1356 1357 /* 1358 * round start and end adresses up to cache line size 1359 */ 1360 start &= ~(CACHE_LINE_SIZE - 1); 1361 end = ALIGN(end, CACHE_LINE_SIZE); 1362 1363 /* 1364 * perform operation on all full cache lines between 'start' and 'end' 1365 */ 1366 while (start < end) { 1367 range_end = aurora_range_end(start, end); 1368 1369 raw_spin_lock_irqsave(&l2x0_lock, flags); 1370 writel_relaxed(start, base + AURORA_RANGE_BASE_ADDR_REG); 1371 writel_relaxed(range_end - CACHE_LINE_SIZE, base + offset); 1372 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 1373 1374 writel_relaxed(0, base + AURORA_SYNC_REG); 1375 start = range_end; 1376 } 1377 } 1378 static void aurora_inv_range(unsigned long start, unsigned long end) 1379 { 1380 aurora_pa_range(start, end, AURORA_INVAL_RANGE_REG); 1381 } 1382 1383 static void aurora_clean_range(unsigned long start, unsigned long end) 1384 { 1385 /* 1386 * If L2 is forced to WT, the L2 will always be clean and we 1387 * don't need to do anything here. 1388 */ 1389 if (!l2_wt_override) 1390 aurora_pa_range(start, end, AURORA_CLEAN_RANGE_REG); 1391 } 1392 1393 static void aurora_flush_range(unsigned long start, unsigned long end) 1394 { 1395 if (l2_wt_override) 1396 aurora_pa_range(start, end, AURORA_INVAL_RANGE_REG); 1397 else 1398 aurora_pa_range(start, end, AURORA_FLUSH_RANGE_REG); 1399 } 1400 1401 static void aurora_flush_all(void) 1402 { 1403 void __iomem *base = l2x0_base; 1404 unsigned long flags; 1405 1406 /* clean all ways */ 1407 raw_spin_lock_irqsave(&l2x0_lock, flags); 1408 __l2c_op_way(base + L2X0_CLEAN_INV_WAY); 1409 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 1410 1411 writel_relaxed(0, base + AURORA_SYNC_REG); 1412 } 1413 1414 static void aurora_cache_sync(void) 1415 { 1416 writel_relaxed(0, l2x0_base + AURORA_SYNC_REG); 1417 } 1418 1419 static void aurora_disable(void) 1420 { 1421 void __iomem *base = l2x0_base; 1422 unsigned long flags; 1423 1424 raw_spin_lock_irqsave(&l2x0_lock, flags); 1425 __l2c_op_way(base + L2X0_CLEAN_INV_WAY); 1426 writel_relaxed(0, base + AURORA_SYNC_REG); 1427 l2c_write_sec(0, base, L2X0_CTRL); 1428 dsb(st); 1429 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 1430 } 1431 1432 static void aurora_save(void __iomem *base) 1433 { 1434 l2x0_saved_regs.ctrl = readl_relaxed(base + L2X0_CTRL); 1435 l2x0_saved_regs.aux_ctrl = readl_relaxed(base + L2X0_AUX_CTRL); 1436 } 1437 1438 /* 1439 * For Aurora cache in no outer mode, enable via the CP15 coprocessor 1440 * broadcasting of cache commands to L2. 1441 */ 1442 static void __init aurora_enable_no_outer(void __iomem *base, 1443 unsigned num_lock) 1444 { 1445 u32 u; 1446 1447 asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u)); 1448 u |= AURORA_CTRL_FW; /* Set the FW bit */ 1449 asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u)); 1450 1451 isb(); 1452 1453 l2c_enable(base, num_lock); 1454 } 1455 1456 static void __init aurora_fixup(void __iomem *base, u32 cache_id, 1457 struct outer_cache_fns *fns) 1458 { 1459 sync_reg_offset = AURORA_SYNC_REG; 1460 } 1461 1462 static void __init aurora_of_parse(const struct device_node *np, 1463 u32 *aux_val, u32 *aux_mask) 1464 { 1465 u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU; 1466 u32 mask = AURORA_ACR_REPLACEMENT_MASK; 1467 1468 of_property_read_u32(np, "cache-id-part", 1469 &cache_id_part_number_from_dt); 1470 1471 /* Determine and save the write policy */ 1472 l2_wt_override = of_property_read_bool(np, "wt-override"); 1473 1474 if (l2_wt_override) { 1475 val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY; 1476 mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK; 1477 } 1478 1479 *aux_val &= ~mask; 1480 *aux_val |= val; 1481 *aux_mask &= ~mask; 1482 } 1483 1484 static const struct l2c_init_data of_aurora_with_outer_data __initconst = { 1485 .type = "Aurora", 1486 .way_size_0 = SZ_4K, 1487 .num_lock = 4, 1488 .of_parse = aurora_of_parse, 1489 .enable = l2c_enable, 1490 .fixup = aurora_fixup, 1491 .save = aurora_save, 1492 .configure = l2c_configure, 1493 .unlock = l2c_unlock, 1494 .outer_cache = { 1495 .inv_range = aurora_inv_range, 1496 .clean_range = aurora_clean_range, 1497 .flush_range = aurora_flush_range, 1498 .flush_all = aurora_flush_all, 1499 .disable = aurora_disable, 1500 .sync = aurora_cache_sync, 1501 .resume = l2c_resume, 1502 }, 1503 }; 1504 1505 static const struct l2c_init_data of_aurora_no_outer_data __initconst = { 1506 .type = "Aurora", 1507 .way_size_0 = SZ_4K, 1508 .num_lock = 4, 1509 .of_parse = aurora_of_parse, 1510 .enable = aurora_enable_no_outer, 1511 .fixup = aurora_fixup, 1512 .save = aurora_save, 1513 .configure = l2c_configure, 1514 .unlock = l2c_unlock, 1515 .outer_cache = { 1516 .resume = l2c_resume, 1517 }, 1518 }; 1519 1520 /* 1521 * For certain Broadcom SoCs, depending on the address range, different offsets 1522 * need to be added to the address before passing it to L2 for 1523 * invalidation/clean/flush 1524 * 1525 * Section Address Range Offset EMI 1526 * 1 0x00000000 - 0x3FFFFFFF 0x80000000 VC 1527 * 2 0x40000000 - 0xBFFFFFFF 0x40000000 SYS 1528 * 3 0xC0000000 - 0xFFFFFFFF 0x80000000 VC 1529 * 1530 * When the start and end addresses have crossed two different sections, we 1531 * need to break the L2 operation into two, each within its own section. 1532 * For example, if we need to invalidate addresses starts at 0xBFFF0000 and 1533 * ends at 0xC0001000, we need do invalidate 1) 0xBFFF0000 - 0xBFFFFFFF and 2) 1534 * 0xC0000000 - 0xC0001000 1535 * 1536 * Note 1: 1537 * By breaking a single L2 operation into two, we may potentially suffer some 1538 * performance hit, but keep in mind the cross section case is very rare 1539 * 1540 * Note 2: 1541 * We do not need to handle the case when the start address is in 1542 * Section 1 and the end address is in Section 3, since it is not a valid use 1543 * case 1544 * 1545 * Note 3: 1546 * Section 1 in practical terms can no longer be used on rev A2. Because of 1547 * that the code does not need to handle section 1 at all. 1548 * 1549 */ 1550 #define BCM_SYS_EMI_START_ADDR 0x40000000UL 1551 #define BCM_VC_EMI_SEC3_START_ADDR 0xC0000000UL 1552 1553 #define BCM_SYS_EMI_OFFSET 0x40000000UL 1554 #define BCM_VC_EMI_OFFSET 0x80000000UL 1555 1556 static inline int bcm_addr_is_sys_emi(unsigned long addr) 1557 { 1558 return (addr >= BCM_SYS_EMI_START_ADDR) && 1559 (addr < BCM_VC_EMI_SEC3_START_ADDR); 1560 } 1561 1562 static inline unsigned long bcm_l2_phys_addr(unsigned long addr) 1563 { 1564 if (bcm_addr_is_sys_emi(addr)) 1565 return addr + BCM_SYS_EMI_OFFSET; 1566 else 1567 return addr + BCM_VC_EMI_OFFSET; 1568 } 1569 1570 static void bcm_inv_range(unsigned long start, unsigned long end) 1571 { 1572 unsigned long new_start, new_end; 1573 1574 BUG_ON(start < BCM_SYS_EMI_START_ADDR); 1575 1576 if (unlikely(end <= start)) 1577 return; 1578 1579 new_start = bcm_l2_phys_addr(start); 1580 new_end = bcm_l2_phys_addr(end); 1581 1582 /* normal case, no cross section between start and end */ 1583 if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { 1584 l2c210_inv_range(new_start, new_end); 1585 return; 1586 } 1587 1588 /* They cross sections, so it can only be a cross from section 1589 * 2 to section 3 1590 */ 1591 l2c210_inv_range(new_start, 1592 bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); 1593 l2c210_inv_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), 1594 new_end); 1595 } 1596 1597 static void bcm_clean_range(unsigned long start, unsigned long end) 1598 { 1599 unsigned long new_start, new_end; 1600 1601 BUG_ON(start < BCM_SYS_EMI_START_ADDR); 1602 1603 if (unlikely(end <= start)) 1604 return; 1605 1606 new_start = bcm_l2_phys_addr(start); 1607 new_end = bcm_l2_phys_addr(end); 1608 1609 /* normal case, no cross section between start and end */ 1610 if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { 1611 l2c210_clean_range(new_start, new_end); 1612 return; 1613 } 1614 1615 /* They cross sections, so it can only be a cross from section 1616 * 2 to section 3 1617 */ 1618 l2c210_clean_range(new_start, 1619 bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); 1620 l2c210_clean_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), 1621 new_end); 1622 } 1623 1624 static void bcm_flush_range(unsigned long start, unsigned long end) 1625 { 1626 unsigned long new_start, new_end; 1627 1628 BUG_ON(start < BCM_SYS_EMI_START_ADDR); 1629 1630 if (unlikely(end <= start)) 1631 return; 1632 1633 if ((end - start) >= l2x0_size) { 1634 outer_cache.flush_all(); 1635 return; 1636 } 1637 1638 new_start = bcm_l2_phys_addr(start); 1639 new_end = bcm_l2_phys_addr(end); 1640 1641 /* normal case, no cross section between start and end */ 1642 if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { 1643 l2c210_flush_range(new_start, new_end); 1644 return; 1645 } 1646 1647 /* They cross sections, so it can only be a cross from section 1648 * 2 to section 3 1649 */ 1650 l2c210_flush_range(new_start, 1651 bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); 1652 l2c210_flush_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), 1653 new_end); 1654 } 1655 1656 /* Broadcom L2C-310 start from ARMs R3P2 or later, and require no fixups */ 1657 static const struct l2c_init_data of_bcm_l2x0_data __initconst = { 1658 .type = "BCM-L2C-310", 1659 .way_size_0 = SZ_8K, 1660 .num_lock = 8, 1661 .of_parse = l2c310_of_parse, 1662 .enable = l2c310_enable, 1663 .save = l2c310_save, 1664 .configure = l2c310_configure, 1665 .unlock = l2c310_unlock, 1666 .outer_cache = { 1667 .inv_range = bcm_inv_range, 1668 .clean_range = bcm_clean_range, 1669 .flush_range = bcm_flush_range, 1670 .flush_all = l2c210_flush_all, 1671 .disable = l2c310_disable, 1672 .sync = l2c210_sync, 1673 .resume = l2c310_resume, 1674 }, 1675 }; 1676 1677 static void __init tauros3_save(void __iomem *base) 1678 { 1679 l2c_save(base); 1680 1681 l2x0_saved_regs.aux2_ctrl = 1682 readl_relaxed(base + TAUROS3_AUX2_CTRL); 1683 l2x0_saved_regs.prefetch_ctrl = 1684 readl_relaxed(base + L310_PREFETCH_CTRL); 1685 } 1686 1687 static void tauros3_configure(void __iomem *base) 1688 { 1689 l2c_configure(base); 1690 writel_relaxed(l2x0_saved_regs.aux2_ctrl, 1691 base + TAUROS3_AUX2_CTRL); 1692 writel_relaxed(l2x0_saved_regs.prefetch_ctrl, 1693 base + L310_PREFETCH_CTRL); 1694 } 1695 1696 static const struct l2c_init_data of_tauros3_data __initconst = { 1697 .type = "Tauros3", 1698 .way_size_0 = SZ_8K, 1699 .num_lock = 8, 1700 .enable = l2c_enable, 1701 .save = tauros3_save, 1702 .configure = tauros3_configure, 1703 .unlock = l2c_unlock, 1704 /* Tauros3 broadcasts L1 cache operations to L2 */ 1705 .outer_cache = { 1706 .resume = l2c_resume, 1707 }, 1708 }; 1709 1710 #define L2C_ID(name, fns) { .compatible = name, .data = (void *)&fns } 1711 static const struct of_device_id l2x0_ids[] __initconst = { 1712 L2C_ID("arm,l210-cache", of_l2c210_data), 1713 L2C_ID("arm,l220-cache", of_l2c220_data), 1714 L2C_ID("arm,pl310-cache", of_l2c310_data), 1715 L2C_ID("brcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data), 1716 L2C_ID("marvell,aurora-outer-cache", of_aurora_with_outer_data), 1717 L2C_ID("marvell,aurora-system-cache", of_aurora_no_outer_data), 1718 L2C_ID("marvell,tauros3-cache", of_tauros3_data), 1719 /* Deprecated IDs */ 1720 L2C_ID("bcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data), 1721 {} 1722 }; 1723 1724 int __init l2x0_of_init(u32 aux_val, u32 aux_mask) 1725 { 1726 const struct l2c_init_data *data; 1727 struct device_node *np; 1728 struct resource res; 1729 u32 cache_id, old_aux; 1730 u32 cache_level = 2; 1731 bool nosync = false; 1732 1733 np = of_find_matching_node(NULL, l2x0_ids); 1734 if (!np) 1735 return -ENODEV; 1736 1737 if (of_address_to_resource(np, 0, &res)) 1738 return -ENODEV; 1739 1740 l2x0_base = ioremap(res.start, resource_size(&res)); 1741 if (!l2x0_base) 1742 return -ENOMEM; 1743 1744 l2x0_saved_regs.phy_base = res.start; 1745 1746 data = of_match_node(l2x0_ids, np)->data; 1747 1748 if (of_device_is_compatible(np, "arm,pl310-cache") && 1749 of_property_read_bool(np, "arm,io-coherent")) 1750 data = &of_l2c310_coherent_data; 1751 1752 old_aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); 1753 if (old_aux != ((old_aux & aux_mask) | aux_val)) { 1754 pr_warn("L2C: platform modifies aux control register: 0x%08x -> 0x%08x\n", 1755 old_aux, (old_aux & aux_mask) | aux_val); 1756 } else if (aux_mask != ~0U && aux_val != 0) { 1757 pr_alert("L2C: platform provided aux values match the hardware, so have no effect. Please remove them.\n"); 1758 } 1759 1760 /* All L2 caches are unified, so this property should be specified */ 1761 if (!of_property_read_bool(np, "cache-unified")) 1762 pr_err("L2C: device tree omits to specify unified cache\n"); 1763 1764 if (of_property_read_u32(np, "cache-level", &cache_level)) 1765 pr_err("L2C: device tree omits to specify cache-level\n"); 1766 1767 if (cache_level != 2) 1768 pr_err("L2C: device tree specifies invalid cache level\n"); 1769 1770 nosync = of_property_read_bool(np, "arm,outer-sync-disable"); 1771 1772 /* Read back current (default) hardware configuration */ 1773 if (data->save) 1774 data->save(l2x0_base); 1775 1776 /* L2 configuration can only be changed if the cache is disabled */ 1777 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) 1778 if (data->of_parse) 1779 data->of_parse(np, &aux_val, &aux_mask); 1780 1781 if (cache_id_part_number_from_dt) 1782 cache_id = cache_id_part_number_from_dt; 1783 else 1784 cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); 1785 1786 return __l2c_init(data, aux_val, aux_mask, cache_id, nosync); 1787 } 1788 #endif 1789