1 /* 2 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support 3 * 4 * Copyright (C) 2007 ARM Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 #include <linux/init.h> 20 #include <linux/spinlock.h> 21 #include <linux/io.h> 22 23 #include <asm/cacheflush.h> 24 #include <asm/hardware/cache-l2x0.h> 25 26 #define CACHE_LINE_SIZE 32 27 28 static void __iomem *l2x0_base; 29 static DEFINE_SPINLOCK(l2x0_lock); 30 static uint32_t l2x0_way_mask; /* Bitmask of active ways */ 31 32 static inline void cache_wait_way(void __iomem *reg, unsigned long mask) 33 { 34 /* wait for cache operation by line or way to complete */ 35 while (readl_relaxed(reg) & mask) 36 ; 37 } 38 39 #ifdef CONFIG_CACHE_PL310 40 static inline void cache_wait(void __iomem *reg, unsigned long mask) 41 { 42 /* cache operations by line are atomic on PL310 */ 43 } 44 #else 45 #define cache_wait cache_wait_way 46 #endif 47 48 static inline void cache_sync(void) 49 { 50 void __iomem *base = l2x0_base; 51 writel_relaxed(0, base + L2X0_CACHE_SYNC); 52 cache_wait(base + L2X0_CACHE_SYNC, 1); 53 } 54 55 static inline void l2x0_clean_line(unsigned long addr) 56 { 57 void __iomem *base = l2x0_base; 58 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 59 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA); 60 } 61 62 static inline void l2x0_inv_line(unsigned long addr) 63 { 64 void __iomem *base = l2x0_base; 65 cache_wait(base + L2X0_INV_LINE_PA, 1); 66 writel_relaxed(addr, base + L2X0_INV_LINE_PA); 67 } 68 69 #ifdef CONFIG_PL310_ERRATA_588369 70 static void debug_writel(unsigned long val) 71 { 72 extern void omap_smc1(u32 fn, u32 arg); 73 74 /* 75 * Texas Instrument secure monitor api to modify the 76 * PL310 Debug Control Register. 77 */ 78 omap_smc1(0x100, val); 79 } 80 81 static inline void l2x0_flush_line(unsigned long addr) 82 { 83 void __iomem *base = l2x0_base; 84 85 /* Clean by PA followed by Invalidate by PA */ 86 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 87 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA); 88 cache_wait(base + L2X0_INV_LINE_PA, 1); 89 writel_relaxed(addr, base + L2X0_INV_LINE_PA); 90 } 91 #else 92 93 /* Optimised out for non-errata case */ 94 static inline void debug_writel(unsigned long val) 95 { 96 } 97 98 static inline void l2x0_flush_line(unsigned long addr) 99 { 100 void __iomem *base = l2x0_base; 101 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 102 writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA); 103 } 104 #endif 105 106 static void l2x0_cache_sync(void) 107 { 108 unsigned long flags; 109 110 spin_lock_irqsave(&l2x0_lock, flags); 111 cache_sync(); 112 spin_unlock_irqrestore(&l2x0_lock, flags); 113 } 114 115 static void l2x0_flush_all(void) 116 { 117 unsigned long flags; 118 119 /* clean all ways */ 120 spin_lock_irqsave(&l2x0_lock, flags); 121 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY); 122 cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask); 123 cache_sync(); 124 spin_unlock_irqrestore(&l2x0_lock, flags); 125 } 126 127 static void l2x0_inv_all(void) 128 { 129 unsigned long flags; 130 131 /* invalidate all ways */ 132 spin_lock_irqsave(&l2x0_lock, flags); 133 /* Invalidating when L2 is enabled is a nono */ 134 BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1); 135 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY); 136 cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask); 137 cache_sync(); 138 spin_unlock_irqrestore(&l2x0_lock, flags); 139 } 140 141 static void l2x0_inv_range(unsigned long start, unsigned long end) 142 { 143 void __iomem *base = l2x0_base; 144 unsigned long flags; 145 146 spin_lock_irqsave(&l2x0_lock, flags); 147 if (start & (CACHE_LINE_SIZE - 1)) { 148 start &= ~(CACHE_LINE_SIZE - 1); 149 debug_writel(0x03); 150 l2x0_flush_line(start); 151 debug_writel(0x00); 152 start += CACHE_LINE_SIZE; 153 } 154 155 if (end & (CACHE_LINE_SIZE - 1)) { 156 end &= ~(CACHE_LINE_SIZE - 1); 157 debug_writel(0x03); 158 l2x0_flush_line(end); 159 debug_writel(0x00); 160 } 161 162 while (start < end) { 163 unsigned long blk_end = start + min(end - start, 4096UL); 164 165 while (start < blk_end) { 166 l2x0_inv_line(start); 167 start += CACHE_LINE_SIZE; 168 } 169 170 if (blk_end < end) { 171 spin_unlock_irqrestore(&l2x0_lock, flags); 172 spin_lock_irqsave(&l2x0_lock, flags); 173 } 174 } 175 cache_wait(base + L2X0_INV_LINE_PA, 1); 176 cache_sync(); 177 spin_unlock_irqrestore(&l2x0_lock, flags); 178 } 179 180 static void l2x0_clean_range(unsigned long start, unsigned long end) 181 { 182 void __iomem *base = l2x0_base; 183 unsigned long flags; 184 185 spin_lock_irqsave(&l2x0_lock, flags); 186 start &= ~(CACHE_LINE_SIZE - 1); 187 while (start < end) { 188 unsigned long blk_end = start + min(end - start, 4096UL); 189 190 while (start < blk_end) { 191 l2x0_clean_line(start); 192 start += CACHE_LINE_SIZE; 193 } 194 195 if (blk_end < end) { 196 spin_unlock_irqrestore(&l2x0_lock, flags); 197 spin_lock_irqsave(&l2x0_lock, flags); 198 } 199 } 200 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 201 cache_sync(); 202 spin_unlock_irqrestore(&l2x0_lock, flags); 203 } 204 205 static void l2x0_flush_range(unsigned long start, unsigned long end) 206 { 207 void __iomem *base = l2x0_base; 208 unsigned long flags; 209 210 spin_lock_irqsave(&l2x0_lock, flags); 211 start &= ~(CACHE_LINE_SIZE - 1); 212 while (start < end) { 213 unsigned long blk_end = start + min(end - start, 4096UL); 214 215 debug_writel(0x03); 216 while (start < blk_end) { 217 l2x0_flush_line(start); 218 start += CACHE_LINE_SIZE; 219 } 220 debug_writel(0x00); 221 222 if (blk_end < end) { 223 spin_unlock_irqrestore(&l2x0_lock, flags); 224 spin_lock_irqsave(&l2x0_lock, flags); 225 } 226 } 227 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 228 cache_sync(); 229 spin_unlock_irqrestore(&l2x0_lock, flags); 230 } 231 232 static void l2x0_disable(void) 233 { 234 unsigned long flags; 235 236 spin_lock_irqsave(&l2x0_lock, flags); 237 writel(0, l2x0_base + L2X0_CTRL); 238 spin_unlock_irqrestore(&l2x0_lock, flags); 239 } 240 241 void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) 242 { 243 __u32 aux; 244 __u32 cache_id; 245 int ways; 246 const char *type; 247 248 l2x0_base = base; 249 250 cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); 251 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); 252 253 aux &= aux_mask; 254 aux |= aux_val; 255 256 /* Determine the number of ways */ 257 switch (cache_id & L2X0_CACHE_ID_PART_MASK) { 258 case L2X0_CACHE_ID_PART_L310: 259 if (aux & (1 << 16)) 260 ways = 16; 261 else 262 ways = 8; 263 type = "L310"; 264 break; 265 case L2X0_CACHE_ID_PART_L210: 266 ways = (aux >> 13) & 0xf; 267 type = "L210"; 268 break; 269 default: 270 /* Assume unknown chips have 8 ways */ 271 ways = 8; 272 type = "L2x0 series"; 273 break; 274 } 275 276 l2x0_way_mask = (1 << ways) - 1; 277 278 /* 279 * Check if l2x0 controller is already enabled. 280 * If you are booting from non-secure mode 281 * accessing the below registers will fault. 282 */ 283 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) { 284 285 /* l2x0 controller is disabled */ 286 writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL); 287 288 l2x0_inv_all(); 289 290 /* enable L2X0 */ 291 writel_relaxed(1, l2x0_base + L2X0_CTRL); 292 } 293 294 outer_cache.inv_range = l2x0_inv_range; 295 outer_cache.clean_range = l2x0_clean_range; 296 outer_cache.flush_range = l2x0_flush_range; 297 outer_cache.sync = l2x0_cache_sync; 298 outer_cache.flush_all = l2x0_flush_all; 299 outer_cache.inv_all = l2x0_inv_all; 300 outer_cache.disable = l2x0_disable; 301 302 printk(KERN_INFO "%s cache controller enabled\n", type); 303 printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n", 304 ways, cache_id, aux); 305 } 306