1 /* 2 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support 3 * 4 * Copyright (C) 2007 ARM Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 #include <linux/init.h> 20 #include <linux/spinlock.h> 21 #include <linux/io.h> 22 23 #include <asm/cacheflush.h> 24 #include <asm/hardware/cache-l2x0.h> 25 26 #define CACHE_LINE_SIZE 32 27 28 static void __iomem *l2x0_base; 29 static DEFINE_SPINLOCK(l2x0_lock); 30 static uint32_t l2x0_way_mask; /* Bitmask of active ways */ 31 static uint32_t l2x0_size; 32 33 static inline void cache_wait_way(void __iomem *reg, unsigned long mask) 34 { 35 /* wait for cache operation by line or way to complete */ 36 while (readl_relaxed(reg) & mask) 37 ; 38 } 39 40 #ifdef CONFIG_CACHE_PL310 41 static inline void cache_wait(void __iomem *reg, unsigned long mask) 42 { 43 /* cache operations by line are atomic on PL310 */ 44 } 45 #else 46 #define cache_wait cache_wait_way 47 #endif 48 49 static inline void cache_sync(void) 50 { 51 void __iomem *base = l2x0_base; 52 writel_relaxed(0, base + L2X0_CACHE_SYNC); 53 cache_wait(base + L2X0_CACHE_SYNC, 1); 54 } 55 56 static inline void l2x0_clean_line(unsigned long addr) 57 { 58 void __iomem *base = l2x0_base; 59 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 60 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA); 61 } 62 63 static inline void l2x0_inv_line(unsigned long addr) 64 { 65 void __iomem *base = l2x0_base; 66 cache_wait(base + L2X0_INV_LINE_PA, 1); 67 writel_relaxed(addr, base + L2X0_INV_LINE_PA); 68 } 69 70 #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) 71 72 #define debug_writel(val) outer_cache.set_debug(val) 73 74 static void l2x0_set_debug(unsigned long val) 75 { 76 writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL); 77 } 78 #else 79 /* Optimised out for non-errata case */ 80 static inline void debug_writel(unsigned long val) 81 { 82 } 83 84 #define l2x0_set_debug NULL 85 #endif 86 87 #ifdef CONFIG_PL310_ERRATA_588369 88 static inline void l2x0_flush_line(unsigned long addr) 89 { 90 void __iomem *base = l2x0_base; 91 92 /* Clean by PA followed by Invalidate by PA */ 93 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 94 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA); 95 cache_wait(base + L2X0_INV_LINE_PA, 1); 96 writel_relaxed(addr, base + L2X0_INV_LINE_PA); 97 } 98 #else 99 100 static inline void l2x0_flush_line(unsigned long addr) 101 { 102 void __iomem *base = l2x0_base; 103 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 104 writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA); 105 } 106 #endif 107 108 static void l2x0_cache_sync(void) 109 { 110 unsigned long flags; 111 112 spin_lock_irqsave(&l2x0_lock, flags); 113 cache_sync(); 114 spin_unlock_irqrestore(&l2x0_lock, flags); 115 } 116 117 static void l2x0_flush_all(void) 118 { 119 unsigned long flags; 120 121 /* clean all ways */ 122 spin_lock_irqsave(&l2x0_lock, flags); 123 debug_writel(0x03); 124 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY); 125 cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask); 126 cache_sync(); 127 debug_writel(0x00); 128 spin_unlock_irqrestore(&l2x0_lock, flags); 129 } 130 131 static void l2x0_clean_all(void) 132 { 133 unsigned long flags; 134 135 /* clean all ways */ 136 spin_lock_irqsave(&l2x0_lock, flags); 137 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY); 138 cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask); 139 cache_sync(); 140 spin_unlock_irqrestore(&l2x0_lock, flags); 141 } 142 143 static void l2x0_inv_all(void) 144 { 145 unsigned long flags; 146 147 /* invalidate all ways */ 148 spin_lock_irqsave(&l2x0_lock, flags); 149 /* Invalidating when L2 is enabled is a nono */ 150 BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1); 151 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY); 152 cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask); 153 cache_sync(); 154 spin_unlock_irqrestore(&l2x0_lock, flags); 155 } 156 157 static void l2x0_inv_range(unsigned long start, unsigned long end) 158 { 159 void __iomem *base = l2x0_base; 160 unsigned long flags; 161 162 spin_lock_irqsave(&l2x0_lock, flags); 163 if (start & (CACHE_LINE_SIZE - 1)) { 164 start &= ~(CACHE_LINE_SIZE - 1); 165 debug_writel(0x03); 166 l2x0_flush_line(start); 167 debug_writel(0x00); 168 start += CACHE_LINE_SIZE; 169 } 170 171 if (end & (CACHE_LINE_SIZE - 1)) { 172 end &= ~(CACHE_LINE_SIZE - 1); 173 debug_writel(0x03); 174 l2x0_flush_line(end); 175 debug_writel(0x00); 176 } 177 178 while (start < end) { 179 unsigned long blk_end = start + min(end - start, 4096UL); 180 181 while (start < blk_end) { 182 l2x0_inv_line(start); 183 start += CACHE_LINE_SIZE; 184 } 185 186 if (blk_end < end) { 187 spin_unlock_irqrestore(&l2x0_lock, flags); 188 spin_lock_irqsave(&l2x0_lock, flags); 189 } 190 } 191 cache_wait(base + L2X0_INV_LINE_PA, 1); 192 cache_sync(); 193 spin_unlock_irqrestore(&l2x0_lock, flags); 194 } 195 196 static void l2x0_clean_range(unsigned long start, unsigned long end) 197 { 198 void __iomem *base = l2x0_base; 199 unsigned long flags; 200 201 if ((end - start) >= l2x0_size) { 202 l2x0_clean_all(); 203 return; 204 } 205 206 spin_lock_irqsave(&l2x0_lock, flags); 207 start &= ~(CACHE_LINE_SIZE - 1); 208 while (start < end) { 209 unsigned long blk_end = start + min(end - start, 4096UL); 210 211 while (start < blk_end) { 212 l2x0_clean_line(start); 213 start += CACHE_LINE_SIZE; 214 } 215 216 if (blk_end < end) { 217 spin_unlock_irqrestore(&l2x0_lock, flags); 218 spin_lock_irqsave(&l2x0_lock, flags); 219 } 220 } 221 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 222 cache_sync(); 223 spin_unlock_irqrestore(&l2x0_lock, flags); 224 } 225 226 static void l2x0_flush_range(unsigned long start, unsigned long end) 227 { 228 void __iomem *base = l2x0_base; 229 unsigned long flags; 230 231 if ((end - start) >= l2x0_size) { 232 l2x0_flush_all(); 233 return; 234 } 235 236 spin_lock_irqsave(&l2x0_lock, flags); 237 start &= ~(CACHE_LINE_SIZE - 1); 238 while (start < end) { 239 unsigned long blk_end = start + min(end - start, 4096UL); 240 241 debug_writel(0x03); 242 while (start < blk_end) { 243 l2x0_flush_line(start); 244 start += CACHE_LINE_SIZE; 245 } 246 debug_writel(0x00); 247 248 if (blk_end < end) { 249 spin_unlock_irqrestore(&l2x0_lock, flags); 250 spin_lock_irqsave(&l2x0_lock, flags); 251 } 252 } 253 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 254 cache_sync(); 255 spin_unlock_irqrestore(&l2x0_lock, flags); 256 } 257 258 static void l2x0_disable(void) 259 { 260 unsigned long flags; 261 262 spin_lock_irqsave(&l2x0_lock, flags); 263 writel(0, l2x0_base + L2X0_CTRL); 264 spin_unlock_irqrestore(&l2x0_lock, flags); 265 } 266 267 void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) 268 { 269 __u32 aux; 270 __u32 cache_id; 271 __u32 way_size = 0; 272 int ways; 273 const char *type; 274 275 l2x0_base = base; 276 277 cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); 278 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); 279 280 aux &= aux_mask; 281 aux |= aux_val; 282 283 /* Determine the number of ways */ 284 switch (cache_id & L2X0_CACHE_ID_PART_MASK) { 285 case L2X0_CACHE_ID_PART_L310: 286 if (aux & (1 << 16)) 287 ways = 16; 288 else 289 ways = 8; 290 type = "L310"; 291 break; 292 case L2X0_CACHE_ID_PART_L210: 293 ways = (aux >> 13) & 0xf; 294 type = "L210"; 295 break; 296 default: 297 /* Assume unknown chips have 8 ways */ 298 ways = 8; 299 type = "L2x0 series"; 300 break; 301 } 302 303 l2x0_way_mask = (1 << ways) - 1; 304 305 /* 306 * L2 cache Size = Way size * Number of ways 307 */ 308 way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17; 309 way_size = 1 << (way_size + 3); 310 l2x0_size = ways * way_size * SZ_1K; 311 312 /* 313 * Check if l2x0 controller is already enabled. 314 * If you are booting from non-secure mode 315 * accessing the below registers will fault. 316 */ 317 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) { 318 319 /* l2x0 controller is disabled */ 320 writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL); 321 322 l2x0_inv_all(); 323 324 /* enable L2X0 */ 325 writel_relaxed(1, l2x0_base + L2X0_CTRL); 326 } 327 328 outer_cache.inv_range = l2x0_inv_range; 329 outer_cache.clean_range = l2x0_clean_range; 330 outer_cache.flush_range = l2x0_flush_range; 331 outer_cache.sync = l2x0_cache_sync; 332 outer_cache.flush_all = l2x0_flush_all; 333 outer_cache.inv_all = l2x0_inv_all; 334 outer_cache.disable = l2x0_disable; 335 outer_cache.set_debug = l2x0_set_debug; 336 337 printk(KERN_INFO "%s cache controller enabled\n", type); 338 printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", 339 ways, cache_id, aux, l2x0_size); 340 } 341