1 /* 2 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support 3 * 4 * Copyright (C) 2007 ARM Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 #include <linux/init.h> 20 #include <linux/spinlock.h> 21 #include <linux/io.h> 22 23 #include <asm/cacheflush.h> 24 #include <asm/hardware/cache-l2x0.h> 25 26 #define CACHE_LINE_SIZE 32 27 28 static void __iomem *l2x0_base; 29 static DEFINE_SPINLOCK(l2x0_lock); 30 static uint32_t l2x0_way_mask; /* Bitmask of active ways */ 31 static uint32_t l2x0_size; 32 33 static inline void cache_wait_way(void __iomem *reg, unsigned long mask) 34 { 35 /* wait for cache operation by line or way to complete */ 36 while (readl_relaxed(reg) & mask) 37 ; 38 } 39 40 #ifdef CONFIG_CACHE_PL310 41 static inline void cache_wait(void __iomem *reg, unsigned long mask) 42 { 43 /* cache operations by line are atomic on PL310 */ 44 } 45 #else 46 #define cache_wait cache_wait_way 47 #endif 48 49 static inline void cache_sync(void) 50 { 51 void __iomem *base = l2x0_base; 52 53 #ifdef CONFIG_ARM_ERRATA_753970 54 /* write to an unmmapped register */ 55 writel_relaxed(0, base + L2X0_DUMMY_REG); 56 #else 57 writel_relaxed(0, base + L2X0_CACHE_SYNC); 58 #endif 59 cache_wait(base + L2X0_CACHE_SYNC, 1); 60 } 61 62 static inline void l2x0_clean_line(unsigned long addr) 63 { 64 void __iomem *base = l2x0_base; 65 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 66 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA); 67 } 68 69 static inline void l2x0_inv_line(unsigned long addr) 70 { 71 void __iomem *base = l2x0_base; 72 cache_wait(base + L2X0_INV_LINE_PA, 1); 73 writel_relaxed(addr, base + L2X0_INV_LINE_PA); 74 } 75 76 #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) 77 78 #define debug_writel(val) outer_cache.set_debug(val) 79 80 static void l2x0_set_debug(unsigned long val) 81 { 82 writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL); 83 } 84 #else 85 /* Optimised out for non-errata case */ 86 static inline void debug_writel(unsigned long val) 87 { 88 } 89 90 #define l2x0_set_debug NULL 91 #endif 92 93 #ifdef CONFIG_PL310_ERRATA_588369 94 static inline void l2x0_flush_line(unsigned long addr) 95 { 96 void __iomem *base = l2x0_base; 97 98 /* Clean by PA followed by Invalidate by PA */ 99 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 100 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA); 101 cache_wait(base + L2X0_INV_LINE_PA, 1); 102 writel_relaxed(addr, base + L2X0_INV_LINE_PA); 103 } 104 #else 105 106 static inline void l2x0_flush_line(unsigned long addr) 107 { 108 void __iomem *base = l2x0_base; 109 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 110 writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA); 111 } 112 #endif 113 114 static void l2x0_cache_sync(void) 115 { 116 unsigned long flags; 117 118 spin_lock_irqsave(&l2x0_lock, flags); 119 cache_sync(); 120 spin_unlock_irqrestore(&l2x0_lock, flags); 121 } 122 123 static void l2x0_flush_all(void) 124 { 125 unsigned long flags; 126 127 /* clean all ways */ 128 spin_lock_irqsave(&l2x0_lock, flags); 129 debug_writel(0x03); 130 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY); 131 cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask); 132 cache_sync(); 133 debug_writel(0x00); 134 spin_unlock_irqrestore(&l2x0_lock, flags); 135 } 136 137 static void l2x0_clean_all(void) 138 { 139 unsigned long flags; 140 141 /* clean all ways */ 142 spin_lock_irqsave(&l2x0_lock, flags); 143 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY); 144 cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask); 145 cache_sync(); 146 spin_unlock_irqrestore(&l2x0_lock, flags); 147 } 148 149 static void l2x0_inv_all(void) 150 { 151 unsigned long flags; 152 153 /* invalidate all ways */ 154 spin_lock_irqsave(&l2x0_lock, flags); 155 /* Invalidating when L2 is enabled is a nono */ 156 BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1); 157 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY); 158 cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask); 159 cache_sync(); 160 spin_unlock_irqrestore(&l2x0_lock, flags); 161 } 162 163 static void l2x0_inv_range(unsigned long start, unsigned long end) 164 { 165 void __iomem *base = l2x0_base; 166 unsigned long flags; 167 168 spin_lock_irqsave(&l2x0_lock, flags); 169 if (start & (CACHE_LINE_SIZE - 1)) { 170 start &= ~(CACHE_LINE_SIZE - 1); 171 debug_writel(0x03); 172 l2x0_flush_line(start); 173 debug_writel(0x00); 174 start += CACHE_LINE_SIZE; 175 } 176 177 if (end & (CACHE_LINE_SIZE - 1)) { 178 end &= ~(CACHE_LINE_SIZE - 1); 179 debug_writel(0x03); 180 l2x0_flush_line(end); 181 debug_writel(0x00); 182 } 183 184 while (start < end) { 185 unsigned long blk_end = start + min(end - start, 4096UL); 186 187 while (start < blk_end) { 188 l2x0_inv_line(start); 189 start += CACHE_LINE_SIZE; 190 } 191 192 if (blk_end < end) { 193 spin_unlock_irqrestore(&l2x0_lock, flags); 194 spin_lock_irqsave(&l2x0_lock, flags); 195 } 196 } 197 cache_wait(base + L2X0_INV_LINE_PA, 1); 198 cache_sync(); 199 spin_unlock_irqrestore(&l2x0_lock, flags); 200 } 201 202 static void l2x0_clean_range(unsigned long start, unsigned long end) 203 { 204 void __iomem *base = l2x0_base; 205 unsigned long flags; 206 207 if ((end - start) >= l2x0_size) { 208 l2x0_clean_all(); 209 return; 210 } 211 212 spin_lock_irqsave(&l2x0_lock, flags); 213 start &= ~(CACHE_LINE_SIZE - 1); 214 while (start < end) { 215 unsigned long blk_end = start + min(end - start, 4096UL); 216 217 while (start < blk_end) { 218 l2x0_clean_line(start); 219 start += CACHE_LINE_SIZE; 220 } 221 222 if (blk_end < end) { 223 spin_unlock_irqrestore(&l2x0_lock, flags); 224 spin_lock_irqsave(&l2x0_lock, flags); 225 } 226 } 227 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 228 cache_sync(); 229 spin_unlock_irqrestore(&l2x0_lock, flags); 230 } 231 232 static void l2x0_flush_range(unsigned long start, unsigned long end) 233 { 234 void __iomem *base = l2x0_base; 235 unsigned long flags; 236 237 if ((end - start) >= l2x0_size) { 238 l2x0_flush_all(); 239 return; 240 } 241 242 spin_lock_irqsave(&l2x0_lock, flags); 243 start &= ~(CACHE_LINE_SIZE - 1); 244 while (start < end) { 245 unsigned long blk_end = start + min(end - start, 4096UL); 246 247 debug_writel(0x03); 248 while (start < blk_end) { 249 l2x0_flush_line(start); 250 start += CACHE_LINE_SIZE; 251 } 252 debug_writel(0x00); 253 254 if (blk_end < end) { 255 spin_unlock_irqrestore(&l2x0_lock, flags); 256 spin_lock_irqsave(&l2x0_lock, flags); 257 } 258 } 259 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 260 cache_sync(); 261 spin_unlock_irqrestore(&l2x0_lock, flags); 262 } 263 264 static void l2x0_disable(void) 265 { 266 unsigned long flags; 267 268 spin_lock_irqsave(&l2x0_lock, flags); 269 writel(0, l2x0_base + L2X0_CTRL); 270 spin_unlock_irqrestore(&l2x0_lock, flags); 271 } 272 273 void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) 274 { 275 __u32 aux; 276 __u32 cache_id; 277 __u32 way_size = 0; 278 int ways; 279 const char *type; 280 281 l2x0_base = base; 282 283 cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); 284 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); 285 286 aux &= aux_mask; 287 aux |= aux_val; 288 289 /* Determine the number of ways */ 290 switch (cache_id & L2X0_CACHE_ID_PART_MASK) { 291 case L2X0_CACHE_ID_PART_L310: 292 if (aux & (1 << 16)) 293 ways = 16; 294 else 295 ways = 8; 296 type = "L310"; 297 break; 298 case L2X0_CACHE_ID_PART_L210: 299 ways = (aux >> 13) & 0xf; 300 type = "L210"; 301 break; 302 default: 303 /* Assume unknown chips have 8 ways */ 304 ways = 8; 305 type = "L2x0 series"; 306 break; 307 } 308 309 l2x0_way_mask = (1 << ways) - 1; 310 311 /* 312 * L2 cache Size = Way size * Number of ways 313 */ 314 way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17; 315 way_size = 1 << (way_size + 3); 316 l2x0_size = ways * way_size * SZ_1K; 317 318 /* 319 * Check if l2x0 controller is already enabled. 320 * If you are booting from non-secure mode 321 * accessing the below registers will fault. 322 */ 323 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) { 324 325 /* l2x0 controller is disabled */ 326 writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL); 327 328 l2x0_inv_all(); 329 330 /* enable L2X0 */ 331 writel_relaxed(1, l2x0_base + L2X0_CTRL); 332 } 333 334 outer_cache.inv_range = l2x0_inv_range; 335 outer_cache.clean_range = l2x0_clean_range; 336 outer_cache.flush_range = l2x0_flush_range; 337 outer_cache.sync = l2x0_cache_sync; 338 outer_cache.flush_all = l2x0_flush_all; 339 outer_cache.inv_all = l2x0_inv_all; 340 outer_cache.disable = l2x0_disable; 341 outer_cache.set_debug = l2x0_set_debug; 342 343 printk(KERN_INFO "%s cache controller enabled\n", type); 344 printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", 345 ways, cache_id, aux, l2x0_size); 346 } 347