1f6f9be1cSFlorian Fainelli /* 2f6f9be1cSFlorian Fainelli * Broadcom Brahma-B15 CPU read-ahead cache management functions 3f6f9be1cSFlorian Fainelli * 4f6f9be1cSFlorian Fainelli * Copyright (C) 2015-2016 Broadcom 5f6f9be1cSFlorian Fainelli * 6f6f9be1cSFlorian Fainelli * This program is free software; you can redistribute it and/or modify 7f6f9be1cSFlorian Fainelli * it under the terms of the GNU General Public License version 2 as 8f6f9be1cSFlorian Fainelli * published by the Free Software Foundation. 9f6f9be1cSFlorian Fainelli */ 10f6f9be1cSFlorian Fainelli 11f6f9be1cSFlorian Fainelli #include <linux/err.h> 12f6f9be1cSFlorian Fainelli #include <linux/spinlock.h> 13f6f9be1cSFlorian Fainelli #include <linux/io.h> 14f6f9be1cSFlorian Fainelli #include <linux/bitops.h> 15f6f9be1cSFlorian Fainelli #include <linux/of_address.h> 1655de8877SFlorian Fainelli #include <linux/notifier.h> 1755de8877SFlorian Fainelli #include <linux/cpu.h> 18534f5f36SFlorian Fainelli #include <linux/syscore_ops.h> 19576a0860SFlorian Fainelli #include <linux/reboot.h> 20f6f9be1cSFlorian Fainelli 21f6f9be1cSFlorian Fainelli #include <asm/cacheflush.h> 22f6f9be1cSFlorian Fainelli #include <asm/hardware/cache-b15-rac.h> 23f6f9be1cSFlorian Fainelli 24f6f9be1cSFlorian Fainelli extern void v7_flush_kern_cache_all(void); 25f6f9be1cSFlorian Fainelli 26f6f9be1cSFlorian Fainelli /* RAC register offsets, relative to the HIF_CPU_BIUCTRL register base */ 27f6f9be1cSFlorian Fainelli #define RAC_CONFIG0_REG (0x78) 28f6f9be1cSFlorian Fainelli #define RACENPREF_MASK (0x3) 29f6f9be1cSFlorian Fainelli #define RACPREFINST_SHIFT (0) 30f6f9be1cSFlorian Fainelli #define RACENINST_SHIFT (2) 31f6f9be1cSFlorian Fainelli #define RACPREFDATA_SHIFT (4) 32f6f9be1cSFlorian Fainelli #define RACENDATA_SHIFT (6) 33f6f9be1cSFlorian Fainelli #define RAC_CPU_SHIFT (8) 34f6f9be1cSFlorian Fainelli #define RACCFG_MASK (0xff) 35f6f9be1cSFlorian Fainelli #define RAC_CONFIG1_REG (0x7c) 36f6f9be1cSFlorian Fainelli #define RAC_FLUSH_REG (0x80) 37f6f9be1cSFlorian Fainelli #define FLUSH_RAC (1 << 0) 38f6f9be1cSFlorian Fainelli 39f6f9be1cSFlorian Fainelli /* Bitmask to enable instruction and data prefetching with a 256-bytes stride */ 40f6f9be1cSFlorian Fainelli #define RAC_DATA_INST_EN_MASK (1 << RACPREFINST_SHIFT | \ 41f6f9be1cSFlorian Fainelli RACENPREF_MASK << RACENINST_SHIFT | \ 42f6f9be1cSFlorian Fainelli 1 << RACPREFDATA_SHIFT | \ 43f6f9be1cSFlorian Fainelli RACENPREF_MASK << RACENDATA_SHIFT) 44f6f9be1cSFlorian Fainelli 45f6f9be1cSFlorian Fainelli #define RAC_ENABLED 0 46534f5f36SFlorian Fainelli /* Special state where we want to bypass the spinlock and call directly 47534f5f36SFlorian Fainelli * into the v7 cache maintenance operations during suspend/resume 48534f5f36SFlorian Fainelli */ 49534f5f36SFlorian Fainelli #define RAC_SUSPENDED 1 50f6f9be1cSFlorian Fainelli 51f6f9be1cSFlorian Fainelli static void __iomem *b15_rac_base; 52f6f9be1cSFlorian Fainelli static DEFINE_SPINLOCK(rac_lock); 5355de8877SFlorian Fainelli static u32 rac_config0_reg; 54f6f9be1cSFlorian Fainelli 55f6f9be1cSFlorian Fainelli /* Initialization flag to avoid checking for b15_rac_base, and to prevent 56f6f9be1cSFlorian Fainelli * multi-platform kernels from crashing here as well. 57f6f9be1cSFlorian Fainelli */ 58f6f9be1cSFlorian Fainelli static unsigned long b15_rac_flags; 59f6f9be1cSFlorian Fainelli 60f6f9be1cSFlorian Fainelli static inline u32 __b15_rac_disable(void) 61f6f9be1cSFlorian Fainelli { 62f6f9be1cSFlorian Fainelli u32 val = __raw_readl(b15_rac_base + RAC_CONFIG0_REG); 63f6f9be1cSFlorian Fainelli __raw_writel(0, b15_rac_base + RAC_CONFIG0_REG); 64f6f9be1cSFlorian Fainelli dmb(); 65f6f9be1cSFlorian Fainelli return val; 66f6f9be1cSFlorian Fainelli } 67f6f9be1cSFlorian Fainelli 68f6f9be1cSFlorian Fainelli static inline void __b15_rac_flush(void) 69f6f9be1cSFlorian Fainelli { 70f6f9be1cSFlorian Fainelli u32 reg; 71f6f9be1cSFlorian Fainelli 72f6f9be1cSFlorian Fainelli __raw_writel(FLUSH_RAC, b15_rac_base + RAC_FLUSH_REG); 73f6f9be1cSFlorian Fainelli do { 74f6f9be1cSFlorian Fainelli /* This dmb() is required to force the Bus Interface Unit 75f6f9be1cSFlorian Fainelli * to clean oustanding writes, and forces an idle cycle 76f6f9be1cSFlorian Fainelli * to be inserted. 77f6f9be1cSFlorian Fainelli */ 78f6f9be1cSFlorian Fainelli dmb(); 79f6f9be1cSFlorian Fainelli reg = __raw_readl(b15_rac_base + RAC_FLUSH_REG); 80f6f9be1cSFlorian Fainelli } while (reg & FLUSH_RAC); 81f6f9be1cSFlorian Fainelli } 82f6f9be1cSFlorian Fainelli 83f6f9be1cSFlorian Fainelli static inline u32 b15_rac_disable_and_flush(void) 84f6f9be1cSFlorian Fainelli { 85f6f9be1cSFlorian Fainelli u32 reg; 86f6f9be1cSFlorian Fainelli 87f6f9be1cSFlorian Fainelli reg = __b15_rac_disable(); 88f6f9be1cSFlorian Fainelli __b15_rac_flush(); 89f6f9be1cSFlorian Fainelli return reg; 90f6f9be1cSFlorian Fainelli } 91f6f9be1cSFlorian Fainelli 92f6f9be1cSFlorian Fainelli static inline void __b15_rac_enable(u32 val) 93f6f9be1cSFlorian Fainelli { 94f6f9be1cSFlorian Fainelli __raw_writel(val, b15_rac_base + RAC_CONFIG0_REG); 95f6f9be1cSFlorian Fainelli /* dsb() is required here to be consistent with __flush_icache_all() */ 96f6f9be1cSFlorian Fainelli dsb(); 97f6f9be1cSFlorian Fainelli } 98f6f9be1cSFlorian Fainelli 99f6f9be1cSFlorian Fainelli #define BUILD_RAC_CACHE_OP(name, bar) \ 100f6f9be1cSFlorian Fainelli void b15_flush_##name(void) \ 101f6f9be1cSFlorian Fainelli { \ 102f6f9be1cSFlorian Fainelli unsigned int do_flush; \ 103f6f9be1cSFlorian Fainelli u32 val = 0; \ 104f6f9be1cSFlorian Fainelli \ 105534f5f36SFlorian Fainelli if (test_bit(RAC_SUSPENDED, &b15_rac_flags)) { \ 106534f5f36SFlorian Fainelli v7_flush_##name(); \ 107534f5f36SFlorian Fainelli bar; \ 108534f5f36SFlorian Fainelli return; \ 109534f5f36SFlorian Fainelli } \ 110534f5f36SFlorian Fainelli \ 111f6f9be1cSFlorian Fainelli spin_lock(&rac_lock); \ 112f6f9be1cSFlorian Fainelli do_flush = test_bit(RAC_ENABLED, &b15_rac_flags); \ 113f6f9be1cSFlorian Fainelli if (do_flush) \ 114f6f9be1cSFlorian Fainelli val = b15_rac_disable_and_flush(); \ 115f6f9be1cSFlorian Fainelli v7_flush_##name(); \ 116f6f9be1cSFlorian Fainelli if (!do_flush) \ 117f6f9be1cSFlorian Fainelli bar; \ 118f6f9be1cSFlorian Fainelli else \ 119f6f9be1cSFlorian Fainelli __b15_rac_enable(val); \ 120f6f9be1cSFlorian Fainelli spin_unlock(&rac_lock); \ 121f6f9be1cSFlorian Fainelli } 122f6f9be1cSFlorian Fainelli 123f6f9be1cSFlorian Fainelli #define nobarrier 124f6f9be1cSFlorian Fainelli 125f6f9be1cSFlorian Fainelli /* The readahead cache present in the Brahma-B15 CPU is a special piece of 126f6f9be1cSFlorian Fainelli * hardware after the integrated L2 cache of the B15 CPU complex whose purpose 127f6f9be1cSFlorian Fainelli * is to prefetch instruction and/or data with a line size of either 64 bytes 128f6f9be1cSFlorian Fainelli * or 256 bytes. The rationale is that the data-bus of the CPU interface is 129f6f9be1cSFlorian Fainelli * optimized for 256-bytes transactions, and enabling the readahead cache 130f6f9be1cSFlorian Fainelli * provides a significant performance boost we want it enabled (typically 131f6f9be1cSFlorian Fainelli * twice the performance for a memcpy benchmark application). 132f6f9be1cSFlorian Fainelli * 133f6f9be1cSFlorian Fainelli * The readahead cache is transparent for Modified Virtual Addresses 134f6f9be1cSFlorian Fainelli * cache maintenance operations: ICIMVAU, DCIMVAC, DCCMVAC, DCCMVAU and 135f6f9be1cSFlorian Fainelli * DCCIMVAC. 136f6f9be1cSFlorian Fainelli * 137f6f9be1cSFlorian Fainelli * It is however not transparent for the following cache maintenance 138f6f9be1cSFlorian Fainelli * operations: DCISW, DCCSW, DCCISW, ICIALLUIS and ICIALLU which is precisely 139f6f9be1cSFlorian Fainelli * what we are patching here with our BUILD_RAC_CACHE_OP here. 140f6f9be1cSFlorian Fainelli */ 141f6f9be1cSFlorian Fainelli BUILD_RAC_CACHE_OP(kern_cache_all, nobarrier); 142f6f9be1cSFlorian Fainelli 143f6f9be1cSFlorian Fainelli static void b15_rac_enable(void) 144f6f9be1cSFlorian Fainelli { 145f6f9be1cSFlorian Fainelli unsigned int cpu; 146f6f9be1cSFlorian Fainelli u32 enable = 0; 147f6f9be1cSFlorian Fainelli 148f6f9be1cSFlorian Fainelli for_each_possible_cpu(cpu) 149f6f9be1cSFlorian Fainelli enable |= (RAC_DATA_INST_EN_MASK << (cpu * RAC_CPU_SHIFT)); 150f6f9be1cSFlorian Fainelli 151f6f9be1cSFlorian Fainelli b15_rac_disable_and_flush(); 152f6f9be1cSFlorian Fainelli __b15_rac_enable(enable); 153f6f9be1cSFlorian Fainelli } 154f6f9be1cSFlorian Fainelli 155576a0860SFlorian Fainelli static int b15_rac_reboot_notifier(struct notifier_block *nb, 156576a0860SFlorian Fainelli unsigned long action, 157576a0860SFlorian Fainelli void *data) 158576a0860SFlorian Fainelli { 159576a0860SFlorian Fainelli /* During kexec, we are not yet migrated on the boot CPU, so we need to 160576a0860SFlorian Fainelli * make sure we are SMP safe here. Once the RAC is disabled, flag it as 161576a0860SFlorian Fainelli * suspended such that the hotplug notifier returns early. 162576a0860SFlorian Fainelli */ 163576a0860SFlorian Fainelli if (action == SYS_RESTART) { 164576a0860SFlorian Fainelli spin_lock(&rac_lock); 165576a0860SFlorian Fainelli b15_rac_disable_and_flush(); 166576a0860SFlorian Fainelli clear_bit(RAC_ENABLED, &b15_rac_flags); 167576a0860SFlorian Fainelli set_bit(RAC_SUSPENDED, &b15_rac_flags); 168576a0860SFlorian Fainelli spin_unlock(&rac_lock); 169576a0860SFlorian Fainelli } 170576a0860SFlorian Fainelli 171576a0860SFlorian Fainelli return NOTIFY_DONE; 172576a0860SFlorian Fainelli } 173576a0860SFlorian Fainelli 174576a0860SFlorian Fainelli static struct notifier_block b15_rac_reboot_nb = { 175576a0860SFlorian Fainelli .notifier_call = b15_rac_reboot_notifier, 176576a0860SFlorian Fainelli }; 177576a0860SFlorian Fainelli 17855de8877SFlorian Fainelli #ifdef CONFIG_HOTPLUG_CPU 17955de8877SFlorian Fainelli /* The CPU hotplug case is the most interesting one, we basically need to make 18055de8877SFlorian Fainelli * sure that the RAC is disabled for the entire system prior to having a CPU 18155de8877SFlorian Fainelli * die, in particular prior to this dying CPU having exited the coherency 18255de8877SFlorian Fainelli * domain. 18355de8877SFlorian Fainelli * 18455de8877SFlorian Fainelli * Once this CPU is marked dead, we can safely re-enable the RAC for the 18555de8877SFlorian Fainelli * remaining CPUs in the system which are still online. 18655de8877SFlorian Fainelli * 18755de8877SFlorian Fainelli * Offlining a CPU is the problematic case, onlining a CPU is not much of an 18855de8877SFlorian Fainelli * issue since the CPU and its cache-level hierarchy will start filling with 18955de8877SFlorian Fainelli * the RAC disabled, so L1 and L2 only. 19055de8877SFlorian Fainelli * 19155de8877SFlorian Fainelli * In this function, we should NOT have to verify any unsafe setting/condition 19255de8877SFlorian Fainelli * b15_rac_base: 19355de8877SFlorian Fainelli * 19455de8877SFlorian Fainelli * It is protected by the RAC_ENABLED flag which is cleared by default, and 19555de8877SFlorian Fainelli * being cleared when initial procedure is done. b15_rac_base had been set at 19655de8877SFlorian Fainelli * that time. 19755de8877SFlorian Fainelli * 19855de8877SFlorian Fainelli * RAC_ENABLED: 19955de8877SFlorian Fainelli * There is a small timing windows, in b15_rac_init(), between 20055de8877SFlorian Fainelli * cpuhp_setup_state_*() 20155de8877SFlorian Fainelli * ... 20255de8877SFlorian Fainelli * set RAC_ENABLED 20355de8877SFlorian Fainelli * However, there is no hotplug activity based on the Linux booting procedure. 20455de8877SFlorian Fainelli * 20555de8877SFlorian Fainelli * Since we have to disable RAC for all cores, we keep RAC on as long as as 20655de8877SFlorian Fainelli * possible (disable it as late as possible) to gain the cache benefit. 20755de8877SFlorian Fainelli * 20855de8877SFlorian Fainelli * Thus, dying/dead states are chosen here 20955de8877SFlorian Fainelli * 21055de8877SFlorian Fainelli * We are choosing not do disable the RAC on a per-CPU basis, here, if we did 21155de8877SFlorian Fainelli * we would want to consider disabling it as early as possible to benefit the 21255de8877SFlorian Fainelli * other active CPUs. 21355de8877SFlorian Fainelli */ 21455de8877SFlorian Fainelli 21555de8877SFlorian Fainelli /* Running on the dying CPU */ 21655de8877SFlorian Fainelli static int b15_rac_dying_cpu(unsigned int cpu) 21755de8877SFlorian Fainelli { 218576a0860SFlorian Fainelli /* During kexec/reboot, the RAC is disabled via the reboot notifier 219576a0860SFlorian Fainelli * return early here. 220576a0860SFlorian Fainelli */ 221576a0860SFlorian Fainelli if (test_bit(RAC_SUSPENDED, &b15_rac_flags)) 222576a0860SFlorian Fainelli return 0; 223576a0860SFlorian Fainelli 22455de8877SFlorian Fainelli spin_lock(&rac_lock); 22555de8877SFlorian Fainelli 22655de8877SFlorian Fainelli /* Indicate that we are starting a hotplug procedure */ 22755de8877SFlorian Fainelli __clear_bit(RAC_ENABLED, &b15_rac_flags); 22855de8877SFlorian Fainelli 22955de8877SFlorian Fainelli /* Disable the readahead cache and save its value to a global */ 23055de8877SFlorian Fainelli rac_config0_reg = b15_rac_disable_and_flush(); 23155de8877SFlorian Fainelli 23255de8877SFlorian Fainelli spin_unlock(&rac_lock); 23355de8877SFlorian Fainelli 23455de8877SFlorian Fainelli return 0; 23555de8877SFlorian Fainelli } 23655de8877SFlorian Fainelli 23755de8877SFlorian Fainelli /* Running on a non-dying CPU */ 23855de8877SFlorian Fainelli static int b15_rac_dead_cpu(unsigned int cpu) 23955de8877SFlorian Fainelli { 240576a0860SFlorian Fainelli /* During kexec/reboot, the RAC is disabled via the reboot notifier 241576a0860SFlorian Fainelli * return early here. 242576a0860SFlorian Fainelli */ 243576a0860SFlorian Fainelli if (test_bit(RAC_SUSPENDED, &b15_rac_flags)) 244576a0860SFlorian Fainelli return 0; 245576a0860SFlorian Fainelli 24655de8877SFlorian Fainelli spin_lock(&rac_lock); 24755de8877SFlorian Fainelli 24855de8877SFlorian Fainelli /* And enable it */ 24955de8877SFlorian Fainelli __b15_rac_enable(rac_config0_reg); 25055de8877SFlorian Fainelli __set_bit(RAC_ENABLED, &b15_rac_flags); 25155de8877SFlorian Fainelli 25255de8877SFlorian Fainelli spin_unlock(&rac_lock); 25355de8877SFlorian Fainelli 25455de8877SFlorian Fainelli return 0; 25555de8877SFlorian Fainelli } 25655de8877SFlorian Fainelli #endif /* CONFIG_HOTPLUG_CPU */ 25755de8877SFlorian Fainelli 258534f5f36SFlorian Fainelli #ifdef CONFIG_PM_SLEEP 259534f5f36SFlorian Fainelli static int b15_rac_suspend(void) 260534f5f36SFlorian Fainelli { 261534f5f36SFlorian Fainelli /* Suspend the read-ahead cache oeprations, forcing our cache 262534f5f36SFlorian Fainelli * implementation to fallback to the regular ARMv7 calls. 263534f5f36SFlorian Fainelli * 264534f5f36SFlorian Fainelli * We are guaranteed to be running on the boot CPU at this point and 265534f5f36SFlorian Fainelli * with every other CPU quiesced, so setting RAC_SUSPENDED is not racy 266534f5f36SFlorian Fainelli * here. 267534f5f36SFlorian Fainelli */ 268534f5f36SFlorian Fainelli rac_config0_reg = b15_rac_disable_and_flush(); 269534f5f36SFlorian Fainelli set_bit(RAC_SUSPENDED, &b15_rac_flags); 270534f5f36SFlorian Fainelli 271534f5f36SFlorian Fainelli return 0; 272534f5f36SFlorian Fainelli } 273534f5f36SFlorian Fainelli 274534f5f36SFlorian Fainelli static void b15_rac_resume(void) 275534f5f36SFlorian Fainelli { 276534f5f36SFlorian Fainelli /* Coming out of a S3 suspend/resume cycle, the read-ahead cache 277534f5f36SFlorian Fainelli * register RAC_CONFIG0_REG will be restored to its default value, make 278534f5f36SFlorian Fainelli * sure we re-enable it and set the enable flag, we are also guaranteed 279534f5f36SFlorian Fainelli * to run on the boot CPU, so not racy again. 280534f5f36SFlorian Fainelli */ 281534f5f36SFlorian Fainelli __b15_rac_enable(rac_config0_reg); 282534f5f36SFlorian Fainelli clear_bit(RAC_SUSPENDED, &b15_rac_flags); 283534f5f36SFlorian Fainelli } 284534f5f36SFlorian Fainelli 285534f5f36SFlorian Fainelli static struct syscore_ops b15_rac_syscore_ops = { 286534f5f36SFlorian Fainelli .suspend = b15_rac_suspend, 287534f5f36SFlorian Fainelli .resume = b15_rac_resume, 288534f5f36SFlorian Fainelli }; 289534f5f36SFlorian Fainelli #endif 290534f5f36SFlorian Fainelli 291f6f9be1cSFlorian Fainelli static int __init b15_rac_init(void) 292f6f9be1cSFlorian Fainelli { 293f6f9be1cSFlorian Fainelli struct device_node *dn; 294f6f9be1cSFlorian Fainelli int ret = 0, cpu; 295f6f9be1cSFlorian Fainelli u32 reg, en_mask = 0; 296f6f9be1cSFlorian Fainelli 297f6f9be1cSFlorian Fainelli dn = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl"); 298f6f9be1cSFlorian Fainelli if (!dn) 299f6f9be1cSFlorian Fainelli return -ENODEV; 300f6f9be1cSFlorian Fainelli 301f6f9be1cSFlorian Fainelli if (WARN(num_possible_cpus() > 4, "RAC only supports 4 CPUs\n")) 302f6f9be1cSFlorian Fainelli goto out; 303f6f9be1cSFlorian Fainelli 304f6f9be1cSFlorian Fainelli b15_rac_base = of_iomap(dn, 0); 305f6f9be1cSFlorian Fainelli if (!b15_rac_base) { 306f6f9be1cSFlorian Fainelli pr_err("failed to remap BIU control base\n"); 307f6f9be1cSFlorian Fainelli ret = -ENOMEM; 308f6f9be1cSFlorian Fainelli goto out; 309f6f9be1cSFlorian Fainelli } 310f6f9be1cSFlorian Fainelli 311576a0860SFlorian Fainelli ret = register_reboot_notifier(&b15_rac_reboot_nb); 312576a0860SFlorian Fainelli if (ret) { 313576a0860SFlorian Fainelli pr_err("failed to register reboot notifier\n"); 314576a0860SFlorian Fainelli iounmap(b15_rac_base); 315576a0860SFlorian Fainelli goto out; 316576a0860SFlorian Fainelli } 317576a0860SFlorian Fainelli 31855de8877SFlorian Fainelli #ifdef CONFIG_HOTPLUG_CPU 31955de8877SFlorian Fainelli ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CACHE_B15_RAC_DEAD, 32055de8877SFlorian Fainelli "arm/cache-b15-rac:dead", 32155de8877SFlorian Fainelli NULL, b15_rac_dead_cpu); 32255de8877SFlorian Fainelli if (ret) 32355de8877SFlorian Fainelli goto out_unmap; 32455de8877SFlorian Fainelli 32555de8877SFlorian Fainelli ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CACHE_B15_RAC_DYING, 32655de8877SFlorian Fainelli "arm/cache-b15-rac:dying", 32755de8877SFlorian Fainelli NULL, b15_rac_dying_cpu); 32855de8877SFlorian Fainelli if (ret) 32955de8877SFlorian Fainelli goto out_cpu_dead; 33055de8877SFlorian Fainelli #endif 33155de8877SFlorian Fainelli 332534f5f36SFlorian Fainelli #ifdef CONFIG_PM_SLEEP 333534f5f36SFlorian Fainelli register_syscore_ops(&b15_rac_syscore_ops); 334534f5f36SFlorian Fainelli #endif 335534f5f36SFlorian Fainelli 336f6f9be1cSFlorian Fainelli spin_lock(&rac_lock); 337f6f9be1cSFlorian Fainelli reg = __raw_readl(b15_rac_base + RAC_CONFIG0_REG); 338f6f9be1cSFlorian Fainelli for_each_possible_cpu(cpu) 339f6f9be1cSFlorian Fainelli en_mask |= ((1 << RACPREFDATA_SHIFT) << (cpu * RAC_CPU_SHIFT)); 340f6f9be1cSFlorian Fainelli WARN(reg & en_mask, "Read-ahead cache not previously disabled\n"); 341f6f9be1cSFlorian Fainelli 342f6f9be1cSFlorian Fainelli b15_rac_enable(); 343f6f9be1cSFlorian Fainelli set_bit(RAC_ENABLED, &b15_rac_flags); 344f6f9be1cSFlorian Fainelli spin_unlock(&rac_lock); 345f6f9be1cSFlorian Fainelli 346f6f9be1cSFlorian Fainelli pr_info("Broadcom Brahma-B15 readahead cache at: 0x%p\n", 347f6f9be1cSFlorian Fainelli b15_rac_base + RAC_CONFIG0_REG); 348f6f9be1cSFlorian Fainelli 34955de8877SFlorian Fainelli goto out; 35055de8877SFlorian Fainelli 35155de8877SFlorian Fainelli out_cpu_dead: 35255de8877SFlorian Fainelli cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CACHE_B15_RAC_DYING); 35355de8877SFlorian Fainelli out_unmap: 354576a0860SFlorian Fainelli unregister_reboot_notifier(&b15_rac_reboot_nb); 35555de8877SFlorian Fainelli iounmap(b15_rac_base); 356f6f9be1cSFlorian Fainelli out: 357f6f9be1cSFlorian Fainelli of_node_put(dn); 358f6f9be1cSFlorian Fainelli return ret; 359f6f9be1cSFlorian Fainelli } 360f6f9be1cSFlorian Fainelli arch_initcall(b15_rac_init); 361