1f6f9be1cSFlorian Fainelli /* 2f6f9be1cSFlorian Fainelli * Broadcom Brahma-B15 CPU read-ahead cache management functions 3f6f9be1cSFlorian Fainelli * 4f6f9be1cSFlorian Fainelli * Copyright (C) 2015-2016 Broadcom 5f6f9be1cSFlorian Fainelli * 6f6f9be1cSFlorian Fainelli * This program is free software; you can redistribute it and/or modify 7f6f9be1cSFlorian Fainelli * it under the terms of the GNU General Public License version 2 as 8f6f9be1cSFlorian Fainelli * published by the Free Software Foundation. 9f6f9be1cSFlorian Fainelli */ 10f6f9be1cSFlorian Fainelli 11f6f9be1cSFlorian Fainelli #include <linux/err.h> 12f6f9be1cSFlorian Fainelli #include <linux/spinlock.h> 13f6f9be1cSFlorian Fainelli #include <linux/io.h> 14f6f9be1cSFlorian Fainelli #include <linux/bitops.h> 15f6f9be1cSFlorian Fainelli #include <linux/of_address.h> 1655de8877SFlorian Fainelli #include <linux/notifier.h> 1755de8877SFlorian Fainelli #include <linux/cpu.h> 18f6f9be1cSFlorian Fainelli 19f6f9be1cSFlorian Fainelli #include <asm/cacheflush.h> 20f6f9be1cSFlorian Fainelli #include <asm/hardware/cache-b15-rac.h> 21f6f9be1cSFlorian Fainelli 22f6f9be1cSFlorian Fainelli extern void v7_flush_kern_cache_all(void); 23f6f9be1cSFlorian Fainelli 24f6f9be1cSFlorian Fainelli /* RAC register offsets, relative to the HIF_CPU_BIUCTRL register base */ 25f6f9be1cSFlorian Fainelli #define RAC_CONFIG0_REG (0x78) 26f6f9be1cSFlorian Fainelli #define RACENPREF_MASK (0x3) 27f6f9be1cSFlorian Fainelli #define RACPREFINST_SHIFT (0) 28f6f9be1cSFlorian Fainelli #define RACENINST_SHIFT (2) 29f6f9be1cSFlorian Fainelli #define RACPREFDATA_SHIFT (4) 30f6f9be1cSFlorian Fainelli #define RACENDATA_SHIFT (6) 31f6f9be1cSFlorian Fainelli #define RAC_CPU_SHIFT (8) 32f6f9be1cSFlorian Fainelli #define RACCFG_MASK (0xff) 33f6f9be1cSFlorian Fainelli #define RAC_CONFIG1_REG (0x7c) 34f6f9be1cSFlorian Fainelli #define RAC_FLUSH_REG (0x80) 35f6f9be1cSFlorian Fainelli #define FLUSH_RAC (1 << 0) 36f6f9be1cSFlorian Fainelli 37f6f9be1cSFlorian Fainelli /* Bitmask to enable instruction and data prefetching with a 256-bytes stride */ 38f6f9be1cSFlorian Fainelli #define RAC_DATA_INST_EN_MASK (1 << RACPREFINST_SHIFT | \ 39f6f9be1cSFlorian Fainelli RACENPREF_MASK << RACENINST_SHIFT | \ 40f6f9be1cSFlorian Fainelli 1 << RACPREFDATA_SHIFT | \ 41f6f9be1cSFlorian Fainelli RACENPREF_MASK << RACENDATA_SHIFT) 42f6f9be1cSFlorian Fainelli 43f6f9be1cSFlorian Fainelli #define RAC_ENABLED 0 44f6f9be1cSFlorian Fainelli 45f6f9be1cSFlorian Fainelli static void __iomem *b15_rac_base; 46f6f9be1cSFlorian Fainelli static DEFINE_SPINLOCK(rac_lock); 4755de8877SFlorian Fainelli static u32 rac_config0_reg; 48f6f9be1cSFlorian Fainelli 49f6f9be1cSFlorian Fainelli /* Initialization flag to avoid checking for b15_rac_base, and to prevent 50f6f9be1cSFlorian Fainelli * multi-platform kernels from crashing here as well. 51f6f9be1cSFlorian Fainelli */ 52f6f9be1cSFlorian Fainelli static unsigned long b15_rac_flags; 53f6f9be1cSFlorian Fainelli 54f6f9be1cSFlorian Fainelli static inline u32 __b15_rac_disable(void) 55f6f9be1cSFlorian Fainelli { 56f6f9be1cSFlorian Fainelli u32 val = __raw_readl(b15_rac_base + RAC_CONFIG0_REG); 57f6f9be1cSFlorian Fainelli __raw_writel(0, b15_rac_base + RAC_CONFIG0_REG); 58f6f9be1cSFlorian Fainelli dmb(); 59f6f9be1cSFlorian Fainelli return val; 60f6f9be1cSFlorian Fainelli } 61f6f9be1cSFlorian Fainelli 62f6f9be1cSFlorian Fainelli static inline void __b15_rac_flush(void) 63f6f9be1cSFlorian Fainelli { 64f6f9be1cSFlorian Fainelli u32 reg; 65f6f9be1cSFlorian Fainelli 66f6f9be1cSFlorian Fainelli __raw_writel(FLUSH_RAC, b15_rac_base + RAC_FLUSH_REG); 67f6f9be1cSFlorian Fainelli do { 68f6f9be1cSFlorian Fainelli /* This dmb() is required to force the Bus Interface Unit 69f6f9be1cSFlorian Fainelli * to clean oustanding writes, and forces an idle cycle 70f6f9be1cSFlorian Fainelli * to be inserted. 71f6f9be1cSFlorian Fainelli */ 72f6f9be1cSFlorian Fainelli dmb(); 73f6f9be1cSFlorian Fainelli reg = __raw_readl(b15_rac_base + RAC_FLUSH_REG); 74f6f9be1cSFlorian Fainelli } while (reg & FLUSH_RAC); 75f6f9be1cSFlorian Fainelli } 76f6f9be1cSFlorian Fainelli 77f6f9be1cSFlorian Fainelli static inline u32 b15_rac_disable_and_flush(void) 78f6f9be1cSFlorian Fainelli { 79f6f9be1cSFlorian Fainelli u32 reg; 80f6f9be1cSFlorian Fainelli 81f6f9be1cSFlorian Fainelli reg = __b15_rac_disable(); 82f6f9be1cSFlorian Fainelli __b15_rac_flush(); 83f6f9be1cSFlorian Fainelli return reg; 84f6f9be1cSFlorian Fainelli } 85f6f9be1cSFlorian Fainelli 86f6f9be1cSFlorian Fainelli static inline void __b15_rac_enable(u32 val) 87f6f9be1cSFlorian Fainelli { 88f6f9be1cSFlorian Fainelli __raw_writel(val, b15_rac_base + RAC_CONFIG0_REG); 89f6f9be1cSFlorian Fainelli /* dsb() is required here to be consistent with __flush_icache_all() */ 90f6f9be1cSFlorian Fainelli dsb(); 91f6f9be1cSFlorian Fainelli } 92f6f9be1cSFlorian Fainelli 93f6f9be1cSFlorian Fainelli #define BUILD_RAC_CACHE_OP(name, bar) \ 94f6f9be1cSFlorian Fainelli void b15_flush_##name(void) \ 95f6f9be1cSFlorian Fainelli { \ 96f6f9be1cSFlorian Fainelli unsigned int do_flush; \ 97f6f9be1cSFlorian Fainelli u32 val = 0; \ 98f6f9be1cSFlorian Fainelli \ 99f6f9be1cSFlorian Fainelli spin_lock(&rac_lock); \ 100f6f9be1cSFlorian Fainelli do_flush = test_bit(RAC_ENABLED, &b15_rac_flags); \ 101f6f9be1cSFlorian Fainelli if (do_flush) \ 102f6f9be1cSFlorian Fainelli val = b15_rac_disable_and_flush(); \ 103f6f9be1cSFlorian Fainelli v7_flush_##name(); \ 104f6f9be1cSFlorian Fainelli if (!do_flush) \ 105f6f9be1cSFlorian Fainelli bar; \ 106f6f9be1cSFlorian Fainelli else \ 107f6f9be1cSFlorian Fainelli __b15_rac_enable(val); \ 108f6f9be1cSFlorian Fainelli spin_unlock(&rac_lock); \ 109f6f9be1cSFlorian Fainelli } 110f6f9be1cSFlorian Fainelli 111f6f9be1cSFlorian Fainelli #define nobarrier 112f6f9be1cSFlorian Fainelli 113f6f9be1cSFlorian Fainelli /* The readahead cache present in the Brahma-B15 CPU is a special piece of 114f6f9be1cSFlorian Fainelli * hardware after the integrated L2 cache of the B15 CPU complex whose purpose 115f6f9be1cSFlorian Fainelli * is to prefetch instruction and/or data with a line size of either 64 bytes 116f6f9be1cSFlorian Fainelli * or 256 bytes. The rationale is that the data-bus of the CPU interface is 117f6f9be1cSFlorian Fainelli * optimized for 256-bytes transactions, and enabling the readahead cache 118f6f9be1cSFlorian Fainelli * provides a significant performance boost we want it enabled (typically 119f6f9be1cSFlorian Fainelli * twice the performance for a memcpy benchmark application). 120f6f9be1cSFlorian Fainelli * 121f6f9be1cSFlorian Fainelli * The readahead cache is transparent for Modified Virtual Addresses 122f6f9be1cSFlorian Fainelli * cache maintenance operations: ICIMVAU, DCIMVAC, DCCMVAC, DCCMVAU and 123f6f9be1cSFlorian Fainelli * DCCIMVAC. 124f6f9be1cSFlorian Fainelli * 125f6f9be1cSFlorian Fainelli * It is however not transparent for the following cache maintenance 126f6f9be1cSFlorian Fainelli * operations: DCISW, DCCSW, DCCISW, ICIALLUIS and ICIALLU which is precisely 127f6f9be1cSFlorian Fainelli * what we are patching here with our BUILD_RAC_CACHE_OP here. 128f6f9be1cSFlorian Fainelli */ 129f6f9be1cSFlorian Fainelli BUILD_RAC_CACHE_OP(kern_cache_all, nobarrier); 130f6f9be1cSFlorian Fainelli 131f6f9be1cSFlorian Fainelli static void b15_rac_enable(void) 132f6f9be1cSFlorian Fainelli { 133f6f9be1cSFlorian Fainelli unsigned int cpu; 134f6f9be1cSFlorian Fainelli u32 enable = 0; 135f6f9be1cSFlorian Fainelli 136f6f9be1cSFlorian Fainelli for_each_possible_cpu(cpu) 137f6f9be1cSFlorian Fainelli enable |= (RAC_DATA_INST_EN_MASK << (cpu * RAC_CPU_SHIFT)); 138f6f9be1cSFlorian Fainelli 139f6f9be1cSFlorian Fainelli b15_rac_disable_and_flush(); 140f6f9be1cSFlorian Fainelli __b15_rac_enable(enable); 141f6f9be1cSFlorian Fainelli } 142f6f9be1cSFlorian Fainelli 14355de8877SFlorian Fainelli #ifdef CONFIG_HOTPLUG_CPU 14455de8877SFlorian Fainelli /* The CPU hotplug case is the most interesting one, we basically need to make 14555de8877SFlorian Fainelli * sure that the RAC is disabled for the entire system prior to having a CPU 14655de8877SFlorian Fainelli * die, in particular prior to this dying CPU having exited the coherency 14755de8877SFlorian Fainelli * domain. 14855de8877SFlorian Fainelli * 14955de8877SFlorian Fainelli * Once this CPU is marked dead, we can safely re-enable the RAC for the 15055de8877SFlorian Fainelli * remaining CPUs in the system which are still online. 15155de8877SFlorian Fainelli * 15255de8877SFlorian Fainelli * Offlining a CPU is the problematic case, onlining a CPU is not much of an 15355de8877SFlorian Fainelli * issue since the CPU and its cache-level hierarchy will start filling with 15455de8877SFlorian Fainelli * the RAC disabled, so L1 and L2 only. 15555de8877SFlorian Fainelli * 15655de8877SFlorian Fainelli * In this function, we should NOT have to verify any unsafe setting/condition 15755de8877SFlorian Fainelli * b15_rac_base: 15855de8877SFlorian Fainelli * 15955de8877SFlorian Fainelli * It is protected by the RAC_ENABLED flag which is cleared by default, and 16055de8877SFlorian Fainelli * being cleared when initial procedure is done. b15_rac_base had been set at 16155de8877SFlorian Fainelli * that time. 16255de8877SFlorian Fainelli * 16355de8877SFlorian Fainelli * RAC_ENABLED: 16455de8877SFlorian Fainelli * There is a small timing windows, in b15_rac_init(), between 16555de8877SFlorian Fainelli * cpuhp_setup_state_*() 16655de8877SFlorian Fainelli * ... 16755de8877SFlorian Fainelli * set RAC_ENABLED 16855de8877SFlorian Fainelli * However, there is no hotplug activity based on the Linux booting procedure. 16955de8877SFlorian Fainelli * 17055de8877SFlorian Fainelli * Since we have to disable RAC for all cores, we keep RAC on as long as as 17155de8877SFlorian Fainelli * possible (disable it as late as possible) to gain the cache benefit. 17255de8877SFlorian Fainelli * 17355de8877SFlorian Fainelli * Thus, dying/dead states are chosen here 17455de8877SFlorian Fainelli * 17555de8877SFlorian Fainelli * We are choosing not do disable the RAC on a per-CPU basis, here, if we did 17655de8877SFlorian Fainelli * we would want to consider disabling it as early as possible to benefit the 17755de8877SFlorian Fainelli * other active CPUs. 17855de8877SFlorian Fainelli */ 17955de8877SFlorian Fainelli 18055de8877SFlorian Fainelli /* Running on the dying CPU */ 18155de8877SFlorian Fainelli static int b15_rac_dying_cpu(unsigned int cpu) 18255de8877SFlorian Fainelli { 18355de8877SFlorian Fainelli spin_lock(&rac_lock); 18455de8877SFlorian Fainelli 18555de8877SFlorian Fainelli /* Indicate that we are starting a hotplug procedure */ 18655de8877SFlorian Fainelli __clear_bit(RAC_ENABLED, &b15_rac_flags); 18755de8877SFlorian Fainelli 18855de8877SFlorian Fainelli /* Disable the readahead cache and save its value to a global */ 18955de8877SFlorian Fainelli rac_config0_reg = b15_rac_disable_and_flush(); 19055de8877SFlorian Fainelli 19155de8877SFlorian Fainelli spin_unlock(&rac_lock); 19255de8877SFlorian Fainelli 19355de8877SFlorian Fainelli return 0; 19455de8877SFlorian Fainelli } 19555de8877SFlorian Fainelli 19655de8877SFlorian Fainelli /* Running on a non-dying CPU */ 19755de8877SFlorian Fainelli static int b15_rac_dead_cpu(unsigned int cpu) 19855de8877SFlorian Fainelli { 19955de8877SFlorian Fainelli spin_lock(&rac_lock); 20055de8877SFlorian Fainelli 20155de8877SFlorian Fainelli /* And enable it */ 20255de8877SFlorian Fainelli __b15_rac_enable(rac_config0_reg); 20355de8877SFlorian Fainelli __set_bit(RAC_ENABLED, &b15_rac_flags); 20455de8877SFlorian Fainelli 20555de8877SFlorian Fainelli spin_unlock(&rac_lock); 20655de8877SFlorian Fainelli 20755de8877SFlorian Fainelli return 0; 20855de8877SFlorian Fainelli } 20955de8877SFlorian Fainelli #endif /* CONFIG_HOTPLUG_CPU */ 21055de8877SFlorian Fainelli 211f6f9be1cSFlorian Fainelli static int __init b15_rac_init(void) 212f6f9be1cSFlorian Fainelli { 213f6f9be1cSFlorian Fainelli struct device_node *dn; 214f6f9be1cSFlorian Fainelli int ret = 0, cpu; 215f6f9be1cSFlorian Fainelli u32 reg, en_mask = 0; 216f6f9be1cSFlorian Fainelli 217f6f9be1cSFlorian Fainelli dn = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl"); 218f6f9be1cSFlorian Fainelli if (!dn) 219f6f9be1cSFlorian Fainelli return -ENODEV; 220f6f9be1cSFlorian Fainelli 221f6f9be1cSFlorian Fainelli if (WARN(num_possible_cpus() > 4, "RAC only supports 4 CPUs\n")) 222f6f9be1cSFlorian Fainelli goto out; 223f6f9be1cSFlorian Fainelli 224f6f9be1cSFlorian Fainelli b15_rac_base = of_iomap(dn, 0); 225f6f9be1cSFlorian Fainelli if (!b15_rac_base) { 226f6f9be1cSFlorian Fainelli pr_err("failed to remap BIU control base\n"); 227f6f9be1cSFlorian Fainelli ret = -ENOMEM; 228f6f9be1cSFlorian Fainelli goto out; 229f6f9be1cSFlorian Fainelli } 230f6f9be1cSFlorian Fainelli 23155de8877SFlorian Fainelli #ifdef CONFIG_HOTPLUG_CPU 23255de8877SFlorian Fainelli ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CACHE_B15_RAC_DEAD, 23355de8877SFlorian Fainelli "arm/cache-b15-rac:dead", 23455de8877SFlorian Fainelli NULL, b15_rac_dead_cpu); 23555de8877SFlorian Fainelli if (ret) 23655de8877SFlorian Fainelli goto out_unmap; 23755de8877SFlorian Fainelli 23855de8877SFlorian Fainelli ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CACHE_B15_RAC_DYING, 23955de8877SFlorian Fainelli "arm/cache-b15-rac:dying", 24055de8877SFlorian Fainelli NULL, b15_rac_dying_cpu); 24155de8877SFlorian Fainelli if (ret) 24255de8877SFlorian Fainelli goto out_cpu_dead; 24355de8877SFlorian Fainelli #endif 24455de8877SFlorian Fainelli 245f6f9be1cSFlorian Fainelli spin_lock(&rac_lock); 246f6f9be1cSFlorian Fainelli reg = __raw_readl(b15_rac_base + RAC_CONFIG0_REG); 247f6f9be1cSFlorian Fainelli for_each_possible_cpu(cpu) 248f6f9be1cSFlorian Fainelli en_mask |= ((1 << RACPREFDATA_SHIFT) << (cpu * RAC_CPU_SHIFT)); 249f6f9be1cSFlorian Fainelli WARN(reg & en_mask, "Read-ahead cache not previously disabled\n"); 250f6f9be1cSFlorian Fainelli 251f6f9be1cSFlorian Fainelli b15_rac_enable(); 252f6f9be1cSFlorian Fainelli set_bit(RAC_ENABLED, &b15_rac_flags); 253f6f9be1cSFlorian Fainelli spin_unlock(&rac_lock); 254f6f9be1cSFlorian Fainelli 255f6f9be1cSFlorian Fainelli pr_info("Broadcom Brahma-B15 readahead cache at: 0x%p\n", 256f6f9be1cSFlorian Fainelli b15_rac_base + RAC_CONFIG0_REG); 257f6f9be1cSFlorian Fainelli 25855de8877SFlorian Fainelli goto out; 25955de8877SFlorian Fainelli 26055de8877SFlorian Fainelli out_cpu_dead: 26155de8877SFlorian Fainelli cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CACHE_B15_RAC_DYING); 26255de8877SFlorian Fainelli out_unmap: 26355de8877SFlorian Fainelli iounmap(b15_rac_base); 264f6f9be1cSFlorian Fainelli out: 265f6f9be1cSFlorian Fainelli of_node_put(dn); 266f6f9be1cSFlorian Fainelli return ret; 267f6f9be1cSFlorian Fainelli } 268f6f9be1cSFlorian Fainelli arch_initcall(b15_rac_init); 269