1comment "Processor Type" 2 3config CPU_32 4 bool 5 default y 6 7# Select CPU types depending on the architecture selected. This selects 8# which CPUs we support in the kernel image, and the compiler instruction 9# optimiser behaviour. 10 11# ARM610 12config CPU_ARM610 13 bool "Support ARM610 processor" 14 depends on ARCH_RPC 15 select CPU_32v3 16 select CPU_CACHE_V3 17 select CPU_CACHE_VIVT 18 select CPU_CP15_MMU 19 select CPU_COPY_V3 if MMU 20 select CPU_TLB_V3 if MMU 21 help 22 The ARM610 is the successor to the ARM3 processor 23 and was produced by VLSI Technology Inc. 24 25 Say Y if you want support for the ARM610 processor. 26 Otherwise, say N. 27 28# ARM7TDMI 29config CPU_ARM7TDMI 30 bool "Support ARM7TDMI processor" 31 depends on !MMU 32 select CPU_32v4T 33 select CPU_ABRT_LV4T 34 select CPU_CACHE_V4 35 help 36 A 32-bit RISC microprocessor based on the ARM7 processor core 37 which has no memory control unit and cache. 38 39 Say Y if you want support for the ARM7TDMI processor. 40 Otherwise, say N. 41 42# ARM710 43config CPU_ARM710 44 bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC 45 default y if ARCH_CLPS7500 46 select CPU_32v3 47 select CPU_CACHE_V3 48 select CPU_CACHE_VIVT 49 select CPU_CP15_MMU 50 select CPU_COPY_V3 if MMU 51 select CPU_TLB_V3 if MMU 52 help 53 A 32-bit RISC microprocessor based on the ARM7 processor core 54 designed by Advanced RISC Machines Ltd. The ARM710 is the 55 successor to the ARM610 processor. It was released in 56 July 1994 by VLSI Technology Inc. 57 58 Say Y if you want support for the ARM710 processor. 59 Otherwise, say N. 60 61# ARM720T 62config CPU_ARM720T 63 bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR 64 default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X 65 select CPU_32v4T 66 select CPU_ABRT_LV4T 67 select CPU_CACHE_V4 68 select CPU_CACHE_VIVT 69 select CPU_CP15_MMU 70 select CPU_COPY_V4WT if MMU 71 select CPU_TLB_V4WT if MMU 72 help 73 A 32-bit RISC processor with 8kByte Cache, Write Buffer and 74 MMU built around an ARM7TDMI core. 75 76 Say Y if you want support for the ARM720T processor. 77 Otherwise, say N. 78 79# ARM740T 80config CPU_ARM740T 81 bool "Support ARM740T processor" if ARCH_INTEGRATOR 82 depends on !MMU 83 select CPU_32v4T 84 select CPU_ABRT_LV4T 85 select CPU_CACHE_V3 # although the core is v4t 86 select CPU_CP15_MPU 87 help 88 A 32-bit RISC processor with 8KB cache or 4KB variants, 89 write buffer and MPU(Protection Unit) built around 90 an ARM7TDMI core. 91 92 Say Y if you want support for the ARM740T processor. 93 Otherwise, say N. 94 95# ARM9TDMI 96config CPU_ARM9TDMI 97 bool "Support ARM9TDMI processor" 98 depends on !MMU 99 select CPU_32v4T 100 select CPU_ABRT_NOMMU 101 select CPU_CACHE_V4 102 help 103 A 32-bit RISC microprocessor based on the ARM9 processor core 104 which has no memory control unit and cache. 105 106 Say Y if you want support for the ARM9TDMI processor. 107 Otherwise, say N. 108 109# ARM920T 110config CPU_ARM920T 111 bool "Support ARM920T processor" 112 depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200 113 default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200 114 select CPU_32v4T 115 select CPU_ABRT_EV4T 116 select CPU_CACHE_V4WT 117 select CPU_CACHE_VIVT 118 select CPU_CP15_MMU 119 select CPU_COPY_V4WB if MMU 120 select CPU_TLB_V4WBI if MMU 121 help 122 The ARM920T is licensed to be produced by numerous vendors, 123 and is used in the Maverick EP9312 and the Samsung S3C2410. 124 125 More information on the Maverick EP9312 at 126 <http://linuxdevices.com/products/PD2382866068.html>. 127 128 Say Y if you want support for the ARM920T processor. 129 Otherwise, say N. 130 131# ARM922T 132config CPU_ARM922T 133 bool "Support ARM922T processor" if ARCH_INTEGRATOR 134 depends on ARCH_LH7A40X || ARCH_INTEGRATOR 135 default y if ARCH_LH7A40X 136 select CPU_32v4T 137 select CPU_ABRT_EV4T 138 select CPU_CACHE_V4WT 139 select CPU_CACHE_VIVT 140 select CPU_CP15_MMU 141 select CPU_COPY_V4WB if MMU 142 select CPU_TLB_V4WBI if MMU 143 help 144 The ARM922T is a version of the ARM920T, but with smaller 145 instruction and data caches. It is used in Altera's 146 Excalibur XA device family. 147 148 Say Y if you want support for the ARM922T processor. 149 Otherwise, say N. 150 151# ARM925T 152config CPU_ARM925T 153 bool "Support ARM925T processor" if ARCH_OMAP1 154 depends on ARCH_OMAP15XX 155 default y if ARCH_OMAP15XX 156 select CPU_32v4T 157 select CPU_ABRT_EV4T 158 select CPU_CACHE_V4WT 159 select CPU_CACHE_VIVT 160 select CPU_CP15_MMU 161 select CPU_COPY_V4WB if MMU 162 select CPU_TLB_V4WBI if MMU 163 help 164 The ARM925T is a mix between the ARM920T and ARM926T, but with 165 different instruction and data caches. It is used in TI's OMAP 166 device family. 167 168 Say Y if you want support for the ARM925T processor. 169 Otherwise, say N. 170 171# ARM926T 172config CPU_ARM926T 173 bool "Support ARM926T processor" 174 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_NS9XXX 175 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_NS9XXX 176 select CPU_32v5 177 select CPU_ABRT_EV5TJ 178 select CPU_CACHE_VIVT 179 select CPU_CP15_MMU 180 select CPU_COPY_V4WB if MMU 181 select CPU_TLB_V4WBI if MMU 182 help 183 This is a variant of the ARM920. It has slightly different 184 instruction sequences for cache and TLB operations. Curiously, 185 there is no documentation on it at the ARM corporate website. 186 187 Say Y if you want support for the ARM926T processor. 188 Otherwise, say N. 189 190# ARM940T 191config CPU_ARM940T 192 bool "Support ARM940T processor" if ARCH_INTEGRATOR 193 depends on !MMU 194 select CPU_32v4T 195 select CPU_ABRT_NOMMU 196 select CPU_CACHE_VIVT 197 select CPU_CP15_MPU 198 help 199 ARM940T is a member of the ARM9TDMI family of general- 200 purpose microprocessors with MPU and separate 4KB 201 instruction and 4KB data cases, each with a 4-word line 202 length. 203 204 Say Y if you want support for the ARM940T processor. 205 Otherwise, say N. 206 207# ARM946E-S 208config CPU_ARM946E 209 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR 210 depends on !MMU 211 select CPU_32v5 212 select CPU_ABRT_NOMMU 213 select CPU_CACHE_VIVT 214 select CPU_CP15_MPU 215 help 216 ARM946E-S is a member of the ARM9E-S family of high- 217 performance, 32-bit system-on-chip processor solutions. 218 The TCM and ARMv5TE 32-bit instruction set is supported. 219 220 Say Y if you want support for the ARM946E-S processor. 221 Otherwise, say N. 222 223# ARM1020 - needs validating 224config CPU_ARM1020 225 bool "Support ARM1020T (rev 0) processor" 226 depends on ARCH_INTEGRATOR 227 select CPU_32v5 228 select CPU_ABRT_EV4T 229 select CPU_CACHE_V4WT 230 select CPU_CACHE_VIVT 231 select CPU_CP15_MMU 232 select CPU_COPY_V4WB if MMU 233 select CPU_TLB_V4WBI if MMU 234 help 235 The ARM1020 is the 32K cached version of the ARM10 processor, 236 with an addition of a floating-point unit. 237 238 Say Y if you want support for the ARM1020 processor. 239 Otherwise, say N. 240 241# ARM1020E - needs validating 242config CPU_ARM1020E 243 bool "Support ARM1020E processor" 244 depends on ARCH_INTEGRATOR 245 select CPU_32v5 246 select CPU_ABRT_EV4T 247 select CPU_CACHE_V4WT 248 select CPU_CACHE_VIVT 249 select CPU_CP15_MMU 250 select CPU_COPY_V4WB if MMU 251 select CPU_TLB_V4WBI if MMU 252 depends on n 253 254# ARM1022E 255config CPU_ARM1022 256 bool "Support ARM1022E processor" 257 depends on ARCH_INTEGRATOR 258 select CPU_32v5 259 select CPU_ABRT_EV4T 260 select CPU_CACHE_VIVT 261 select CPU_CP15_MMU 262 select CPU_COPY_V4WB if MMU # can probably do better 263 select CPU_TLB_V4WBI if MMU 264 help 265 The ARM1022E is an implementation of the ARMv5TE architecture 266 based upon the ARM10 integer core with a 16KiB L1 Harvard cache, 267 embedded trace macrocell, and a floating-point unit. 268 269 Say Y if you want support for the ARM1022E processor. 270 Otherwise, say N. 271 272# ARM1026EJ-S 273config CPU_ARM1026 274 bool "Support ARM1026EJ-S processor" 275 depends on ARCH_INTEGRATOR 276 select CPU_32v5 277 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 278 select CPU_CACHE_VIVT 279 select CPU_CP15_MMU 280 select CPU_COPY_V4WB if MMU # can probably do better 281 select CPU_TLB_V4WBI if MMU 282 help 283 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture 284 based upon the ARM10 integer core. 285 286 Say Y if you want support for the ARM1026EJ-S processor. 287 Otherwise, say N. 288 289# SA110 290config CPU_SA110 291 bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC 292 default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI 293 select CPU_32v3 if ARCH_RPC 294 select CPU_32v4 if !ARCH_RPC 295 select CPU_ABRT_EV4 296 select CPU_CACHE_V4WB 297 select CPU_CACHE_VIVT 298 select CPU_CP15_MMU 299 select CPU_COPY_V4WB if MMU 300 select CPU_TLB_V4WB if MMU 301 help 302 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and 303 is available at five speeds ranging from 100 MHz to 233 MHz. 304 More information is available at 305 <http://developer.intel.com/design/strong/sa110.htm>. 306 307 Say Y if you want support for the SA-110 processor. 308 Otherwise, say N. 309 310# SA1100 311config CPU_SA1100 312 bool 313 depends on ARCH_SA1100 314 default y 315 select CPU_32v4 316 select CPU_ABRT_EV4 317 select CPU_CACHE_V4WB 318 select CPU_CACHE_VIVT 319 select CPU_CP15_MMU 320 select CPU_TLB_V4WB if MMU 321 322# XScale 323config CPU_XSCALE 324 bool 325 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000 326 default y 327 select CPU_32v5 328 select CPU_ABRT_EV5T 329 select CPU_CACHE_VIVT 330 select CPU_CP15_MMU 331 select CPU_TLB_V4WBI if MMU 332 333# XScale Core Version 3 334config CPU_XSC3 335 bool 336 depends on ARCH_IXP23XX || ARCH_IOP13XX 337 default y 338 select CPU_32v5 339 select CPU_ABRT_EV5T 340 select CPU_CACHE_VIVT 341 select CPU_CP15_MMU 342 select CPU_TLB_V4WBI if MMU 343 select IO_36 344 345# ARMv6 346config CPU_V6 347 bool "Support ARM V6 processor" 348 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 349 select CPU_32v6 350 select CPU_ABRT_EV6 351 select CPU_CACHE_V6 352 select CPU_CACHE_VIPT 353 select CPU_CP15_MMU 354 select CPU_COPY_V6 if MMU 355 select CPU_TLB_V6 if MMU 356 357# ARMv6k 358config CPU_32v6K 359 bool "Support ARM V6K processor extensions" if !SMP 360 depends on CPU_V6 361 default y if SMP 362 help 363 Say Y here if your ARMv6 processor supports the 'K' extension. 364 This enables the kernel to use some instructions not present 365 on previous processors, and as such a kernel build with this 366 enabled will not boot on processors with do not support these 367 instructions. 368 369# Figure out what processor architecture version we should be using. 370# This defines the compiler instruction set which depends on the machine type. 371config CPU_32v3 372 bool 373 select TLS_REG_EMUL if SMP || !MMU 374 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 375 376config CPU_32v4 377 bool 378 select TLS_REG_EMUL if SMP || !MMU 379 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 380 381config CPU_32v4T 382 bool 383 select TLS_REG_EMUL if SMP || !MMU 384 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 385 386config CPU_32v5 387 bool 388 select TLS_REG_EMUL if SMP || !MMU 389 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 390 391config CPU_32v6 392 bool 393 394# The abort model 395config CPU_ABRT_NOMMU 396 bool 397 398config CPU_ABRT_EV4 399 bool 400 401config CPU_ABRT_EV4T 402 bool 403 404config CPU_ABRT_LV4T 405 bool 406 407config CPU_ABRT_EV5T 408 bool 409 410config CPU_ABRT_EV5TJ 411 bool 412 413config CPU_ABRT_EV6 414 bool 415 416# The cache model 417config CPU_CACHE_V3 418 bool 419 420config CPU_CACHE_V4 421 bool 422 423config CPU_CACHE_V4WT 424 bool 425 426config CPU_CACHE_V4WB 427 bool 428 429config CPU_CACHE_V6 430 bool 431 432config CPU_CACHE_VIVT 433 bool 434 435config CPU_CACHE_VIPT 436 bool 437 438if MMU 439# The copy-page model 440config CPU_COPY_V3 441 bool 442 443config CPU_COPY_V4WT 444 bool 445 446config CPU_COPY_V4WB 447 bool 448 449config CPU_COPY_V6 450 bool 451 452# This selects the TLB model 453config CPU_TLB_V3 454 bool 455 help 456 ARM Architecture Version 3 TLB. 457 458config CPU_TLB_V4WT 459 bool 460 help 461 ARM Architecture Version 4 TLB with writethrough cache. 462 463config CPU_TLB_V4WB 464 bool 465 help 466 ARM Architecture Version 4 TLB with writeback cache. 467 468config CPU_TLB_V4WBI 469 bool 470 help 471 ARM Architecture Version 4 TLB with writeback cache and invalidate 472 instruction cache entry. 473 474config CPU_TLB_V6 475 bool 476 477endif 478 479config CPU_CP15 480 bool 481 help 482 Processor has the CP15 register. 483 484config CPU_CP15_MMU 485 bool 486 select CPU_CP15 487 help 488 Processor has the CP15 register, which has MMU related registers. 489 490config CPU_CP15_MPU 491 bool 492 select CPU_CP15 493 help 494 Processor has the CP15 register, which has MPU related registers. 495 496# 497# CPU supports 36-bit I/O 498# 499config IO_36 500 bool 501 502comment "Processor Features" 503 504config ARM_THUMB 505 bool "Support Thumb user binaries" 506 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 507 default y 508 help 509 Say Y if you want to include kernel support for running user space 510 Thumb binaries. 511 512 The Thumb instruction set is a compressed form of the standard ARM 513 instruction set resulting in smaller binaries at the expense of 514 slightly less efficient code. 515 516 If you don't know what this all is, saying Y is a safe choice. 517 518config CPU_BIG_ENDIAN 519 bool "Build big-endian kernel" 520 depends on ARCH_SUPPORTS_BIG_ENDIAN 521 help 522 Say Y if you plan on running a kernel in big-endian mode. 523 Note that your board must be properly built and your board 524 port must properly enable any big-endian related features 525 of your chipset/board/processor. 526 527config CPU_HIGH_VECTOR 528 depends on !MMU && CPU_CP15 && !CPU_ARM740T 529 bool "Select the High exception vector" 530 default n 531 help 532 Say Y here to select high exception vector(0xFFFF0000~). 533 The exception vector can be vary depending on the platform 534 design in nommu mode. If your platform needs to select 535 high exception vector, say Y. 536 Otherwise or if you are unsure, say N, and the low exception 537 vector (0x00000000~) will be used. 538 539config CPU_ICACHE_DISABLE 540 bool "Disable I-Cache (I-bit)" 541 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) 542 help 543 Say Y here to disable the processor instruction cache. Unless 544 you have a reason not to or are unsure, say N. 545 546config CPU_DCACHE_DISABLE 547 bool "Disable D-Cache (C-bit)" 548 depends on CPU_CP15 549 help 550 Say Y here to disable the processor data cache. Unless 551 you have a reason not to or are unsure, say N. 552 553config CPU_DCACHE_SIZE 554 hex 555 depends on CPU_ARM740T || CPU_ARM946E 556 default 0x00001000 if CPU_ARM740T 557 default 0x00002000 # default size for ARM946E-S 558 help 559 Some cores are synthesizable to have various sized cache. For 560 ARM946E-S case, it can vary from 0KB to 1MB. 561 To support such cache operations, it is efficient to know the size 562 before compile time. 563 If your SoC is configured to have a different size, define the value 564 here with proper conditions. 565 566config CPU_DCACHE_WRITETHROUGH 567 bool "Force write through D-cache" 568 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE 569 default y if CPU_ARM925T 570 help 571 Say Y here to use the data cache in writethrough mode. Unless you 572 specifically require this or are unsure, say N. 573 574config CPU_CACHE_ROUND_ROBIN 575 bool "Round robin I and D cache replacement algorithm" 576 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) 577 help 578 Say Y here to use the predictable round-robin cache replacement 579 policy. Unless you specifically require this or are unsure, say N. 580 581config CPU_BPREDICT_DISABLE 582 bool "Disable branch prediction" 583 depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 584 help 585 Say Y here to disable branch prediction. If unsure, say N. 586 587config TLS_REG_EMUL 588 bool 589 help 590 An SMP system using a pre-ARMv6 processor (there are apparently 591 a few prototypes like that in existence) and therefore access to 592 that required register must be emulated. 593 594config HAS_TLS_REG 595 bool 596 depends on !TLS_REG_EMUL 597 default y if SMP || CPU_32v7 598 help 599 This selects support for the CP15 thread register. 600 It is defined to be available on some ARMv6 processors (including 601 all SMP capable ARMv6's) or later processors. User space may 602 assume directly accessing that register and always obtain the 603 expected value only on ARMv7 and above. 604 605config NEEDS_SYSCALL_FOR_CMPXCHG 606 bool 607 help 608 SMP on a pre-ARMv6 processor? Well OK then. 609 Forget about fast user space cmpxchg support. 610 It is just not possible. 611 612config OUTER_CACHE 613 bool 614 default n 615 616config CACHE_L2X0 617 bool 618 select OUTER_CACHE 619