1comment "Processor Type" 2 3# Select CPU types depending on the architecture selected. This selects 4# which CPUs we support in the kernel image, and the compiler instruction 5# optimiser behaviour. 6 7# ARM610 8config CPU_ARM610 9 bool "Support ARM610 processor" if ARCH_RPC 10 select CPU_32v3 11 select CPU_CACHE_V3 12 select CPU_CACHE_VIVT 13 select CPU_CP15_MMU 14 select CPU_COPY_V3 if MMU 15 select CPU_TLB_V3 if MMU 16 select CPU_PABRT_LEGACY 17 help 18 The ARM610 is the successor to the ARM3 processor 19 and was produced by VLSI Technology Inc. 20 21 Say Y if you want support for the ARM610 processor. 22 Otherwise, say N. 23 24# ARM7TDMI 25config CPU_ARM7TDMI 26 bool "Support ARM7TDMI processor" 27 depends on !MMU 28 select CPU_32v4T 29 select CPU_ABRT_LV4T 30 select CPU_PABRT_LEGACY 31 select CPU_CACHE_V4 32 help 33 A 32-bit RISC microprocessor based on the ARM7 processor core 34 which has no memory control unit and cache. 35 36 Say Y if you want support for the ARM7TDMI processor. 37 Otherwise, say N. 38 39# ARM710 40config CPU_ARM710 41 bool "Support ARM710 processor" if ARCH_RPC 42 select CPU_32v3 43 select CPU_CACHE_V3 44 select CPU_CACHE_VIVT 45 select CPU_CP15_MMU 46 select CPU_COPY_V3 if MMU 47 select CPU_TLB_V3 if MMU 48 select CPU_PABRT_LEGACY 49 help 50 A 32-bit RISC microprocessor based on the ARM7 processor core 51 designed by Advanced RISC Machines Ltd. The ARM710 is the 52 successor to the ARM610 processor. It was released in 53 July 1994 by VLSI Technology Inc. 54 55 Say Y if you want support for the ARM710 processor. 56 Otherwise, say N. 57 58# ARM720T 59config CPU_ARM720T 60 bool "Support ARM720T processor" if ARCH_INTEGRATOR 61 select CPU_32v4T 62 select CPU_ABRT_LV4T 63 select CPU_PABRT_LEGACY 64 select CPU_CACHE_V4 65 select CPU_CACHE_VIVT 66 select CPU_CP15_MMU 67 select CPU_COPY_V4WT if MMU 68 select CPU_TLB_V4WT if MMU 69 help 70 A 32-bit RISC processor with 8kByte Cache, Write Buffer and 71 MMU built around an ARM7TDMI core. 72 73 Say Y if you want support for the ARM720T processor. 74 Otherwise, say N. 75 76# ARM740T 77config CPU_ARM740T 78 bool "Support ARM740T processor" if ARCH_INTEGRATOR 79 depends on !MMU 80 select CPU_32v4T 81 select CPU_ABRT_LV4T 82 select CPU_PABRT_LEGACY 83 select CPU_CACHE_V3 # although the core is v4t 84 select CPU_CP15_MPU 85 help 86 A 32-bit RISC processor with 8KB cache or 4KB variants, 87 write buffer and MPU(Protection Unit) built around 88 an ARM7TDMI core. 89 90 Say Y if you want support for the ARM740T processor. 91 Otherwise, say N. 92 93# ARM9TDMI 94config CPU_ARM9TDMI 95 bool "Support ARM9TDMI processor" 96 depends on !MMU 97 select CPU_32v4T 98 select CPU_ABRT_NOMMU 99 select CPU_PABRT_LEGACY 100 select CPU_CACHE_V4 101 help 102 A 32-bit RISC microprocessor based on the ARM9 processor core 103 which has no memory control unit and cache. 104 105 Say Y if you want support for the ARM9TDMI processor. 106 Otherwise, say N. 107 108# ARM920T 109config CPU_ARM920T 110 bool "Support ARM920T processor" if ARCH_INTEGRATOR 111 select CPU_32v4T 112 select CPU_ABRT_EV4T 113 select CPU_PABRT_LEGACY 114 select CPU_CACHE_V4WT 115 select CPU_CACHE_VIVT 116 select CPU_CP15_MMU 117 select CPU_COPY_V4WB if MMU 118 select CPU_TLB_V4WBI if MMU 119 help 120 The ARM920T is licensed to be produced by numerous vendors, 121 and is used in the Cirrus EP93xx and the Samsung S3C2410. 122 123 Say Y if you want support for the ARM920T processor. 124 Otherwise, say N. 125 126# ARM922T 127config CPU_ARM922T 128 bool "Support ARM922T processor" if ARCH_INTEGRATOR 129 select CPU_32v4T 130 select CPU_ABRT_EV4T 131 select CPU_PABRT_LEGACY 132 select CPU_CACHE_V4WT 133 select CPU_CACHE_VIVT 134 select CPU_CP15_MMU 135 select CPU_COPY_V4WB if MMU 136 select CPU_TLB_V4WBI if MMU 137 help 138 The ARM922T is a version of the ARM920T, but with smaller 139 instruction and data caches. It is used in Altera's 140 Excalibur XA device family and Micrel's KS8695 Centaur. 141 142 Say Y if you want support for the ARM922T processor. 143 Otherwise, say N. 144 145# ARM925T 146config CPU_ARM925T 147 bool "Support ARM925T processor" if ARCH_OMAP1 148 select CPU_32v4T 149 select CPU_ABRT_EV4T 150 select CPU_PABRT_LEGACY 151 select CPU_CACHE_V4WT 152 select CPU_CACHE_VIVT 153 select CPU_CP15_MMU 154 select CPU_COPY_V4WB if MMU 155 select CPU_TLB_V4WBI if MMU 156 help 157 The ARM925T is a mix between the ARM920T and ARM926T, but with 158 different instruction and data caches. It is used in TI's OMAP 159 device family. 160 161 Say Y if you want support for the ARM925T processor. 162 Otherwise, say N. 163 164# ARM926T 165config CPU_ARM926T 166 bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB 167 select CPU_32v5 168 select CPU_ABRT_EV5TJ 169 select CPU_PABRT_LEGACY 170 select CPU_CACHE_VIVT 171 select CPU_CP15_MMU 172 select CPU_COPY_V4WB if MMU 173 select CPU_TLB_V4WBI if MMU 174 help 175 This is a variant of the ARM920. It has slightly different 176 instruction sequences for cache and TLB operations. Curiously, 177 there is no documentation on it at the ARM corporate website. 178 179 Say Y if you want support for the ARM926T processor. 180 Otherwise, say N. 181 182# FA526 183config CPU_FA526 184 bool 185 select CPU_32v4 186 select CPU_ABRT_EV4 187 select CPU_PABRT_LEGACY 188 select CPU_CACHE_VIVT 189 select CPU_CP15_MMU 190 select CPU_CACHE_FA 191 select CPU_COPY_FA if MMU 192 select CPU_TLB_FA if MMU 193 help 194 The FA526 is a version of the ARMv4 compatible processor with 195 Branch Target Buffer, Unified TLB and cache line size 16. 196 197 Say Y if you want support for the FA526 processor. 198 Otherwise, say N. 199 200# ARM940T 201config CPU_ARM940T 202 bool "Support ARM940T processor" if ARCH_INTEGRATOR 203 depends on !MMU 204 select CPU_32v4T 205 select CPU_ABRT_NOMMU 206 select CPU_PABRT_LEGACY 207 select CPU_CACHE_VIVT 208 select CPU_CP15_MPU 209 help 210 ARM940T is a member of the ARM9TDMI family of general- 211 purpose microprocessors with MPU and separate 4KB 212 instruction and 4KB data cases, each with a 4-word line 213 length. 214 215 Say Y if you want support for the ARM940T processor. 216 Otherwise, say N. 217 218# ARM946E-S 219config CPU_ARM946E 220 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR 221 depends on !MMU 222 select CPU_32v5 223 select CPU_ABRT_NOMMU 224 select CPU_PABRT_LEGACY 225 select CPU_CACHE_VIVT 226 select CPU_CP15_MPU 227 help 228 ARM946E-S is a member of the ARM9E-S family of high- 229 performance, 32-bit system-on-chip processor solutions. 230 The TCM and ARMv5TE 32-bit instruction set is supported. 231 232 Say Y if you want support for the ARM946E-S processor. 233 Otherwise, say N. 234 235# ARM1020 - needs validating 236config CPU_ARM1020 237 bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR 238 select CPU_32v5 239 select CPU_ABRT_EV4T 240 select CPU_PABRT_LEGACY 241 select CPU_CACHE_V4WT 242 select CPU_CACHE_VIVT 243 select CPU_CP15_MMU 244 select CPU_COPY_V4WB if MMU 245 select CPU_TLB_V4WBI if MMU 246 help 247 The ARM1020 is the 32K cached version of the ARM10 processor, 248 with an addition of a floating-point unit. 249 250 Say Y if you want support for the ARM1020 processor. 251 Otherwise, say N. 252 253# ARM1020E - needs validating 254config CPU_ARM1020E 255 bool "Support ARM1020E processor" if ARCH_INTEGRATOR 256 select CPU_32v5 257 select CPU_ABRT_EV4T 258 select CPU_PABRT_LEGACY 259 select CPU_CACHE_V4WT 260 select CPU_CACHE_VIVT 261 select CPU_CP15_MMU 262 select CPU_COPY_V4WB if MMU 263 select CPU_TLB_V4WBI if MMU 264 depends on n 265 266# ARM1022E 267config CPU_ARM1022 268 bool "Support ARM1022E processor" if ARCH_INTEGRATOR 269 select CPU_32v5 270 select CPU_ABRT_EV4T 271 select CPU_PABRT_LEGACY 272 select CPU_CACHE_VIVT 273 select CPU_CP15_MMU 274 select CPU_COPY_V4WB if MMU # can probably do better 275 select CPU_TLB_V4WBI if MMU 276 help 277 The ARM1022E is an implementation of the ARMv5TE architecture 278 based upon the ARM10 integer core with a 16KiB L1 Harvard cache, 279 embedded trace macrocell, and a floating-point unit. 280 281 Say Y if you want support for the ARM1022E processor. 282 Otherwise, say N. 283 284# ARM1026EJ-S 285config CPU_ARM1026 286 bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR 287 select CPU_32v5 288 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 289 select CPU_PABRT_LEGACY 290 select CPU_CACHE_VIVT 291 select CPU_CP15_MMU 292 select CPU_COPY_V4WB if MMU # can probably do better 293 select CPU_TLB_V4WBI if MMU 294 help 295 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture 296 based upon the ARM10 integer core. 297 298 Say Y if you want support for the ARM1026EJ-S processor. 299 Otherwise, say N. 300 301# SA110 302config CPU_SA110 303 bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC 304 select CPU_32v3 if ARCH_RPC 305 select CPU_32v4 if !ARCH_RPC 306 select CPU_ABRT_EV4 307 select CPU_PABRT_LEGACY 308 select CPU_CACHE_V4WB 309 select CPU_CACHE_VIVT 310 select CPU_CP15_MMU 311 select CPU_COPY_V4WB if MMU 312 select CPU_TLB_V4WB if MMU 313 help 314 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and 315 is available at five speeds ranging from 100 MHz to 233 MHz. 316 More information is available at 317 <http://developer.intel.com/design/strong/sa110.htm>. 318 319 Say Y if you want support for the SA-110 processor. 320 Otherwise, say N. 321 322# SA1100 323config CPU_SA1100 324 bool 325 select CPU_32v4 326 select CPU_ABRT_EV4 327 select CPU_PABRT_LEGACY 328 select CPU_CACHE_V4WB 329 select CPU_CACHE_VIVT 330 select CPU_CP15_MMU 331 select CPU_TLB_V4WB if MMU 332 333# XScale 334config CPU_XSCALE 335 bool 336 select CPU_32v5 337 select CPU_ABRT_EV5T 338 select CPU_PABRT_LEGACY 339 select CPU_CACHE_VIVT 340 select CPU_CP15_MMU 341 select CPU_TLB_V4WBI if MMU 342 343# XScale Core Version 3 344config CPU_XSC3 345 bool 346 select CPU_32v5 347 select CPU_ABRT_EV5T 348 select CPU_PABRT_LEGACY 349 select CPU_CACHE_VIVT 350 select CPU_CP15_MMU 351 select CPU_TLB_V4WBI if MMU 352 select IO_36 353 354# Marvell PJ1 (Mohawk) 355config CPU_MOHAWK 356 bool 357 select CPU_32v5 358 select CPU_ABRT_EV5T 359 select CPU_PABRT_LEGACY 360 select CPU_CACHE_VIVT 361 select CPU_CP15_MMU 362 select CPU_TLB_V4WBI if MMU 363 select CPU_COPY_V4WB if MMU 364 365# Feroceon 366config CPU_FEROCEON 367 bool 368 select CPU_32v5 369 select CPU_ABRT_EV5T 370 select CPU_PABRT_LEGACY 371 select CPU_CACHE_VIVT 372 select CPU_CP15_MMU 373 select CPU_COPY_FEROCEON if MMU 374 select CPU_TLB_FEROCEON if MMU 375 376config CPU_FEROCEON_OLD_ID 377 bool "Accept early Feroceon cores with an ARM926 ID" 378 depends on CPU_FEROCEON && !CPU_ARM926T 379 default y 380 help 381 This enables the usage of some old Feroceon cores 382 for which the CPU ID is equal to the ARM926 ID. 383 Relevant for Feroceon-1850 and early Feroceon-2850. 384 385# ARMv6 386config CPU_V6 387 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_DOVE 388 select CPU_32v6 389 select CPU_ABRT_EV6 390 select CPU_PABRT_V6 391 select CPU_CACHE_V6 392 select CPU_CACHE_VIPT 393 select CPU_CP15_MMU 394 select CPU_HAS_ASID if MMU 395 select CPU_COPY_V6 if MMU 396 select CPU_TLB_V6 if MMU 397 398# ARMv6k 399config CPU_32v6K 400 bool "Support ARM V6K processor extensions" if !SMP 401 depends on CPU_V6 402 default y if SMP && !ARCH_MX3 403 help 404 Say Y here if your ARMv6 processor supports the 'K' extension. 405 This enables the kernel to use some instructions not present 406 on previous processors, and as such a kernel build with this 407 enabled will not boot on processors with do not support these 408 instructions. 409 410# ARMv7 411config CPU_V7 412 bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX 413 select CPU_32v6K 414 select CPU_32v7 415 select CPU_ABRT_EV7 416 select CPU_PABRT_V7 417 select CPU_CACHE_V7 418 select CPU_CACHE_VIPT 419 select CPU_CP15_MMU 420 select CPU_HAS_ASID if MMU 421 select CPU_COPY_V6 if MMU 422 select CPU_TLB_V7 if MMU 423 424# Figure out what processor architecture version we should be using. 425# This defines the compiler instruction set which depends on the machine type. 426config CPU_32v3 427 bool 428 select TLS_REG_EMUL if SMP || !MMU 429 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 430 431config CPU_32v4 432 bool 433 select TLS_REG_EMUL if SMP || !MMU 434 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 435 436config CPU_32v4T 437 bool 438 select TLS_REG_EMUL if SMP || !MMU 439 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 440 441config CPU_32v5 442 bool 443 select TLS_REG_EMUL if SMP || !MMU 444 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 445 446config CPU_32v6 447 bool 448 select TLS_REG_EMUL if !CPU_32v6K && !MMU 449 450config CPU_32v7 451 bool 452 453# The abort model 454config CPU_ABRT_NOMMU 455 bool 456 457config CPU_ABRT_EV4 458 bool 459 460config CPU_ABRT_EV4T 461 bool 462 463config CPU_ABRT_LV4T 464 bool 465 466config CPU_ABRT_EV5T 467 bool 468 469config CPU_ABRT_EV5TJ 470 bool 471 472config CPU_ABRT_EV6 473 bool 474 475config CPU_ABRT_EV7 476 bool 477 478config CPU_PABRT_LEGACY 479 bool 480 481config CPU_PABRT_V6 482 bool 483 484config CPU_PABRT_V7 485 bool 486 487# The cache model 488config CPU_CACHE_V3 489 bool 490 491config CPU_CACHE_V4 492 bool 493 494config CPU_CACHE_V4WT 495 bool 496 497config CPU_CACHE_V4WB 498 bool 499 500config CPU_CACHE_V6 501 bool 502 503config CPU_CACHE_V7 504 bool 505 506config CPU_CACHE_VIVT 507 bool 508 509config CPU_CACHE_VIPT 510 bool 511 512config CPU_CACHE_FA 513 bool 514 515if MMU 516# The copy-page model 517config CPU_COPY_V3 518 bool 519 520config CPU_COPY_V4WT 521 bool 522 523config CPU_COPY_V4WB 524 bool 525 526config CPU_COPY_FEROCEON 527 bool 528 529config CPU_COPY_FA 530 bool 531 532config CPU_COPY_V6 533 bool 534 535# This selects the TLB model 536config CPU_TLB_V3 537 bool 538 help 539 ARM Architecture Version 3 TLB. 540 541config CPU_TLB_V4WT 542 bool 543 help 544 ARM Architecture Version 4 TLB with writethrough cache. 545 546config CPU_TLB_V4WB 547 bool 548 help 549 ARM Architecture Version 4 TLB with writeback cache. 550 551config CPU_TLB_V4WBI 552 bool 553 help 554 ARM Architecture Version 4 TLB with writeback cache and invalidate 555 instruction cache entry. 556 557config CPU_TLB_FEROCEON 558 bool 559 help 560 Feroceon TLB (v4wbi with non-outer-cachable page table walks). 561 562config CPU_TLB_FA 563 bool 564 help 565 Faraday ARM FA526 architecture, unified TLB with writeback cache 566 and invalidate instruction cache entry. Branch target buffer is 567 also supported. 568 569config CPU_TLB_V6 570 bool 571 572config CPU_TLB_V7 573 bool 574 575endif 576 577config CPU_HAS_ASID 578 bool 579 help 580 This indicates whether the CPU has the ASID register; used to 581 tag TLB and possibly cache entries. 582 583config CPU_CP15 584 bool 585 help 586 Processor has the CP15 register. 587 588config CPU_CP15_MMU 589 bool 590 select CPU_CP15 591 help 592 Processor has the CP15 register, which has MMU related registers. 593 594config CPU_CP15_MPU 595 bool 596 select CPU_CP15 597 help 598 Processor has the CP15 register, which has MPU related registers. 599 600# 601# CPU supports 36-bit I/O 602# 603config IO_36 604 bool 605 606comment "Processor Features" 607 608config ARM_THUMB 609 bool "Support Thumb user binaries" 610 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V7 || CPU_FEROCEON 611 default y 612 help 613 Say Y if you want to include kernel support for running user space 614 Thumb binaries. 615 616 The Thumb instruction set is a compressed form of the standard ARM 617 instruction set resulting in smaller binaries at the expense of 618 slightly less efficient code. 619 620 If you don't know what this all is, saying Y is a safe choice. 621 622config ARM_THUMBEE 623 bool "Enable ThumbEE CPU extension" 624 depends on CPU_V7 625 help 626 Say Y here if you have a CPU with the ThumbEE extension and code to 627 make use of it. Say N for code that can run on CPUs without ThumbEE. 628 629config CPU_BIG_ENDIAN 630 bool "Build big-endian kernel" 631 depends on ARCH_SUPPORTS_BIG_ENDIAN 632 help 633 Say Y if you plan on running a kernel in big-endian mode. 634 Note that your board must be properly built and your board 635 port must properly enable any big-endian related features 636 of your chipset/board/processor. 637 638config CPU_ENDIAN_BE8 639 bool 640 depends on CPU_BIG_ENDIAN 641 default CPU_V6 || CPU_V7 642 help 643 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors. 644 645config CPU_ENDIAN_BE32 646 bool 647 depends on CPU_BIG_ENDIAN 648 default !CPU_ENDIAN_BE8 649 help 650 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors. 651 652config CPU_HIGH_VECTOR 653 depends on !MMU && CPU_CP15 && !CPU_ARM740T 654 bool "Select the High exception vector" 655 help 656 Say Y here to select high exception vector(0xFFFF0000~). 657 The exception vector can be vary depending on the platform 658 design in nommu mode. If your platform needs to select 659 high exception vector, say Y. 660 Otherwise or if you are unsure, say N, and the low exception 661 vector (0x00000000~) will be used. 662 663config CPU_ICACHE_DISABLE 664 bool "Disable I-Cache (I-bit)" 665 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) 666 help 667 Say Y here to disable the processor instruction cache. Unless 668 you have a reason not to or are unsure, say N. 669 670config CPU_DCACHE_DISABLE 671 bool "Disable D-Cache (C-bit)" 672 depends on CPU_CP15 673 help 674 Say Y here to disable the processor data cache. Unless 675 you have a reason not to or are unsure, say N. 676 677config CPU_DCACHE_SIZE 678 hex 679 depends on CPU_ARM740T || CPU_ARM946E 680 default 0x00001000 if CPU_ARM740T 681 default 0x00002000 # default size for ARM946E-S 682 help 683 Some cores are synthesizable to have various sized cache. For 684 ARM946E-S case, it can vary from 0KB to 1MB. 685 To support such cache operations, it is efficient to know the size 686 before compile time. 687 If your SoC is configured to have a different size, define the value 688 here with proper conditions. 689 690config CPU_DCACHE_WRITETHROUGH 691 bool "Force write through D-cache" 692 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE 693 default y if CPU_ARM925T 694 help 695 Say Y here to use the data cache in writethrough mode. Unless you 696 specifically require this or are unsure, say N. 697 698config CPU_CACHE_ROUND_ROBIN 699 bool "Round robin I and D cache replacement algorithm" 700 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) 701 help 702 Say Y here to use the predictable round-robin cache replacement 703 policy. Unless you specifically require this or are unsure, say N. 704 705config CPU_BPREDICT_DISABLE 706 bool "Disable branch prediction" 707 depends on CPU_ARM1020 || CPU_V6 || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 708 help 709 Say Y here to disable branch prediction. If unsure, say N. 710 711config TLS_REG_EMUL 712 bool 713 help 714 An SMP system using a pre-ARMv6 processor (there are apparently 715 a few prototypes like that in existence) and therefore access to 716 that required register must be emulated. 717 718config HAS_TLS_REG 719 bool 720 depends on !TLS_REG_EMUL 721 default y if SMP || CPU_32v7 722 help 723 This selects support for the CP15 thread register. 724 It is defined to be available on some ARMv6 processors (including 725 all SMP capable ARMv6's) or later processors. User space may 726 assume directly accessing that register and always obtain the 727 expected value only on ARMv7 and above. 728 729config NEEDS_SYSCALL_FOR_CMPXCHG 730 bool 731 help 732 SMP on a pre-ARMv6 processor? Well OK then. 733 Forget about fast user space cmpxchg support. 734 It is just not possible. 735 736config OUTER_CACHE 737 bool 738 739config CACHE_FEROCEON_L2 740 bool "Enable the Feroceon L2 cache controller" 741 depends on ARCH_KIRKWOOD || ARCH_MV78XX0 742 default y 743 select OUTER_CACHE 744 help 745 This option enables the Feroceon L2 cache controller. 746 747config CACHE_FEROCEON_L2_WRITETHROUGH 748 bool "Force Feroceon L2 cache write through" 749 depends on CACHE_FEROCEON_L2 750 help 751 Say Y here to use the Feroceon L2 cache in writethrough mode. 752 Unless you specifically require this, say N for writeback mode. 753 754config CACHE_L2X0 755 bool "Enable the L2x0 outer cache controller" 756 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ 757 REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK 758 default y 759 select OUTER_CACHE 760 help 761 This option enables the L2x0 PrimeCell. 762 763config CACHE_TAUROS2 764 bool "Enable the Tauros2 L2 cache controller" 765 depends on ARCH_DOVE 766 default y 767 select OUTER_CACHE 768 help 769 This option enables the Tauros2 L2 cache controller (as 770 found on PJ1/PJ4). 771 772config CACHE_XSC3L2 773 bool "Enable the L2 cache on XScale3" 774 depends on CPU_XSC3 775 default y 776 select OUTER_CACHE 777 help 778 This option enables the L2 cache on XScale3. 779 780config ARM_L1_CACHE_SHIFT 781 int 782 default 6 if ARCH_OMAP3 || ARCH_S5PC1XX 783 default 5 784