1comment "Processor Type" 2 3# Select CPU types depending on the architecture selected. This selects 4# which CPUs we support in the kernel image, and the compiler instruction 5# optimiser behaviour. 6 7# ARM610 8config CPU_ARM610 9 bool "Support ARM610 processor" if ARCH_RPC 10 select CPU_32v3 11 select CPU_CACHE_V3 12 select CPU_CACHE_VIVT 13 select CPU_CP15_MMU 14 select CPU_COPY_V3 if MMU 15 select CPU_TLB_V3 if MMU 16 select CPU_PABRT_LEGACY 17 help 18 The ARM610 is the successor to the ARM3 processor 19 and was produced by VLSI Technology Inc. 20 21 Say Y if you want support for the ARM610 processor. 22 Otherwise, say N. 23 24# ARM7TDMI 25config CPU_ARM7TDMI 26 bool "Support ARM7TDMI processor" 27 depends on !MMU 28 select CPU_32v4T 29 select CPU_ABRT_LV4T 30 select CPU_PABRT_LEGACY 31 select CPU_CACHE_V4 32 help 33 A 32-bit RISC microprocessor based on the ARM7 processor core 34 which has no memory control unit and cache. 35 36 Say Y if you want support for the ARM7TDMI processor. 37 Otherwise, say N. 38 39# ARM710 40config CPU_ARM710 41 bool "Support ARM710 processor" if ARCH_RPC 42 select CPU_32v3 43 select CPU_CACHE_V3 44 select CPU_CACHE_VIVT 45 select CPU_CP15_MMU 46 select CPU_COPY_V3 if MMU 47 select CPU_TLB_V3 if MMU 48 select CPU_PABRT_LEGACY 49 help 50 A 32-bit RISC microprocessor based on the ARM7 processor core 51 designed by Advanced RISC Machines Ltd. The ARM710 is the 52 successor to the ARM610 processor. It was released in 53 July 1994 by VLSI Technology Inc. 54 55 Say Y if you want support for the ARM710 processor. 56 Otherwise, say N. 57 58# ARM720T 59config CPU_ARM720T 60 bool "Support ARM720T processor" if ARCH_INTEGRATOR 61 select CPU_32v4T 62 select CPU_ABRT_LV4T 63 select CPU_PABRT_LEGACY 64 select CPU_CACHE_V4 65 select CPU_CACHE_VIVT 66 select CPU_CP15_MMU 67 select CPU_COPY_V4WT if MMU 68 select CPU_TLB_V4WT if MMU 69 help 70 A 32-bit RISC processor with 8kByte Cache, Write Buffer and 71 MMU built around an ARM7TDMI core. 72 73 Say Y if you want support for the ARM720T processor. 74 Otherwise, say N. 75 76# ARM740T 77config CPU_ARM740T 78 bool "Support ARM740T processor" if ARCH_INTEGRATOR 79 depends on !MMU 80 select CPU_32v4T 81 select CPU_ABRT_LV4T 82 select CPU_PABRT_LEGACY 83 select CPU_CACHE_V3 # although the core is v4t 84 select CPU_CP15_MPU 85 help 86 A 32-bit RISC processor with 8KB cache or 4KB variants, 87 write buffer and MPU(Protection Unit) built around 88 an ARM7TDMI core. 89 90 Say Y if you want support for the ARM740T processor. 91 Otherwise, say N. 92 93# ARM9TDMI 94config CPU_ARM9TDMI 95 bool "Support ARM9TDMI processor" 96 depends on !MMU 97 select CPU_32v4T 98 select CPU_ABRT_NOMMU 99 select CPU_PABRT_LEGACY 100 select CPU_CACHE_V4 101 help 102 A 32-bit RISC microprocessor based on the ARM9 processor core 103 which has no memory control unit and cache. 104 105 Say Y if you want support for the ARM9TDMI processor. 106 Otherwise, say N. 107 108# ARM920T 109config CPU_ARM920T 110 bool "Support ARM920T processor" if ARCH_INTEGRATOR 111 select CPU_32v4T 112 select CPU_ABRT_EV4T 113 select CPU_PABRT_LEGACY 114 select CPU_CACHE_V4WT 115 select CPU_CACHE_VIVT 116 select CPU_CP15_MMU 117 select CPU_COPY_V4WB if MMU 118 select CPU_TLB_V4WBI if MMU 119 help 120 The ARM920T is licensed to be produced by numerous vendors, 121 and is used in the Cirrus EP93xx and the Samsung S3C2410. 122 123 Say Y if you want support for the ARM920T processor. 124 Otherwise, say N. 125 126# ARM922T 127config CPU_ARM922T 128 bool "Support ARM922T processor" if ARCH_INTEGRATOR 129 select CPU_32v4T 130 select CPU_ABRT_EV4T 131 select CPU_PABRT_LEGACY 132 select CPU_CACHE_V4WT 133 select CPU_CACHE_VIVT 134 select CPU_CP15_MMU 135 select CPU_COPY_V4WB if MMU 136 select CPU_TLB_V4WBI if MMU 137 help 138 The ARM922T is a version of the ARM920T, but with smaller 139 instruction and data caches. It is used in Altera's 140 Excalibur XA device family and Micrel's KS8695 Centaur. 141 142 Say Y if you want support for the ARM922T processor. 143 Otherwise, say N. 144 145# ARM925T 146config CPU_ARM925T 147 bool "Support ARM925T processor" if ARCH_OMAP1 148 select CPU_32v4T 149 select CPU_ABRT_EV4T 150 select CPU_PABRT_LEGACY 151 select CPU_CACHE_V4WT 152 select CPU_CACHE_VIVT 153 select CPU_CP15_MMU 154 select CPU_COPY_V4WB if MMU 155 select CPU_TLB_V4WBI if MMU 156 help 157 The ARM925T is a mix between the ARM920T and ARM926T, but with 158 different instruction and data caches. It is used in TI's OMAP 159 device family. 160 161 Say Y if you want support for the ARM925T processor. 162 Otherwise, say N. 163 164# ARM926T 165config CPU_ARM926T 166 bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB 167 select CPU_32v5 168 select CPU_ABRT_EV5TJ 169 select CPU_PABRT_LEGACY 170 select CPU_CACHE_VIVT 171 select CPU_CP15_MMU 172 select CPU_COPY_V4WB if MMU 173 select CPU_TLB_V4WBI if MMU 174 help 175 This is a variant of the ARM920. It has slightly different 176 instruction sequences for cache and TLB operations. Curiously, 177 there is no documentation on it at the ARM corporate website. 178 179 Say Y if you want support for the ARM926T processor. 180 Otherwise, say N. 181 182# FA526 183config CPU_FA526 184 bool 185 select CPU_32v4 186 select CPU_ABRT_EV4 187 select CPU_PABRT_LEGACY 188 select CPU_CACHE_VIVT 189 select CPU_CP15_MMU 190 select CPU_CACHE_FA 191 select CPU_COPY_FA if MMU 192 select CPU_TLB_FA if MMU 193 help 194 The FA526 is a version of the ARMv4 compatible processor with 195 Branch Target Buffer, Unified TLB and cache line size 16. 196 197 Say Y if you want support for the FA526 processor. 198 Otherwise, say N. 199 200# ARM940T 201config CPU_ARM940T 202 bool "Support ARM940T processor" if ARCH_INTEGRATOR 203 depends on !MMU 204 select CPU_32v4T 205 select CPU_ABRT_NOMMU 206 select CPU_PABRT_LEGACY 207 select CPU_CACHE_VIVT 208 select CPU_CP15_MPU 209 help 210 ARM940T is a member of the ARM9TDMI family of general- 211 purpose microprocessors with MPU and separate 4KB 212 instruction and 4KB data cases, each with a 4-word line 213 length. 214 215 Say Y if you want support for the ARM940T processor. 216 Otherwise, say N. 217 218# ARM946E-S 219config CPU_ARM946E 220 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR 221 depends on !MMU 222 select CPU_32v5 223 select CPU_ABRT_NOMMU 224 select CPU_PABRT_LEGACY 225 select CPU_CACHE_VIVT 226 select CPU_CP15_MPU 227 help 228 ARM946E-S is a member of the ARM9E-S family of high- 229 performance, 32-bit system-on-chip processor solutions. 230 The TCM and ARMv5TE 32-bit instruction set is supported. 231 232 Say Y if you want support for the ARM946E-S processor. 233 Otherwise, say N. 234 235# ARM1020 - needs validating 236config CPU_ARM1020 237 bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR 238 select CPU_32v5 239 select CPU_ABRT_EV4T 240 select CPU_PABRT_LEGACY 241 select CPU_CACHE_V4WT 242 select CPU_CACHE_VIVT 243 select CPU_CP15_MMU 244 select CPU_COPY_V4WB if MMU 245 select CPU_TLB_V4WBI if MMU 246 help 247 The ARM1020 is the 32K cached version of the ARM10 processor, 248 with an addition of a floating-point unit. 249 250 Say Y if you want support for the ARM1020 processor. 251 Otherwise, say N. 252 253# ARM1020E - needs validating 254config CPU_ARM1020E 255 bool "Support ARM1020E processor" if ARCH_INTEGRATOR 256 select CPU_32v5 257 select CPU_ABRT_EV4T 258 select CPU_PABRT_LEGACY 259 select CPU_CACHE_V4WT 260 select CPU_CACHE_VIVT 261 select CPU_CP15_MMU 262 select CPU_COPY_V4WB if MMU 263 select CPU_TLB_V4WBI if MMU 264 depends on n 265 266# ARM1022E 267config CPU_ARM1022 268 bool "Support ARM1022E processor" if ARCH_INTEGRATOR 269 select CPU_32v5 270 select CPU_ABRT_EV4T 271 select CPU_PABRT_LEGACY 272 select CPU_CACHE_VIVT 273 select CPU_CP15_MMU 274 select CPU_COPY_V4WB if MMU # can probably do better 275 select CPU_TLB_V4WBI if MMU 276 help 277 The ARM1022E is an implementation of the ARMv5TE architecture 278 based upon the ARM10 integer core with a 16KiB L1 Harvard cache, 279 embedded trace macrocell, and a floating-point unit. 280 281 Say Y if you want support for the ARM1022E processor. 282 Otherwise, say N. 283 284# ARM1026EJ-S 285config CPU_ARM1026 286 bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR 287 select CPU_32v5 288 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 289 select CPU_PABRT_LEGACY 290 select CPU_CACHE_VIVT 291 select CPU_CP15_MMU 292 select CPU_COPY_V4WB if MMU # can probably do better 293 select CPU_TLB_V4WBI if MMU 294 help 295 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture 296 based upon the ARM10 integer core. 297 298 Say Y if you want support for the ARM1026EJ-S processor. 299 Otherwise, say N. 300 301# SA110 302config CPU_SA110 303 bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC 304 select CPU_32v3 if ARCH_RPC 305 select CPU_32v4 if !ARCH_RPC 306 select CPU_ABRT_EV4 307 select CPU_PABRT_LEGACY 308 select CPU_CACHE_V4WB 309 select CPU_CACHE_VIVT 310 select CPU_CP15_MMU 311 select CPU_COPY_V4WB if MMU 312 select CPU_TLB_V4WB if MMU 313 help 314 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and 315 is available at five speeds ranging from 100 MHz to 233 MHz. 316 More information is available at 317 <http://developer.intel.com/design/strong/sa110.htm>. 318 319 Say Y if you want support for the SA-110 processor. 320 Otherwise, say N. 321 322# SA1100 323config CPU_SA1100 324 bool 325 select CPU_32v4 326 select CPU_ABRT_EV4 327 select CPU_PABRT_LEGACY 328 select CPU_CACHE_V4WB 329 select CPU_CACHE_VIVT 330 select CPU_CP15_MMU 331 select CPU_TLB_V4WB if MMU 332 333# XScale 334config CPU_XSCALE 335 bool 336 select CPU_32v5 337 select CPU_ABRT_EV5T 338 select CPU_PABRT_LEGACY 339 select CPU_CACHE_VIVT 340 select CPU_CP15_MMU 341 select CPU_TLB_V4WBI if MMU 342 343# XScale Core Version 3 344config CPU_XSC3 345 bool 346 select CPU_32v5 347 select CPU_ABRT_EV5T 348 select CPU_PABRT_LEGACY 349 select CPU_CACHE_VIVT 350 select CPU_CP15_MMU 351 select CPU_TLB_V4WBI if MMU 352 select IO_36 353 354# Marvell PJ1 (Mohawk) 355config CPU_MOHAWK 356 bool 357 select CPU_32v5 358 select CPU_ABRT_EV5T 359 select CPU_PABRT_LEGACY 360 select CPU_CACHE_VIVT 361 select CPU_CP15_MMU 362 select CPU_TLB_V4WBI if MMU 363 select CPU_COPY_V4WB if MMU 364 365# Feroceon 366config CPU_FEROCEON 367 bool 368 select CPU_32v5 369 select CPU_ABRT_EV5T 370 select CPU_PABRT_LEGACY 371 select CPU_CACHE_VIVT 372 select CPU_CP15_MMU 373 select CPU_COPY_FEROCEON if MMU 374 select CPU_TLB_FEROCEON if MMU 375 376config CPU_FEROCEON_OLD_ID 377 bool "Accept early Feroceon cores with an ARM926 ID" 378 depends on CPU_FEROCEON && !CPU_ARM926T 379 default y 380 help 381 This enables the usage of some old Feroceon cores 382 for which the CPU ID is equal to the ARM926 ID. 383 Relevant for Feroceon-1850 and early Feroceon-2850. 384 385# Marvell PJ4 386config CPU_PJ4 387 bool 388 select CPU_V7 389 select ARM_THUMBEE 390 391# ARMv6 392config CPU_V6 393 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_DOVE 394 select CPU_32v6 395 select CPU_ABRT_EV6 396 select CPU_PABRT_V6 397 select CPU_CACHE_V6 398 select CPU_CACHE_VIPT 399 select CPU_CP15_MMU 400 select CPU_HAS_ASID if MMU 401 select CPU_COPY_V6 if MMU 402 select CPU_TLB_V6 if MMU 403 404# ARMv6k 405config CPU_32v6K 406 bool "Support ARM V6K processor extensions" if !SMP 407 depends on CPU_V6 || CPU_V7 408 default y if SMP 409 help 410 Say Y here if your ARMv6 processor supports the 'K' extension. 411 This enables the kernel to use some instructions not present 412 on previous processors, and as such a kernel build with this 413 enabled will not boot on processors with do not support these 414 instructions. 415 416# ARMv7 417config CPU_V7 418 bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX 419 select CPU_32v6K 420 select CPU_32v7 421 select CPU_ABRT_EV7 422 select CPU_PABRT_V7 423 select CPU_CACHE_V7 424 select CPU_CACHE_VIPT 425 select CPU_CP15_MMU 426 select CPU_HAS_ASID if MMU 427 select CPU_COPY_V6 if MMU 428 select CPU_TLB_V7 if MMU 429 430# Figure out what processor architecture version we should be using. 431# This defines the compiler instruction set which depends on the machine type. 432config CPU_32v3 433 bool 434 select TLS_REG_EMUL if SMP || !MMU 435 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 436 437config CPU_32v4 438 bool 439 select TLS_REG_EMUL if SMP || !MMU 440 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 441 442config CPU_32v4T 443 bool 444 select TLS_REG_EMUL if SMP || !MMU 445 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 446 447config CPU_32v5 448 bool 449 select TLS_REG_EMUL if SMP || !MMU 450 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 451 452config CPU_32v6 453 bool 454 select TLS_REG_EMUL if !CPU_32v6K && !MMU 455 456config CPU_32v7 457 bool 458 459# The abort model 460config CPU_ABRT_NOMMU 461 bool 462 463config CPU_ABRT_EV4 464 bool 465 466config CPU_ABRT_EV4T 467 bool 468 469config CPU_ABRT_LV4T 470 bool 471 472config CPU_ABRT_EV5T 473 bool 474 475config CPU_ABRT_EV5TJ 476 bool 477 478config CPU_ABRT_EV6 479 bool 480 481config CPU_ABRT_EV7 482 bool 483 484config CPU_PABRT_LEGACY 485 bool 486 487config CPU_PABRT_V6 488 bool 489 490config CPU_PABRT_V7 491 bool 492 493# The cache model 494config CPU_CACHE_V3 495 bool 496 497config CPU_CACHE_V4 498 bool 499 500config CPU_CACHE_V4WT 501 bool 502 503config CPU_CACHE_V4WB 504 bool 505 506config CPU_CACHE_V6 507 bool 508 509config CPU_CACHE_V7 510 bool 511 512config CPU_CACHE_VIVT 513 bool 514 515config CPU_CACHE_VIPT 516 bool 517 518config CPU_CACHE_FA 519 bool 520 521if MMU 522# The copy-page model 523config CPU_COPY_V3 524 bool 525 526config CPU_COPY_V4WT 527 bool 528 529config CPU_COPY_V4WB 530 bool 531 532config CPU_COPY_FEROCEON 533 bool 534 535config CPU_COPY_FA 536 bool 537 538config CPU_COPY_V6 539 bool 540 541# This selects the TLB model 542config CPU_TLB_V3 543 bool 544 help 545 ARM Architecture Version 3 TLB. 546 547config CPU_TLB_V4WT 548 bool 549 help 550 ARM Architecture Version 4 TLB with writethrough cache. 551 552config CPU_TLB_V4WB 553 bool 554 help 555 ARM Architecture Version 4 TLB with writeback cache. 556 557config CPU_TLB_V4WBI 558 bool 559 help 560 ARM Architecture Version 4 TLB with writeback cache and invalidate 561 instruction cache entry. 562 563config CPU_TLB_FEROCEON 564 bool 565 help 566 Feroceon TLB (v4wbi with non-outer-cachable page table walks). 567 568config CPU_TLB_FA 569 bool 570 help 571 Faraday ARM FA526 architecture, unified TLB with writeback cache 572 and invalidate instruction cache entry. Branch target buffer is 573 also supported. 574 575config CPU_TLB_V6 576 bool 577 578config CPU_TLB_V7 579 bool 580 581config VERIFY_PERMISSION_FAULT 582 bool 583endif 584 585config CPU_HAS_ASID 586 bool 587 help 588 This indicates whether the CPU has the ASID register; used to 589 tag TLB and possibly cache entries. 590 591config CPU_CP15 592 bool 593 help 594 Processor has the CP15 register. 595 596config CPU_CP15_MMU 597 bool 598 select CPU_CP15 599 help 600 Processor has the CP15 register, which has MMU related registers. 601 602config CPU_CP15_MPU 603 bool 604 select CPU_CP15 605 help 606 Processor has the CP15 register, which has MPU related registers. 607 608config CPU_USE_DOMAINS 609 bool 610 depends on MMU 611 default y if !CPU_32v6K 612 help 613 This option enables or disables the use of domain switching 614 via the set_fs() function. 615 616# 617# CPU supports 36-bit I/O 618# 619config IO_36 620 bool 621 622comment "Processor Features" 623 624config ARM_THUMB 625 bool "Support Thumb user binaries" 626 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V7 || CPU_FEROCEON 627 default y 628 help 629 Say Y if you want to include kernel support for running user space 630 Thumb binaries. 631 632 The Thumb instruction set is a compressed form of the standard ARM 633 instruction set resulting in smaller binaries at the expense of 634 slightly less efficient code. 635 636 If you don't know what this all is, saying Y is a safe choice. 637 638config ARM_THUMBEE 639 bool "Enable ThumbEE CPU extension" 640 depends on CPU_V7 641 help 642 Say Y here if you have a CPU with the ThumbEE extension and code to 643 make use of it. Say N for code that can run on CPUs without ThumbEE. 644 645config SWP_EMULATE 646 bool "Emulate SWP/SWPB instructions" 647 depends on !CPU_USE_DOMAINS && CPU_V7 && !CPU_V6 648 select HAVE_PROC_CPU if PROC_FS 649 default y if SMP 650 help 651 ARMv6 architecture deprecates use of the SWP/SWPB instructions. 652 ARMv7 multiprocessing extensions introduce the ability to disable 653 these instructions, triggering an undefined instruction exception 654 when executed. Say Y here to enable software emulation of these 655 instructions for userspace (not kernel) using LDREX/STREX. 656 Also creates /proc/cpu/swp_emulation for statistics. 657 658 In some older versions of glibc [<=2.8] SWP is used during futex 659 trylock() operations with the assumption that the code will not 660 be preempted. This invalid assumption may be more likely to fail 661 with SWP emulation enabled, leading to deadlock of the user 662 application. 663 664 NOTE: when accessing uncached shared regions, LDREX/STREX rely 665 on an external transaction monitoring block called a global 666 monitor to maintain update atomicity. If your system does not 667 implement a global monitor, this option can cause programs that 668 perform SWP operations to uncached memory to deadlock. 669 670 If unsure, say Y. 671 672config CPU_BIG_ENDIAN 673 bool "Build big-endian kernel" 674 depends on ARCH_SUPPORTS_BIG_ENDIAN 675 help 676 Say Y if you plan on running a kernel in big-endian mode. 677 Note that your board must be properly built and your board 678 port must properly enable any big-endian related features 679 of your chipset/board/processor. 680 681config CPU_ENDIAN_BE8 682 bool 683 depends on CPU_BIG_ENDIAN 684 default CPU_V6 || CPU_V7 685 help 686 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors. 687 688config CPU_ENDIAN_BE32 689 bool 690 depends on CPU_BIG_ENDIAN 691 default !CPU_ENDIAN_BE8 692 help 693 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors. 694 695config CPU_HIGH_VECTOR 696 depends on !MMU && CPU_CP15 && !CPU_ARM740T 697 bool "Select the High exception vector" 698 help 699 Say Y here to select high exception vector(0xFFFF0000~). 700 The exception vector can be vary depending on the platform 701 design in nommu mode. If your platform needs to select 702 high exception vector, say Y. 703 Otherwise or if you are unsure, say N, and the low exception 704 vector (0x00000000~) will be used. 705 706config CPU_ICACHE_DISABLE 707 bool "Disable I-Cache (I-bit)" 708 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) 709 help 710 Say Y here to disable the processor instruction cache. Unless 711 you have a reason not to or are unsure, say N. 712 713config CPU_DCACHE_DISABLE 714 bool "Disable D-Cache (C-bit)" 715 depends on CPU_CP15 716 help 717 Say Y here to disable the processor data cache. Unless 718 you have a reason not to or are unsure, say N. 719 720config CPU_DCACHE_SIZE 721 hex 722 depends on CPU_ARM740T || CPU_ARM946E 723 default 0x00001000 if CPU_ARM740T 724 default 0x00002000 # default size for ARM946E-S 725 help 726 Some cores are synthesizable to have various sized cache. For 727 ARM946E-S case, it can vary from 0KB to 1MB. 728 To support such cache operations, it is efficient to know the size 729 before compile time. 730 If your SoC is configured to have a different size, define the value 731 here with proper conditions. 732 733config CPU_DCACHE_WRITETHROUGH 734 bool "Force write through D-cache" 735 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE 736 default y if CPU_ARM925T 737 help 738 Say Y here to use the data cache in writethrough mode. Unless you 739 specifically require this or are unsure, say N. 740 741config CPU_CACHE_ROUND_ROBIN 742 bool "Round robin I and D cache replacement algorithm" 743 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) 744 help 745 Say Y here to use the predictable round-robin cache replacement 746 policy. Unless you specifically require this or are unsure, say N. 747 748config CPU_BPREDICT_DISABLE 749 bool "Disable branch prediction" 750 depends on CPU_ARM1020 || CPU_V6 || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 751 help 752 Say Y here to disable branch prediction. If unsure, say N. 753 754config TLS_REG_EMUL 755 bool 756 help 757 An SMP system using a pre-ARMv6 processor (there are apparently 758 a few prototypes like that in existence) and therefore access to 759 that required register must be emulated. 760 761config NEEDS_SYSCALL_FOR_CMPXCHG 762 bool 763 help 764 SMP on a pre-ARMv6 processor? Well OK then. 765 Forget about fast user space cmpxchg support. 766 It is just not possible. 767 768config DMA_CACHE_RWFO 769 bool "Enable read/write for ownership DMA cache maintenance" 770 depends on CPU_V6 && SMP 771 default y 772 help 773 The Snoop Control Unit on ARM11MPCore does not detect the 774 cache maintenance operations and the dma_{map,unmap}_area() 775 functions may leave stale cache entries on other CPUs. By 776 enabling this option, Read or Write For Ownership in the ARMv6 777 DMA cache maintenance functions is performed. These LDR/STR 778 instructions change the cache line state to shared or modified 779 so that the cache operation has the desired effect. 780 781 Note that the workaround is only valid on processors that do 782 not perform speculative loads into the D-cache. For such 783 processors, if cache maintenance operations are not broadcast 784 in hardware, other workarounds are needed (e.g. cache 785 maintenance broadcasting in software via FIQ). 786 787config OUTER_CACHE 788 bool 789 790config OUTER_CACHE_SYNC 791 bool 792 help 793 The outer cache has a outer_cache_fns.sync function pointer 794 that can be used to drain the write buffer of the outer cache. 795 796config CACHE_FEROCEON_L2 797 bool "Enable the Feroceon L2 cache controller" 798 depends on ARCH_KIRKWOOD || ARCH_MV78XX0 799 default y 800 select OUTER_CACHE 801 help 802 This option enables the Feroceon L2 cache controller. 803 804config CACHE_FEROCEON_L2_WRITETHROUGH 805 bool "Force Feroceon L2 cache write through" 806 depends on CACHE_FEROCEON_L2 807 help 808 Say Y here to use the Feroceon L2 cache in writethrough mode. 809 Unless you specifically require this, say N for writeback mode. 810 811config CACHE_L2X0 812 bool "Enable the L2x0 outer cache controller" 813 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ 814 REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \ 815 ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \ 816 ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE 817 default y 818 select OUTER_CACHE 819 select OUTER_CACHE_SYNC 820 help 821 This option enables the L2x0 PrimeCell. 822 823config CACHE_PL310 824 bool 825 depends on CACHE_L2X0 826 default y if CPU_V7 && !CPU_V6 827 help 828 This option enables optimisations for the PL310 cache 829 controller. 830 831config CACHE_TAUROS2 832 bool "Enable the Tauros2 L2 cache controller" 833 depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4) 834 default y 835 select OUTER_CACHE 836 help 837 This option enables the Tauros2 L2 cache controller (as 838 found on PJ1/PJ4). 839 840config CACHE_XSC3L2 841 bool "Enable the L2 cache on XScale3" 842 depends on CPU_XSC3 843 default y 844 select OUTER_CACHE 845 help 846 This option enables the L2 cache on XScale3. 847 848config ARM_L1_CACHE_SHIFT 849 int 850 default 6 if ARM_L1_CACHE_SHIFT_6 851 default 5 852 853config ARM_DMA_MEM_BUFFERABLE 854 bool "Use non-cacheable memory for DMA" if CPU_V6 && !CPU_V7 855 depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \ 856 MACH_REALVIEW_PB11MP) 857 default y if CPU_V6 || CPU_V7 858 help 859 Historically, the kernel has used strongly ordered mappings to 860 provide DMA coherent memory. With the advent of ARMv7, mapping 861 memory with differing types results in unpredictable behaviour, 862 so on these CPUs, this option is forced on. 863 864 Multiple mappings with differing attributes is also unpredictable 865 on ARMv6 CPUs, but since they do not have aggressive speculative 866 prefetch, no harm appears to occur. 867 868 However, drivers may be missing the necessary barriers for ARMv6, 869 and therefore turning this on may result in unpredictable driver 870 behaviour. Therefore, we offer this as an option. 871 872 You are recommended say 'Y' here and debug any affected drivers. 873 874config ARCH_HAS_BARRIERS 875 bool 876 help 877 This option allows the use of custom mandatory barriers 878 included via the mach/barriers.h file. 879