1 /* 2 * This file contains common code that is intended to be used across 3 * boards so that it's not replicated. 4 * 5 * Copyright (C) 2011 Xilinx 6 * 7 * This software is licensed under the terms of the GNU General Public 8 * License version 2, as published by the Free Software Foundation, and 9 * may be copied, distributed, and modified under those terms. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/init.h> 18 #include <linux/io.h> 19 #include <linux/kernel.h> 20 #include <linux/cpumask.h> 21 #include <linux/platform_device.h> 22 #include <linux/clk.h> 23 #include <linux/clk-provider.h> 24 #include <linux/clk/zynq.h> 25 #include <linux/clocksource.h> 26 #include <linux/of_address.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_platform.h> 29 #include <linux/of.h> 30 #include <linux/memblock.h> 31 #include <linux/irqchip.h> 32 #include <linux/irqchip/arm-gic.h> 33 #include <linux/slab.h> 34 #include <linux/sys_soc.h> 35 36 #include <asm/mach/arch.h> 37 #include <asm/mach/map.h> 38 #include <asm/mach/time.h> 39 #include <asm/mach-types.h> 40 #include <asm/page.h> 41 #include <asm/pgtable.h> 42 #include <asm/smp_scu.h> 43 #include <asm/system_info.h> 44 #include <asm/hardware/cache-l2x0.h> 45 46 #include "common.h" 47 48 #define ZYNQ_DEVCFG_MCTRL 0x80 49 #define ZYNQ_DEVCFG_PS_VERSION_SHIFT 28 50 #define ZYNQ_DEVCFG_PS_VERSION_MASK 0xF 51 52 void __iomem *zynq_scu_base; 53 54 /** 55 * zynq_memory_init - Initialize special memory 56 * 57 * We need to stop things allocating the low memory as DMA can't work in 58 * the 1st 512K of memory. 59 */ 60 static void __init zynq_memory_init(void) 61 { 62 if (!__pa(PAGE_OFFSET)) 63 memblock_reserve(__pa(PAGE_OFFSET), 0x80000); 64 } 65 66 static struct platform_device zynq_cpuidle_device = { 67 .name = "cpuidle-zynq", 68 }; 69 70 /** 71 * zynq_get_revision - Get Zynq silicon revision 72 * 73 * Return: Silicon version or -1 otherwise 74 */ 75 static int __init zynq_get_revision(void) 76 { 77 struct device_node *np; 78 void __iomem *zynq_devcfg_base; 79 u32 revision; 80 81 np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-devcfg-1.0"); 82 if (!np) { 83 pr_err("%s: no devcfg node found\n", __func__); 84 return -1; 85 } 86 87 zynq_devcfg_base = of_iomap(np, 0); 88 if (!zynq_devcfg_base) { 89 pr_err("%s: Unable to map I/O memory\n", __func__); 90 return -1; 91 } 92 93 revision = readl(zynq_devcfg_base + ZYNQ_DEVCFG_MCTRL); 94 revision >>= ZYNQ_DEVCFG_PS_VERSION_SHIFT; 95 revision &= ZYNQ_DEVCFG_PS_VERSION_MASK; 96 97 iounmap(zynq_devcfg_base); 98 99 return revision; 100 } 101 102 static void __init zynq_init_late(void) 103 { 104 zynq_core_pm_init(); 105 zynq_pm_late_init(); 106 } 107 108 /** 109 * zynq_init_machine - System specific initialization, intended to be 110 * called from board specific initialization. 111 */ 112 static void __init zynq_init_machine(void) 113 { 114 struct soc_device_attribute *soc_dev_attr; 115 struct soc_device *soc_dev; 116 struct device *parent = NULL; 117 118 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); 119 if (!soc_dev_attr) 120 goto out; 121 122 system_rev = zynq_get_revision(); 123 124 soc_dev_attr->family = kasprintf(GFP_KERNEL, "Xilinx Zynq"); 125 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "0x%x", system_rev); 126 soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "0x%x", 127 zynq_slcr_get_device_id()); 128 129 soc_dev = soc_device_register(soc_dev_attr); 130 if (IS_ERR(soc_dev)) { 131 kfree(soc_dev_attr->family); 132 kfree(soc_dev_attr->revision); 133 kfree(soc_dev_attr->soc_id); 134 kfree(soc_dev_attr); 135 goto out; 136 } 137 138 parent = soc_device_to_device(soc_dev); 139 140 out: 141 /* 142 * Finished with the static registrations now; fill in the missing 143 * devices 144 */ 145 of_platform_default_populate(NULL, NULL, parent); 146 147 platform_device_register(&zynq_cpuidle_device); 148 } 149 150 static void __init zynq_timer_init(void) 151 { 152 zynq_clock_init(); 153 of_clk_init(NULL); 154 timer_probe(); 155 } 156 157 static struct map_desc zynq_cortex_a9_scu_map __initdata = { 158 .length = SZ_256, 159 .type = MT_DEVICE, 160 }; 161 162 static void __init zynq_scu_map_io(void) 163 { 164 unsigned long base; 165 166 base = scu_a9_get_base(); 167 zynq_cortex_a9_scu_map.pfn = __phys_to_pfn(base); 168 /* Expected address is in vmalloc area that's why simple assign here */ 169 zynq_cortex_a9_scu_map.virtual = base; 170 iotable_init(&zynq_cortex_a9_scu_map, 1); 171 zynq_scu_base = (void __iomem *)base; 172 BUG_ON(!zynq_scu_base); 173 } 174 175 /** 176 * zynq_map_io - Create memory mappings needed for early I/O. 177 */ 178 static void __init zynq_map_io(void) 179 { 180 debug_ll_io_init(); 181 zynq_scu_map_io(); 182 } 183 184 static void __init zynq_irq_init(void) 185 { 186 zynq_early_slcr_init(); 187 irqchip_init(); 188 } 189 190 static const char * const zynq_dt_match[] = { 191 "xlnx,zynq-7000", 192 NULL 193 }; 194 195 DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform") 196 /* 64KB way size, 8-way associativity, parity disabled */ 197 .l2c_aux_val = 0x00400000, 198 .l2c_aux_mask = 0xffbfffff, 199 .smp = smp_ops(zynq_smp_ops), 200 .map_io = zynq_map_io, 201 .init_irq = zynq_irq_init, 202 .init_machine = zynq_init_machine, 203 .init_late = zynq_init_late, 204 .init_time = zynq_timer_init, 205 .dt_compat = zynq_dt_match, 206 .reserve = zynq_memory_init, 207 MACHINE_END 208