1 /* 2 * This file contains common code that is intended to be used across 3 * boards so that it's not replicated. 4 * 5 * Copyright (C) 2011 Xilinx 6 * 7 * This software is licensed under the terms of the GNU General Public 8 * License version 2, as published by the Free Software Foundation, and 9 * may be copied, distributed, and modified under those terms. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/init.h> 18 #include <linux/kernel.h> 19 #include <linux/cpumask.h> 20 #include <linux/platform_device.h> 21 #include <linux/clk.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_platform.h> 24 #include <linux/of.h> 25 26 #include <asm/mach/arch.h> 27 #include <asm/mach/map.h> 28 #include <asm/mach-types.h> 29 #include <asm/page.h> 30 #include <asm/hardware/gic.h> 31 #include <asm/hardware/cache-l2x0.h> 32 33 #include <mach/zynq_soc.h> 34 #include <mach/clkdev.h> 35 #include "common.h" 36 37 static struct of_device_id zynq_of_bus_ids[] __initdata = { 38 { .compatible = "simple-bus", }, 39 {} 40 }; 41 42 /** 43 * xilinx_init_machine() - System specific initialization, intended to be 44 * called from board specific initialization. 45 */ 46 static void __init xilinx_init_machine(void) 47 { 48 #ifdef CONFIG_CACHE_L2X0 49 /* 50 * 64KB way size, 8-way associativity, parity disabled 51 */ 52 l2x0_init(PL310_L2CC_BASE, 0x02060000, 0xF0F0FFFF); 53 #endif 54 55 of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL); 56 } 57 58 /** 59 * xilinx_irq_init() - Interrupt controller initialization for the GIC. 60 */ 61 static void __init xilinx_irq_init(void) 62 { 63 gic_init(0, 29, SCU_GIC_DIST_BASE, SCU_GIC_CPU_BASE); 64 } 65 66 /* The minimum devices needed to be mapped before the VM system is up and 67 * running include the GIC, UART and Timer Counter. 68 */ 69 70 static struct map_desc io_desc[] __initdata = { 71 { 72 .virtual = TTC0_VIRT, 73 .pfn = __phys_to_pfn(TTC0_PHYS), 74 .length = SZ_4K, 75 .type = MT_DEVICE, 76 }, { 77 .virtual = SCU_PERIPH_VIRT, 78 .pfn = __phys_to_pfn(SCU_PERIPH_PHYS), 79 .length = SZ_8K, 80 .type = MT_DEVICE, 81 }, { 82 .virtual = PL310_L2CC_VIRT, 83 .pfn = __phys_to_pfn(PL310_L2CC_PHYS), 84 .length = SZ_4K, 85 .type = MT_DEVICE, 86 }, 87 88 #ifdef CONFIG_DEBUG_LL 89 { 90 .virtual = UART0_VIRT, 91 .pfn = __phys_to_pfn(UART0_PHYS), 92 .length = SZ_4K, 93 .type = MT_DEVICE, 94 }, 95 #endif 96 97 }; 98 99 /** 100 * xilinx_map_io() - Create memory mappings needed for early I/O. 101 */ 102 static void __init xilinx_map_io(void) 103 { 104 iotable_init(io_desc, ARRAY_SIZE(io_desc)); 105 } 106 107 static const char *xilinx_dt_match[] = { 108 "xlnx,zynq-ep107", 109 NULL 110 }; 111 112 MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform") 113 .map_io = xilinx_map_io, 114 .init_irq = xilinx_irq_init, 115 .handle_irq = gic_handle_irq, 116 .init_machine = xilinx_init_machine, 117 .timer = &xttcpss_sys_timer, 118 .dt_compat = xilinx_dt_match, 119 MACHINE_END 120