11e22a8c6SLinus Walleij /* 21e22a8c6SLinus Walleij * Copyright (C) ST-Ericsson SA 2010-2013 31e22a8c6SLinus Walleij * Author: Rickard Andersson <rickard.andersson@stericsson.com> for 41e22a8c6SLinus Walleij * ST-Ericsson. 51e22a8c6SLinus Walleij * Author: Daniel Lezcano <daniel.lezcano@linaro.org> for Linaro. 6ead9e293SUlf Hansson * Author: Ulf Hansson <ulf.hansson@linaro.org> for Linaro. 7ead9e293SUlf Hansson * 81e22a8c6SLinus Walleij * License terms: GNU General Public License (GPL) version 2 91e22a8c6SLinus Walleij * 101e22a8c6SLinus Walleij */ 111e22a8c6SLinus Walleij 121e22a8c6SLinus Walleij #include <linux/kernel.h> 131e22a8c6SLinus Walleij #include <linux/irqchip/arm-gic.h> 141e22a8c6SLinus Walleij #include <linux/delay.h> 151e22a8c6SLinus Walleij #include <linux/io.h> 16ead9e293SUlf Hansson #include <linux/suspend.h> 171e22a8c6SLinus Walleij #include <linux/platform_data/arm-ux500-pm.h> 1826ef94dcSLinus Walleij #include <linux/of.h> 1926ef94dcSLinus Walleij #include <linux/of_address.h> 201e22a8c6SLinus Walleij 21174e7796SLinus Walleij #include "db8500-regs.h" 22cd931dcfSUlf Hansson #include "pm_domains.h" 231e22a8c6SLinus Walleij 241e22a8c6SLinus Walleij /* ARM WFI Standby signal register */ 251e22a8c6SLinus Walleij #define PRCM_ARM_WFI_STANDBY (prcmu_base + 0x130) 261e22a8c6SLinus Walleij #define PRCM_ARM_WFI_STANDBY_WFI0 0x08 271e22a8c6SLinus Walleij #define PRCM_ARM_WFI_STANDBY_WFI1 0x10 281e22a8c6SLinus Walleij #define PRCM_IOCR (prcmu_base + 0x310) 291e22a8c6SLinus Walleij #define PRCM_IOCR_IOFORCE 0x1 301e22a8c6SLinus Walleij 311e22a8c6SLinus Walleij /* Dual A9 core interrupt management unit registers */ 321e22a8c6SLinus Walleij #define PRCM_A9_MASK_REQ (prcmu_base + 0x328) 331e22a8c6SLinus Walleij #define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ 0x1 341e22a8c6SLinus Walleij 351e22a8c6SLinus Walleij #define PRCM_A9_MASK_ACK (prcmu_base + 0x32c) 361e22a8c6SLinus Walleij #define PRCM_ARMITMSK31TO0 (prcmu_base + 0x11c) 371e22a8c6SLinus Walleij #define PRCM_ARMITMSK63TO32 (prcmu_base + 0x120) 381e22a8c6SLinus Walleij #define PRCM_ARMITMSK95TO64 (prcmu_base + 0x124) 391e22a8c6SLinus Walleij #define PRCM_ARMITMSK127TO96 (prcmu_base + 0x128) 401e22a8c6SLinus Walleij #define PRCM_POWER_STATE_VAL (prcmu_base + 0x25C) 411e22a8c6SLinus Walleij #define PRCM_ARMITVAL31TO0 (prcmu_base + 0x260) 421e22a8c6SLinus Walleij #define PRCM_ARMITVAL63TO32 (prcmu_base + 0x264) 431e22a8c6SLinus Walleij #define PRCM_ARMITVAL95TO64 (prcmu_base + 0x268) 441e22a8c6SLinus Walleij #define PRCM_ARMITVAL127TO96 (prcmu_base + 0x26C) 451e22a8c6SLinus Walleij 461e22a8c6SLinus Walleij static void __iomem *prcmu_base; 4726ef94dcSLinus Walleij static void __iomem *dist_base; 481e22a8c6SLinus Walleij 491e22a8c6SLinus Walleij /* This function decouple the gic from the prcmu */ 501e22a8c6SLinus Walleij int prcmu_gic_decouple(void) 511e22a8c6SLinus Walleij { 521e22a8c6SLinus Walleij u32 val = readl(PRCM_A9_MASK_REQ); 531e22a8c6SLinus Walleij 541e22a8c6SLinus Walleij /* Set bit 0 register value to 1 */ 551e22a8c6SLinus Walleij writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, 561e22a8c6SLinus Walleij PRCM_A9_MASK_REQ); 571e22a8c6SLinus Walleij 581e22a8c6SLinus Walleij /* Make sure the register is updated */ 591e22a8c6SLinus Walleij readl(PRCM_A9_MASK_REQ); 601e22a8c6SLinus Walleij 611e22a8c6SLinus Walleij /* Wait a few cycles for the gic mask completion */ 621e22a8c6SLinus Walleij udelay(1); 631e22a8c6SLinus Walleij 641e22a8c6SLinus Walleij return 0; 651e22a8c6SLinus Walleij } 661e22a8c6SLinus Walleij 671e22a8c6SLinus Walleij /* This function recouple the gic with the prcmu */ 681e22a8c6SLinus Walleij int prcmu_gic_recouple(void) 691e22a8c6SLinus Walleij { 701e22a8c6SLinus Walleij u32 val = readl(PRCM_A9_MASK_REQ); 711e22a8c6SLinus Walleij 721e22a8c6SLinus Walleij /* Set bit 0 register value to 0 */ 731e22a8c6SLinus Walleij writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ); 741e22a8c6SLinus Walleij 751e22a8c6SLinus Walleij return 0; 761e22a8c6SLinus Walleij } 771e22a8c6SLinus Walleij 781e22a8c6SLinus Walleij #define PRCMU_GIC_NUMBER_REGS 5 791e22a8c6SLinus Walleij 801e22a8c6SLinus Walleij /* 811e22a8c6SLinus Walleij * This function checks if there are pending irq on the gic. It only 821e22a8c6SLinus Walleij * makes sense if the gic has been decoupled before with the 831e22a8c6SLinus Walleij * db8500_prcmu_gic_decouple function. Disabling an interrupt only 841e22a8c6SLinus Walleij * disables the forwarding of the interrupt to any CPU interface. It 851e22a8c6SLinus Walleij * does not prevent the interrupt from changing state, for example 861e22a8c6SLinus Walleij * becoming pending, or active and pending if it is already 871e22a8c6SLinus Walleij * active. Hence, we have to check the interrupt is pending *and* is 881e22a8c6SLinus Walleij * active. 891e22a8c6SLinus Walleij */ 901e22a8c6SLinus Walleij bool prcmu_gic_pending_irq(void) 911e22a8c6SLinus Walleij { 921e22a8c6SLinus Walleij u32 pr; /* Pending register */ 931e22a8c6SLinus Walleij u32 er; /* Enable register */ 941e22a8c6SLinus Walleij int i; 951e22a8c6SLinus Walleij 961e22a8c6SLinus Walleij /* 5 registers. STI & PPI not skipped */ 971e22a8c6SLinus Walleij for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) { 981e22a8c6SLinus Walleij 991e22a8c6SLinus Walleij pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4); 1001e22a8c6SLinus Walleij er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 1011e22a8c6SLinus Walleij 1021e22a8c6SLinus Walleij if (pr & er) 1031e22a8c6SLinus Walleij return true; /* There is a pending interrupt */ 1041e22a8c6SLinus Walleij } 1051e22a8c6SLinus Walleij 1061e22a8c6SLinus Walleij return false; 1071e22a8c6SLinus Walleij } 1081e22a8c6SLinus Walleij 1091e22a8c6SLinus Walleij /* 1101e22a8c6SLinus Walleij * This function checks if there are pending interrupt on the 1111e22a8c6SLinus Walleij * prcmu which has been delegated to monitor the irqs with the 1121e22a8c6SLinus Walleij * db8500_prcmu_copy_gic_settings function. 1131e22a8c6SLinus Walleij */ 1141e22a8c6SLinus Walleij bool prcmu_pending_irq(void) 1151e22a8c6SLinus Walleij { 1161e22a8c6SLinus Walleij u32 it, im; 1171e22a8c6SLinus Walleij int i; 1181e22a8c6SLinus Walleij 1191e22a8c6SLinus Walleij for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { 1201e22a8c6SLinus Walleij it = readl(PRCM_ARMITVAL31TO0 + i * 4); 1211e22a8c6SLinus Walleij im = readl(PRCM_ARMITMSK31TO0 + i * 4); 1221e22a8c6SLinus Walleij if (it & im) 1231e22a8c6SLinus Walleij return true; /* There is a pending interrupt */ 1241e22a8c6SLinus Walleij } 1251e22a8c6SLinus Walleij 1261e22a8c6SLinus Walleij return false; 1271e22a8c6SLinus Walleij } 1281e22a8c6SLinus Walleij 1291e22a8c6SLinus Walleij /* 1301e22a8c6SLinus Walleij * This function checks if the specified cpu is in in WFI. It's usage 1311e22a8c6SLinus Walleij * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple 1321e22a8c6SLinus Walleij * function. Of course passing smp_processor_id() to this function will 1331e22a8c6SLinus Walleij * always return false... 1341e22a8c6SLinus Walleij */ 1351e22a8c6SLinus Walleij bool prcmu_is_cpu_in_wfi(int cpu) 1361e22a8c6SLinus Walleij { 1371e22a8c6SLinus Walleij return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 : 1381e22a8c6SLinus Walleij PRCM_ARM_WFI_STANDBY_WFI0; 1391e22a8c6SLinus Walleij } 1401e22a8c6SLinus Walleij 1411e22a8c6SLinus Walleij /* 1421e22a8c6SLinus Walleij * This function copies the gic SPI settings to the prcmu in order to 1431e22a8c6SLinus Walleij * monitor them and abort/finish the retention/off sequence or state. 1441e22a8c6SLinus Walleij */ 1451e22a8c6SLinus Walleij int prcmu_copy_gic_settings(void) 1461e22a8c6SLinus Walleij { 1471e22a8c6SLinus Walleij u32 er; /* Enable register */ 1481e22a8c6SLinus Walleij int i; 1491e22a8c6SLinus Walleij 1501e22a8c6SLinus Walleij /* We skip the STI and PPI */ 1511e22a8c6SLinus Walleij for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { 1521e22a8c6SLinus Walleij er = readl_relaxed(dist_base + 1531e22a8c6SLinus Walleij GIC_DIST_ENABLE_SET + (i + 1) * 4); 1541e22a8c6SLinus Walleij writel(er, PRCM_ARMITMSK31TO0 + i * 4); 1551e22a8c6SLinus Walleij } 1561e22a8c6SLinus Walleij 1571e22a8c6SLinus Walleij return 0; 1581e22a8c6SLinus Walleij } 1591e22a8c6SLinus Walleij 160ead9e293SUlf Hansson #ifdef CONFIG_SUSPEND 161ead9e293SUlf Hansson static int ux500_suspend_enter(suspend_state_t state) 162ead9e293SUlf Hansson { 163ead9e293SUlf Hansson cpu_do_idle(); 164ead9e293SUlf Hansson return 0; 165ead9e293SUlf Hansson } 166ead9e293SUlf Hansson 167ead9e293SUlf Hansson static int ux500_suspend_valid(suspend_state_t state) 168ead9e293SUlf Hansson { 169ead9e293SUlf Hansson return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 170ead9e293SUlf Hansson } 171ead9e293SUlf Hansson 172ead9e293SUlf Hansson static const struct platform_suspend_ops ux500_suspend_ops = { 173ead9e293SUlf Hansson .enter = ux500_suspend_enter, 174ead9e293SUlf Hansson .valid = ux500_suspend_valid, 175ead9e293SUlf Hansson }; 176ead9e293SUlf Hansson #define UX500_SUSPEND_OPS (&ux500_suspend_ops) 177ead9e293SUlf Hansson #else 178ead9e293SUlf Hansson #define UX500_SUSPEND_OPS NULL 179ead9e293SUlf Hansson #endif 180ead9e293SUlf Hansson 1811e22a8c6SLinus Walleij void __init ux500_pm_init(u32 phy_base, u32 size) 1821e22a8c6SLinus Walleij { 18326ef94dcSLinus Walleij struct device_node *np; 18426ef94dcSLinus Walleij 1851e22a8c6SLinus Walleij prcmu_base = ioremap(phy_base, size); 1861e22a8c6SLinus Walleij if (!prcmu_base) { 1871e22a8c6SLinus Walleij pr_err("could not remap PRCMU for PM functions\n"); 1881e22a8c6SLinus Walleij return; 1891e22a8c6SLinus Walleij } 19026ef94dcSLinus Walleij np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic"); 19126ef94dcSLinus Walleij dist_base = of_iomap(np, 0); 19226ef94dcSLinus Walleij of_node_put(np); 19326ef94dcSLinus Walleij if (!dist_base) { 19426ef94dcSLinus Walleij pr_err("could not remap GIC dist base for PM functions\n"); 19526ef94dcSLinus Walleij return; 19626ef94dcSLinus Walleij } 19726ef94dcSLinus Walleij 1981e22a8c6SLinus Walleij /* 1991e22a8c6SLinus Walleij * On watchdog reboot the GIC is in some cases decoupled. 2001e22a8c6SLinus Walleij * This will make sure that the GIC is correctly configured. 2011e22a8c6SLinus Walleij */ 2021e22a8c6SLinus Walleij prcmu_gic_recouple(); 203ead9e293SUlf Hansson 204ead9e293SUlf Hansson /* Set up ux500 suspend callbacks. */ 205ead9e293SUlf Hansson suspend_set_ops(UX500_SUSPEND_OPS); 206cd931dcfSUlf Hansson 207cd931dcfSUlf Hansson /* Initialize ux500 power domains */ 208cd931dcfSUlf Hansson ux500_pm_domains_init(); 2091e22a8c6SLinus Walleij } 210