11e22a8c6SLinus Walleij /* 21e22a8c6SLinus Walleij * Copyright (C) ST-Ericsson SA 2010-2013 31e22a8c6SLinus Walleij * Author: Rickard Andersson <rickard.andersson@stericsson.com> for 41e22a8c6SLinus Walleij * ST-Ericsson. 51e22a8c6SLinus Walleij * Author: Daniel Lezcano <daniel.lezcano@linaro.org> for Linaro. 61e22a8c6SLinus Walleij * License terms: GNU General Public License (GPL) version 2 71e22a8c6SLinus Walleij * 81e22a8c6SLinus Walleij */ 91e22a8c6SLinus Walleij 101e22a8c6SLinus Walleij #include <linux/kernel.h> 111e22a8c6SLinus Walleij #include <linux/irqchip/arm-gic.h> 121e22a8c6SLinus Walleij #include <linux/delay.h> 131e22a8c6SLinus Walleij #include <linux/io.h> 141e22a8c6SLinus Walleij #include <linux/platform_data/arm-ux500-pm.h> 151e22a8c6SLinus Walleij 161e22a8c6SLinus Walleij #include <mach/hardware.h> 171e22a8c6SLinus Walleij 181e22a8c6SLinus Walleij /* ARM WFI Standby signal register */ 191e22a8c6SLinus Walleij #define PRCM_ARM_WFI_STANDBY (prcmu_base + 0x130) 201e22a8c6SLinus Walleij #define PRCM_ARM_WFI_STANDBY_WFI0 0x08 211e22a8c6SLinus Walleij #define PRCM_ARM_WFI_STANDBY_WFI1 0x10 221e22a8c6SLinus Walleij #define PRCM_IOCR (prcmu_base + 0x310) 231e22a8c6SLinus Walleij #define PRCM_IOCR_IOFORCE 0x1 241e22a8c6SLinus Walleij 251e22a8c6SLinus Walleij /* Dual A9 core interrupt management unit registers */ 261e22a8c6SLinus Walleij #define PRCM_A9_MASK_REQ (prcmu_base + 0x328) 271e22a8c6SLinus Walleij #define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ 0x1 281e22a8c6SLinus Walleij 291e22a8c6SLinus Walleij #define PRCM_A9_MASK_ACK (prcmu_base + 0x32c) 301e22a8c6SLinus Walleij #define PRCM_ARMITMSK31TO0 (prcmu_base + 0x11c) 311e22a8c6SLinus Walleij #define PRCM_ARMITMSK63TO32 (prcmu_base + 0x120) 321e22a8c6SLinus Walleij #define PRCM_ARMITMSK95TO64 (prcmu_base + 0x124) 331e22a8c6SLinus Walleij #define PRCM_ARMITMSK127TO96 (prcmu_base + 0x128) 341e22a8c6SLinus Walleij #define PRCM_POWER_STATE_VAL (prcmu_base + 0x25C) 351e22a8c6SLinus Walleij #define PRCM_ARMITVAL31TO0 (prcmu_base + 0x260) 361e22a8c6SLinus Walleij #define PRCM_ARMITVAL63TO32 (prcmu_base + 0x264) 371e22a8c6SLinus Walleij #define PRCM_ARMITVAL95TO64 (prcmu_base + 0x268) 381e22a8c6SLinus Walleij #define PRCM_ARMITVAL127TO96 (prcmu_base + 0x26C) 391e22a8c6SLinus Walleij 401e22a8c6SLinus Walleij static void __iomem *prcmu_base; 411e22a8c6SLinus Walleij 421e22a8c6SLinus Walleij /* This function decouple the gic from the prcmu */ 431e22a8c6SLinus Walleij int prcmu_gic_decouple(void) 441e22a8c6SLinus Walleij { 451e22a8c6SLinus Walleij u32 val = readl(PRCM_A9_MASK_REQ); 461e22a8c6SLinus Walleij 471e22a8c6SLinus Walleij /* Set bit 0 register value to 1 */ 481e22a8c6SLinus Walleij writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, 491e22a8c6SLinus Walleij PRCM_A9_MASK_REQ); 501e22a8c6SLinus Walleij 511e22a8c6SLinus Walleij /* Make sure the register is updated */ 521e22a8c6SLinus Walleij readl(PRCM_A9_MASK_REQ); 531e22a8c6SLinus Walleij 541e22a8c6SLinus Walleij /* Wait a few cycles for the gic mask completion */ 551e22a8c6SLinus Walleij udelay(1); 561e22a8c6SLinus Walleij 571e22a8c6SLinus Walleij return 0; 581e22a8c6SLinus Walleij } 591e22a8c6SLinus Walleij 601e22a8c6SLinus Walleij /* This function recouple the gic with the prcmu */ 611e22a8c6SLinus Walleij int prcmu_gic_recouple(void) 621e22a8c6SLinus Walleij { 631e22a8c6SLinus Walleij u32 val = readl(PRCM_A9_MASK_REQ); 641e22a8c6SLinus Walleij 651e22a8c6SLinus Walleij /* Set bit 0 register value to 0 */ 661e22a8c6SLinus Walleij writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ); 671e22a8c6SLinus Walleij 681e22a8c6SLinus Walleij return 0; 691e22a8c6SLinus Walleij } 701e22a8c6SLinus Walleij 711e22a8c6SLinus Walleij #define PRCMU_GIC_NUMBER_REGS 5 721e22a8c6SLinus Walleij 731e22a8c6SLinus Walleij /* 741e22a8c6SLinus Walleij * This function checks if there are pending irq on the gic. It only 751e22a8c6SLinus Walleij * makes sense if the gic has been decoupled before with the 761e22a8c6SLinus Walleij * db8500_prcmu_gic_decouple function. Disabling an interrupt only 771e22a8c6SLinus Walleij * disables the forwarding of the interrupt to any CPU interface. It 781e22a8c6SLinus Walleij * does not prevent the interrupt from changing state, for example 791e22a8c6SLinus Walleij * becoming pending, or active and pending if it is already 801e22a8c6SLinus Walleij * active. Hence, we have to check the interrupt is pending *and* is 811e22a8c6SLinus Walleij * active. 821e22a8c6SLinus Walleij */ 831e22a8c6SLinus Walleij bool prcmu_gic_pending_irq(void) 841e22a8c6SLinus Walleij { 851e22a8c6SLinus Walleij u32 pr; /* Pending register */ 861e22a8c6SLinus Walleij u32 er; /* Enable register */ 871e22a8c6SLinus Walleij void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE); 881e22a8c6SLinus Walleij int i; 891e22a8c6SLinus Walleij 901e22a8c6SLinus Walleij /* 5 registers. STI & PPI not skipped */ 911e22a8c6SLinus Walleij for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) { 921e22a8c6SLinus Walleij 931e22a8c6SLinus Walleij pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4); 941e22a8c6SLinus Walleij er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 951e22a8c6SLinus Walleij 961e22a8c6SLinus Walleij if (pr & er) 971e22a8c6SLinus Walleij return true; /* There is a pending interrupt */ 981e22a8c6SLinus Walleij } 991e22a8c6SLinus Walleij 1001e22a8c6SLinus Walleij return false; 1011e22a8c6SLinus Walleij } 1021e22a8c6SLinus Walleij 1031e22a8c6SLinus Walleij /* 1041e22a8c6SLinus Walleij * This function checks if there are pending interrupt on the 1051e22a8c6SLinus Walleij * prcmu which has been delegated to monitor the irqs with the 1061e22a8c6SLinus Walleij * db8500_prcmu_copy_gic_settings function. 1071e22a8c6SLinus Walleij */ 1081e22a8c6SLinus Walleij bool prcmu_pending_irq(void) 1091e22a8c6SLinus Walleij { 1101e22a8c6SLinus Walleij u32 it, im; 1111e22a8c6SLinus Walleij int i; 1121e22a8c6SLinus Walleij 1131e22a8c6SLinus Walleij for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { 1141e22a8c6SLinus Walleij it = readl(PRCM_ARMITVAL31TO0 + i * 4); 1151e22a8c6SLinus Walleij im = readl(PRCM_ARMITMSK31TO0 + i * 4); 1161e22a8c6SLinus Walleij if (it & im) 1171e22a8c6SLinus Walleij return true; /* There is a pending interrupt */ 1181e22a8c6SLinus Walleij } 1191e22a8c6SLinus Walleij 1201e22a8c6SLinus Walleij return false; 1211e22a8c6SLinus Walleij } 1221e22a8c6SLinus Walleij 1231e22a8c6SLinus Walleij /* 1241e22a8c6SLinus Walleij * This function checks if the specified cpu is in in WFI. It's usage 1251e22a8c6SLinus Walleij * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple 1261e22a8c6SLinus Walleij * function. Of course passing smp_processor_id() to this function will 1271e22a8c6SLinus Walleij * always return false... 1281e22a8c6SLinus Walleij */ 1291e22a8c6SLinus Walleij bool prcmu_is_cpu_in_wfi(int cpu) 1301e22a8c6SLinus Walleij { 1311e22a8c6SLinus Walleij return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 : 1321e22a8c6SLinus Walleij PRCM_ARM_WFI_STANDBY_WFI0; 1331e22a8c6SLinus Walleij } 1341e22a8c6SLinus Walleij 1351e22a8c6SLinus Walleij /* 1361e22a8c6SLinus Walleij * This function copies the gic SPI settings to the prcmu in order to 1371e22a8c6SLinus Walleij * monitor them and abort/finish the retention/off sequence or state. 1381e22a8c6SLinus Walleij */ 1391e22a8c6SLinus Walleij int prcmu_copy_gic_settings(void) 1401e22a8c6SLinus Walleij { 1411e22a8c6SLinus Walleij u32 er; /* Enable register */ 1421e22a8c6SLinus Walleij void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE); 1431e22a8c6SLinus Walleij int i; 1441e22a8c6SLinus Walleij 1451e22a8c6SLinus Walleij /* We skip the STI and PPI */ 1461e22a8c6SLinus Walleij for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { 1471e22a8c6SLinus Walleij er = readl_relaxed(dist_base + 1481e22a8c6SLinus Walleij GIC_DIST_ENABLE_SET + (i + 1) * 4); 1491e22a8c6SLinus Walleij writel(er, PRCM_ARMITMSK31TO0 + i * 4); 1501e22a8c6SLinus Walleij } 1511e22a8c6SLinus Walleij 1521e22a8c6SLinus Walleij return 0; 1531e22a8c6SLinus Walleij } 1541e22a8c6SLinus Walleij 1551e22a8c6SLinus Walleij void __init ux500_pm_init(u32 phy_base, u32 size) 1561e22a8c6SLinus Walleij { 1571e22a8c6SLinus Walleij prcmu_base = ioremap(phy_base, size); 1581e22a8c6SLinus Walleij if (!prcmu_base) { 1591e22a8c6SLinus Walleij pr_err("could not remap PRCMU for PM functions\n"); 1601e22a8c6SLinus Walleij return; 1611e22a8c6SLinus Walleij } 1621e22a8c6SLinus Walleij /* 1631e22a8c6SLinus Walleij * On watchdog reboot the GIC is in some cases decoupled. 1641e22a8c6SLinus Walleij * This will make sure that the GIC is correctly configured. 1651e22a8c6SLinus Walleij */ 1661e22a8c6SLinus Walleij prcmu_gic_recouple(); 1671e22a8c6SLinus Walleij } 168