1 /* 2 * Copyright (C) 2002 ARM Ltd. 3 * Copyright (C) 2008 STMicroelctronics. 4 * Copyright (C) 2009 ST-Ericsson. 5 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> 6 * 7 * This file is based on arm realview platform 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 #include <linux/init.h> 14 #include <linux/errno.h> 15 #include <linux/delay.h> 16 #include <linux/device.h> 17 #include <linux/smp.h> 18 #include <linux/io.h> 19 20 #include <asm/cacheflush.h> 21 #include <asm/smp_plat.h> 22 #include <asm/smp_scu.h> 23 24 #include "setup.h" 25 26 #include "db8500-regs.h" 27 #include "id.h" 28 29 /* This is called from headsmp.S to wakeup the secondary core */ 30 extern void u8500_secondary_startup(void); 31 32 /* 33 * Write pen_release in a way that is guaranteed to be visible to all 34 * observers, irrespective of whether they're taking part in coherency 35 * or not. This is necessary for the hotplug code to work reliably. 36 */ 37 static void write_pen_release(int val) 38 { 39 pen_release = val; 40 smp_wmb(); 41 sync_cache_w(&pen_release); 42 } 43 44 static void __iomem *scu_base_addr(void) 45 { 46 if (cpu_is_u8500_family() || cpu_is_ux540_family()) 47 return __io_address(U8500_SCU_BASE); 48 else 49 ux500_unknown_soc(); 50 51 return NULL; 52 } 53 54 static DEFINE_SPINLOCK(boot_lock); 55 56 static void ux500_secondary_init(unsigned int cpu) 57 { 58 /* 59 * let the primary processor know we're out of the 60 * pen, then head off into the C entry point 61 */ 62 write_pen_release(-1); 63 64 /* 65 * Synchronise with the boot thread. 66 */ 67 spin_lock(&boot_lock); 68 spin_unlock(&boot_lock); 69 } 70 71 static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle) 72 { 73 unsigned long timeout; 74 75 /* 76 * set synchronisation state between this boot processor 77 * and the secondary one 78 */ 79 spin_lock(&boot_lock); 80 81 /* 82 * The secondary processor is waiting to be released from 83 * the holding pen - release it, then wait for it to flag 84 * that it has been released by resetting pen_release. 85 */ 86 write_pen_release(cpu_logical_map(cpu)); 87 88 arch_send_wakeup_ipi_mask(cpumask_of(cpu)); 89 90 timeout = jiffies + (1 * HZ); 91 while (time_before(jiffies, timeout)) { 92 if (pen_release == -1) 93 break; 94 } 95 96 /* 97 * now the secondary core is starting up let it run its 98 * calibrations, then wait for it to finish 99 */ 100 spin_unlock(&boot_lock); 101 102 return pen_release != -1 ? -ENOSYS : 0; 103 } 104 105 static void __init wakeup_secondary(void) 106 { 107 void __iomem *backupram; 108 109 if (cpu_is_u8500_family() || cpu_is_ux540_family()) 110 backupram = __io_address(U8500_BACKUPRAM0_BASE); 111 else 112 ux500_unknown_soc(); 113 114 /* 115 * write the address of secondary startup into the backup ram register 116 * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the 117 * backup ram register at offset 0x1FF0, which is what boot rom code 118 * is waiting for. This would wake up the secondary core from WFE 119 */ 120 #define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4 121 __raw_writel(virt_to_phys(u8500_secondary_startup), 122 backupram + UX500_CPU1_JUMPADDR_OFFSET); 123 124 #define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0 125 __raw_writel(0xA1FEED01, 126 backupram + UX500_CPU1_WAKEMAGIC_OFFSET); 127 128 /* make sure write buffer is drained */ 129 mb(); 130 } 131 132 /* 133 * Initialise the CPU possible map early - this describes the CPUs 134 * which may be present or become present in the system. 135 */ 136 static void __init ux500_smp_init_cpus(void) 137 { 138 void __iomem *scu_base = scu_base_addr(); 139 unsigned int i, ncores; 140 141 ncores = scu_base ? scu_get_core_count(scu_base) : 1; 142 143 /* sanity check */ 144 if (ncores > nr_cpu_ids) { 145 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", 146 ncores, nr_cpu_ids); 147 ncores = nr_cpu_ids; 148 } 149 150 for (i = 0; i < ncores; i++) 151 set_cpu_possible(i, true); 152 } 153 154 static void __init ux500_smp_prepare_cpus(unsigned int max_cpus) 155 { 156 157 scu_enable(scu_base_addr()); 158 wakeup_secondary(); 159 } 160 161 struct smp_operations ux500_smp_ops __initdata = { 162 .smp_init_cpus = ux500_smp_init_cpus, 163 .smp_prepare_cpus = ux500_smp_prepare_cpus, 164 .smp_secondary_init = ux500_secondary_init, 165 .smp_boot_secondary = ux500_boot_secondary, 166 #ifdef CONFIG_HOTPLUG_CPU 167 .cpu_die = ux500_cpu_die, 168 #endif 169 }; 170