1 /* 2 * Copyright (C) 2002 ARM Ltd. 3 * Copyright (C) 2008 STMicroelctronics. 4 * Copyright (C) 2009 ST-Ericsson. 5 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> 6 * 7 * This file is based on arm realview platform 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 #include <linux/init.h> 14 #include <linux/errno.h> 15 #include <linux/delay.h> 16 #include <linux/device.h> 17 #include <linux/smp.h> 18 #include <linux/io.h> 19 20 #include <asm/cacheflush.h> 21 #include <asm/hardware/gic.h> 22 #include <asm/smp_plat.h> 23 #include <asm/smp_scu.h> 24 #include <mach/hardware.h> 25 #include <mach/setup.h> 26 27 /* This is called from headsmp.S to wakeup the secondary core */ 28 extern void u8500_secondary_startup(void); 29 30 /* 31 * Write pen_release in a way that is guaranteed to be visible to all 32 * observers, irrespective of whether they're taking part in coherency 33 * or not. This is necessary for the hotplug code to work reliably. 34 */ 35 static void write_pen_release(int val) 36 { 37 pen_release = val; 38 smp_wmb(); 39 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); 40 outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); 41 } 42 43 static void __iomem *scu_base_addr(void) 44 { 45 if (cpu_is_u8500_family()) 46 return __io_address(U8500_SCU_BASE); 47 else 48 ux500_unknown_soc(); 49 50 return NULL; 51 } 52 53 static DEFINE_SPINLOCK(boot_lock); 54 55 static void __cpuinit ux500_secondary_init(unsigned int cpu) 56 { 57 /* 58 * if any interrupts are already enabled for the primary 59 * core (e.g. timer irq), then they will not have been enabled 60 * for us: do so 61 */ 62 gic_secondary_init(0); 63 64 /* 65 * let the primary processor know we're out of the 66 * pen, then head off into the C entry point 67 */ 68 write_pen_release(-1); 69 70 /* 71 * Synchronise with the boot thread. 72 */ 73 spin_lock(&boot_lock); 74 spin_unlock(&boot_lock); 75 } 76 77 static int __cpuinit ux500_boot_secondary(unsigned int cpu, struct task_struct *idle) 78 { 79 unsigned long timeout; 80 81 /* 82 * set synchronisation state between this boot processor 83 * and the secondary one 84 */ 85 spin_lock(&boot_lock); 86 87 /* 88 * The secondary processor is waiting to be released from 89 * the holding pen - release it, then wait for it to flag 90 * that it has been released by resetting pen_release. 91 */ 92 write_pen_release(cpu_logical_map(cpu)); 93 94 smp_send_reschedule(cpu); 95 96 timeout = jiffies + (1 * HZ); 97 while (time_before(jiffies, timeout)) { 98 if (pen_release == -1) 99 break; 100 } 101 102 /* 103 * now the secondary core is starting up let it run its 104 * calibrations, then wait for it to finish 105 */ 106 spin_unlock(&boot_lock); 107 108 return pen_release != -1 ? -ENOSYS : 0; 109 } 110 111 static void __init wakeup_secondary(void) 112 { 113 void __iomem *backupram; 114 115 if (cpu_is_u8500_family()) 116 backupram = __io_address(U8500_BACKUPRAM0_BASE); 117 else 118 ux500_unknown_soc(); 119 120 /* 121 * write the address of secondary startup into the backup ram register 122 * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the 123 * backup ram register at offset 0x1FF0, which is what boot rom code 124 * is waiting for. This would wake up the secondary core from WFE 125 */ 126 #define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4 127 __raw_writel(virt_to_phys(u8500_secondary_startup), 128 backupram + UX500_CPU1_JUMPADDR_OFFSET); 129 130 #define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0 131 __raw_writel(0xA1FEED01, 132 backupram + UX500_CPU1_WAKEMAGIC_OFFSET); 133 134 /* make sure write buffer is drained */ 135 mb(); 136 } 137 138 /* 139 * Initialise the CPU possible map early - this describes the CPUs 140 * which may be present or become present in the system. 141 */ 142 static void __init ux500_smp_init_cpus(void) 143 { 144 void __iomem *scu_base = scu_base_addr(); 145 unsigned int i, ncores; 146 147 ncores = scu_base ? scu_get_core_count(scu_base) : 1; 148 149 /* sanity check */ 150 if (ncores > nr_cpu_ids) { 151 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", 152 ncores, nr_cpu_ids); 153 ncores = nr_cpu_ids; 154 } 155 156 for (i = 0; i < ncores; i++) 157 set_cpu_possible(i, true); 158 159 set_smp_cross_call(gic_raise_softirq); 160 } 161 162 static void __init ux500_smp_prepare_cpus(unsigned int max_cpus) 163 { 164 165 scu_enable(scu_base_addr()); 166 wakeup_secondary(); 167 } 168 169 struct smp_operations ux500_smp_ops __initdata = { 170 .smp_init_cpus = ux500_smp_init_cpus, 171 .smp_prepare_cpus = ux500_smp_prepare_cpus, 172 .smp_secondary_init = ux500_secondary_init, 173 .smp_boot_secondary = ux500_boot_secondary, 174 #ifdef CONFIG_HOTPLUG_CPU 175 .cpu_die = ux500_cpu_die, 176 #endif 177 }; 178