1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2008-2009 ST-Ericsson SA 4 * 5 * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com> 6 */ 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/device.h> 10 #include <linux/amba/bus.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/irqchip.h> 14 #include <linux/irqchip/arm-gic.h> 15 #include <linux/mfd/dbx500-prcmu.h> 16 #include <linux/platform_data/arm-ux500-pm.h> 17 #include <linux/platform_device.h> 18 #include <linux/io.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/of_platform.h> 22 #include <linux/regulator/machine.h> 23 24 #include <asm/outercache.h> 25 #include <asm/hardware/cache-l2x0.h> 26 #include <asm/mach/map.h> 27 #include <asm/mach/arch.h> 28 29 #include "db8500-regs.h" 30 #include "pm_domains.h" 31 32 static int __init ux500_l2x0_unlock(void) 33 { 34 int i; 35 struct device_node *np; 36 void __iomem *l2x0_base; 37 38 np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); 39 l2x0_base = of_iomap(np, 0); 40 of_node_put(np); 41 if (!l2x0_base) 42 return -ENODEV; 43 44 /* 45 * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions 46 * apparently locks both caches before jumping to the kernel. The 47 * l2x0 core will not touch the unlock registers if the l2x0 is 48 * already enabled, so we do it right here instead. The PL310 has 49 * 8 sets of registers, one per possible CPU. 50 */ 51 for (i = 0; i < 8; i++) { 52 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE + 53 i * L2X0_LOCKDOWN_STRIDE); 54 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE + 55 i * L2X0_LOCKDOWN_STRIDE); 56 } 57 iounmap(l2x0_base); 58 return 0; 59 } 60 61 static void ux500_l2c310_write_sec(unsigned long val, unsigned reg) 62 { 63 /* 64 * We can't write to secure registers as we are in non-secure 65 * mode, until we have some SMI service available. 66 */ 67 } 68 69 /* 70 * FIXME: Should we set up the GPIO domain here? 71 * 72 * The problem is that we cannot put the interrupt resources into the platform 73 * device until the irqdomain has been added. Right now, we set the GIC interrupt 74 * domain from init_irq(), then load the gpio driver from 75 * core_initcall(nmk_gpio_init) and add the platform devices from 76 * arch_initcall(customize_machine). 77 * 78 * This feels fragile because it depends on the gpio device getting probed 79 * _before_ any device uses the gpio interrupts. 80 */ 81 static void __init ux500_init_irq(void) 82 { 83 struct device_node *np; 84 struct resource r; 85 86 irqchip_init(); 87 np = of_find_compatible_node(NULL, NULL, "stericsson,db8500-prcmu"); 88 of_address_to_resource(np, 0, &r); 89 of_node_put(np); 90 if (!r.start) { 91 pr_err("could not find PRCMU base resource\n"); 92 return; 93 } 94 prcmu_early_init(r.start, r.end-r.start); 95 ux500_pm_init(r.start, r.end-r.start); 96 97 /* Unlock before init */ 98 ux500_l2x0_unlock(); 99 outer_cache.write_sec = ux500_l2c310_write_sec; 100 } 101 102 static void ux500_restart(enum reboot_mode mode, const char *cmd) 103 { 104 local_irq_disable(); 105 local_fiq_disable(); 106 107 prcmu_system_reset(0); 108 } 109 110 static const struct of_device_id u8500_local_bus_nodes[] = { 111 /* only create devices below soc node */ 112 { .compatible = "stericsson,db8500", }, 113 { .compatible = "simple-bus"}, 114 { }, 115 }; 116 117 static void __init u8500_init_machine(void) 118 { 119 /* Initialize ux500 power domains */ 120 ux500_pm_domains_init(); 121 122 of_platform_populate(NULL, u8500_local_bus_nodes, 123 NULL, NULL); 124 } 125 126 static const char * stericsson_dt_platform_compat[] = { 127 "st-ericsson,u8500", 128 "st-ericsson,u9500", 129 NULL, 130 }; 131 132 DT_MACHINE_START(U8500_DT, "ST-Ericsson Ux5x0 platform (Device Tree Support)") 133 .l2c_aux_val = 0, 134 .l2c_aux_mask = ~0, 135 .init_irq = ux500_init_irq, 136 .init_machine = u8500_init_machine, 137 .dt_compat = stericsson_dt_platform_compat, 138 .restart = ux500_restart, 139 MACHINE_END 140