1 /* 2 * Copyright (C) 2008-2009 ST-Ericsson 3 * 4 * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2, as 8 * published by the Free Software Foundation. 9 * 10 */ 11 #include <linux/types.h> 12 #include <linux/init.h> 13 #include <linux/device.h> 14 #include <linux/amba/bus.h> 15 #include <linux/interrupt.h> 16 #include <linux/irq.h> 17 #include <linux/gpio.h> 18 #include <linux/platform_device.h> 19 #include <linux/io.h> 20 21 #include <asm/mach/map.h> 22 #include <asm/pmu.h> 23 #include <mach/hardware.h> 24 #include <mach/setup.h> 25 #include <mach/devices.h> 26 27 #include "devices-db8500.h" 28 29 /* minimum static i/o mapping required to boot U8500 platforms */ 30 static struct map_desc u8500_uart_io_desc[] __initdata = { 31 __IO_DEV_DESC(U8500_UART0_BASE, SZ_4K), 32 __IO_DEV_DESC(U8500_UART2_BASE, SZ_4K), 33 }; 34 35 static struct map_desc u8500_io_desc[] __initdata = { 36 __IO_DEV_DESC(U8500_GIC_CPU_BASE, SZ_4K), 37 __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K), 38 __IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K), 39 __IO_DEV_DESC(U8500_TWD_BASE, SZ_4K), 40 __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), 41 __IO_DEV_DESC(U8500_SCU_BASE, SZ_4K), 42 __IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K), 43 44 __IO_DEV_DESC(U8500_CLKRST1_BASE, SZ_4K), 45 __IO_DEV_DESC(U8500_CLKRST2_BASE, SZ_4K), 46 __IO_DEV_DESC(U8500_CLKRST3_BASE, SZ_4K), 47 __IO_DEV_DESC(U8500_CLKRST5_BASE, SZ_4K), 48 __IO_DEV_DESC(U8500_CLKRST6_BASE, SZ_4K), 49 50 __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K), 51 __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K), 52 __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K), 53 __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K), 54 __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K), 55 }; 56 57 static struct map_desc u8500_ed_io_desc[] __initdata = { 58 __IO_DEV_DESC(U8500_MTU0_BASE_ED, SZ_4K), 59 __IO_DEV_DESC(U8500_CLKRST7_BASE_ED, SZ_8K), 60 }; 61 62 static struct map_desc u8500_v1_io_desc[] __initdata = { 63 __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), 64 __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE_V1, SZ_4K), 65 }; 66 67 static struct map_desc u8500_v2_io_desc[] __initdata = { 68 __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K), 69 }; 70 71 void __init u8500_map_io(void) 72 { 73 /* 74 * Map the UARTs early so that the DEBUG_LL stuff continues to work. 75 */ 76 iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc)); 77 78 ux500_map_io(); 79 80 iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); 81 82 if (cpu_is_u8500ed()) 83 iotable_init(u8500_ed_io_desc, ARRAY_SIZE(u8500_ed_io_desc)); 84 else if (cpu_is_u8500v1()) 85 iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc)); 86 else if (cpu_is_u8500v2()) 87 iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc)); 88 } 89 90 static struct resource db8500_pmu_resources[] = { 91 [0] = { 92 .start = IRQ_DB8500_PMU, 93 .end = IRQ_DB8500_PMU, 94 .flags = IORESOURCE_IRQ, 95 }, 96 }; 97 98 /* 99 * The PMU IRQ lines of two cores are wired together into a single interrupt. 100 * Bounce the interrupt to the other core if it's not ours. 101 */ 102 static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler) 103 { 104 irqreturn_t ret = handler(irq, dev); 105 int other = !smp_processor_id(); 106 107 if (ret == IRQ_NONE && cpu_online(other)) 108 irq_set_affinity(irq, cpumask_of(other)); 109 110 /* 111 * We should be able to get away with the amount of IRQ_NONEs we give, 112 * while still having the spurious IRQ detection code kick in if the 113 * interrupt really starts hitting spuriously. 114 */ 115 return ret; 116 } 117 118 static struct arm_pmu_platdata db8500_pmu_platdata = { 119 .handle_irq = db8500_pmu_handler, 120 }; 121 122 static struct platform_device db8500_pmu_device = { 123 .name = "arm-pmu", 124 .id = ARM_PMU_DEVICE_CPU, 125 .num_resources = ARRAY_SIZE(db8500_pmu_resources), 126 .resource = db8500_pmu_resources, 127 .dev.platform_data = &db8500_pmu_platdata, 128 }; 129 130 static struct platform_device *platform_devs[] __initdata = { 131 &u8500_dma40_device, 132 &db8500_pmu_device, 133 }; 134 135 static resource_size_t __initdata db8500_gpio_base[] = { 136 U8500_GPIOBANK0_BASE, 137 U8500_GPIOBANK1_BASE, 138 U8500_GPIOBANK2_BASE, 139 U8500_GPIOBANK3_BASE, 140 U8500_GPIOBANK4_BASE, 141 U8500_GPIOBANK5_BASE, 142 U8500_GPIOBANK6_BASE, 143 U8500_GPIOBANK7_BASE, 144 U8500_GPIOBANK8_BASE, 145 }; 146 147 static void __init db8500_add_gpios(void) 148 { 149 struct nmk_gpio_platform_data pdata = { 150 /* No custom data yet */ 151 }; 152 153 dbx500_add_gpios(ARRAY_AND_SIZE(db8500_gpio_base), 154 IRQ_DB8500_GPIO0, &pdata); 155 } 156 157 /* 158 * This function is called from the board init 159 */ 160 void __init u8500_init_devices(void) 161 { 162 if (cpu_is_u8500ed()) 163 dma40_u8500ed_fixup(); 164 165 db8500_add_rtc(); 166 db8500_add_gpios(); 167 168 platform_device_register_simple("cpufreq-u8500", -1, NULL, 0); 169 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); 170 171 return ; 172 } 173